2 * Copyright (C) 2017 Andes Technology Corporation
3 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _ASM_RISCV_CACHE_H
9 #define _ASM_RISCV_CACHE_H
12 * The current upper bound for RISCV L1 data cache line sizes is 32 bytes.
13 * We use that value for aligning DMA buffers unless the board config has
14 * specified an alternate cache line size.
16 #ifdef CONFIG_SYS_CACHELINE_SIZE
17 #define ARCH_DMA_MINALIGN CONFIG_SYS_CACHELINE_SIZE
19 #define ARCH_DMA_MINALIGN 32
22 #endif /* _ASM_RISCV_CACHE_H */