arch/riscv/dts/microchip-mpfs-icicle-kit.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5 #include "dt-bindings/clock/microchip-mpfs-clock.h"
   6
   7 /* Clock frequency (in Hz) of the rtcclk */
   8 #define RTCCLK_FREQ             1000000
   9
  10 / {
  11         #address-cells = <2>;
  12         #size-cells = <2>;
  13         model = "Microchip MPFS Icicle Kit";
  14         compatible = "microchip,mpfs-icicle-kit";
  15
  16         aliases {
  17                 serial0 = &uart0;
  18                 ethernet0 = &emac1;
  19         };
  20
  21         chosen {
  22                 stdout-path = "serial0";
  23         };
  24
  25         cpucomplex: cpus {
  26                 #address-cells = <1>;
  27                 #size-cells = <0>;
  28                 timebase-frequency = <RTCCLK_FREQ>;
  29                 cpu0: cpu@0 {
  30                         clocks = <&clkcfg CLK_CPU>;
  31                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
  32                         device_type = "cpu";
  33                         i-cache-block-size = <64>;
  34                         i-cache-sets = <128>;
  35                         i-cache-size = <16384>;
  36                         reg = <0>;
  37                         riscv,isa = "rv64imac";
  38                         status = "disabled";
  39                         operating-points = <
  40                                 /* kHz  uV */
  41                                 600000  1100000
  42                                 300000   950000
  43                                 150000   750000
  44                         >;
  45                         cpu0intc: interrupt-controller {
  46                                 #interrupt-cells = <1>;
  47                                 compatible = "riscv,cpu-intc";
  48                                 interrupt-controller;
  49                         };
  50                 };
  51                 cpu1: cpu@1 {
  52                         clocks = <&clkcfg CLK_CPU>;
  53                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  54                         d-cache-block-size = <64>;
  55                         d-cache-sets = <64>;
  56                         d-cache-size = <32768>;
  57                         d-tlb-sets = <1>;
  58                         d-tlb-size = <32>;
  59                         device_type = "cpu";
  60                         i-cache-block-size = <64>;
  61                         i-cache-sets = <64>;
  62                         i-cache-size = <32768>;
  63                         i-tlb-sets = <1>;
  64                         i-tlb-size = <32>;
  65                         mmu-type = "riscv,sv39";
  66                         reg = <1>;
  67                         riscv,isa = "rv64imafdc";
  68                         tlb-split;
  69                         status = "okay";
  70                         operating-points = <
  71                                 /* kHz  uV */
  72                                 600000  1100000
  73                                 300000   950000
  74                                 150000   750000
  75                         >;
  76                         cpu1intc: interrupt-controller {
  77                                 #interrupt-cells = <1>;
  78                                 compatible = "riscv,cpu-intc";
  79                                 interrupt-controller;
  80                         };
  81                 };
  82                 cpu2: cpu@2 {
  83                         clocks = <&clkcfg CLK_CPU>;
  84                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  85                         d-cache-block-size = <64>;
  86                         d-cache-sets = <64>;
  87                         d-cache-size = <32768>;
  88                         d-tlb-sets = <1>;
  89                         d-tlb-size = <32>;
  90                         device_type = "cpu";
  91                         i-cache-block-size = <64>;
  92                         i-cache-sets = <64>;
  93                         i-cache-size = <32768>;
  94                         i-tlb-sets = <1>;
  95                         i-tlb-size = <32>;
  96                         mmu-type = "riscv,sv39";
  97                         reg = <2>;
  98                         riscv,isa = "rv64imafdc";
  99                         tlb-split;
 100                         status = "okay";
 101                         operating-points = <
 102                                 /* kHz  uV */
 103                                 600000  1100000
 104                                 300000   950000
 105                                 150000   750000
 106                         >;
 107                         cpu2intc: interrupt-controller {
 108                                 #interrupt-cells = <1>;
 109                                 compatible = "riscv,cpu-intc";
 110                                 interrupt-controller;
 111                         };
 112                 };
 113                 cpu3: cpu@3 {
 114                         clocks = <&clkcfg CLK_CPU>;
 115                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 116                         d-cache-block-size = <64>;
 117                         d-cache-sets = <64>;
 118                         d-cache-size = <32768>;
 119                         d-tlb-sets = <1>;
 120                         d-tlb-size = <32>;
 121                         device_type = "cpu";
 122                         i-cache-block-size = <64>;
 123                         i-cache-sets = <64>;
 124                         i-cache-size = <32768>;
 125                         i-tlb-sets = <1>;
 126                         i-tlb-size = <32>;
 127                         mmu-type = "riscv,sv39";
 128                         reg = <3>;
 129                         riscv,isa = "rv64imafdc";
 130                         tlb-split;
 131                         status = "okay";
 132                         operating-points = <
 133                                 /* kHz  uV */
 134                                 600000  1100000
 135                                 300000   950000
 136                                 150000   750000
 137                         >;
 138                         cpu3intc: interrupt-controller {
 139                                 #interrupt-cells = <1>;
 140                                 compatible = "riscv,cpu-intc";
 141                                 interrupt-controller;
 142                         };
 143                 };
 144                 cpu4: cpu@4 {
 145                         clocks = <&clkcfg CLK_CPU>;
 146                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 147                         d-cache-block-size = <64>;
 148                         d-cache-sets = <64>;
 149                         d-cache-size = <32768>;
 150                         d-tlb-sets = <1>;
 151                         d-tlb-size = <32>;
 152                         device_type = "cpu";
 153                         i-cache-block-size = <64>;
 154                         i-cache-sets = <64>;
 155                         i-cache-size = <32768>;
 156                         i-tlb-sets = <1>;
 157                         i-tlb-size = <32>;
 158                         mmu-type = "riscv,sv39";
 159                         reg = <4>;
 160                         riscv,isa = "rv64imafdc";
 161                         tlb-split;
 162                         status = "okay";
 163                         operating-points = <
 164                                 /* kHz  uV */
 165                                 600000  1100000
 166                                 300000   950000
 167                                 150000   750000
 168                         >;
 169                         cpu4intc: interrupt-controller {
 170                                 #interrupt-cells = <1>;
 171                                 compatible = "riscv,cpu-intc";
 172                                 interrupt-controller;
 173                         };
 174                 };
 175         };
 176         refclk: refclk {
 177                 compatible = "fixed-clock";
 178                 #clock-cells = <0>;
 179                 clock-frequency = <600000000>;
 180                 clock-output-names = "msspllclk";
 181         };
 182         ddr: memory@80000000 {
 183                 device_type = "memory";
 184                 reg = <0x0 0x80000000 0x0 0x40000000>;
 185                 clocks = <&clkcfg CLK_DDRC>;
 186         };
 187         soc: soc {
 188                 #address-cells = <2>;
 189                 #size-cells = <2>;
 190                 compatible = "microchip,mpfs-icicle-kit", "simple-bus";
 191                 ranges;
 192                 clint0: clint@2000000 {
 193                         compatible = "riscv,clint0";
 194                         interrupts-extended = <&cpu0intc 3 &cpu0intc 7
 195                                                 &cpu1intc 3 &cpu1intc 7
 196                                                 &cpu2intc 3 &cpu2intc 7
 197                                                 &cpu3intc 3 &cpu3intc 7
 198                                                 &cpu4intc 3 &cpu4intc 7>;
 199                         reg = <0x0 0x2000000 0x0 0x10000>;
 200                         reg-names = "control";
 201                         clock-frequency = <RTCCLK_FREQ>;
 202                 };
 203                 cachecontroller: cache-controller@2010000 {
 204                         compatible = "sifive,fu540-c000-ccache", "cache";
 205                         cache-block-size = <64>;
 206                         cache-level = <2>;
 207                         cache-sets = <1024>;
 208                         cache-size = <2097152>;
 209                         cache-unified;
 210                         interrupt-parent = <&plic>;
 211                         interrupts = <1 2 3>;
 212                         reg = <0x0 0x2010000 0x0 0x1000>;
 213                 };
 214                 plic: interrupt-controller@c000000 {
 215                         #interrupt-cells = <1>;
 216                         compatible = "sifive,plic-1.0.0";
 217                         reg = <0x0 0xc000000 0x0 0x4000000>;
 218                         riscv,max-priority = <7>;
 219                         riscv,ndev = <186>;
 220                         interrupt-controller;
 221                         interrupts-extended = <
 222                                 &cpu0intc 11
 223                                 &cpu1intc 11 &cpu1intc 9
 224                                 &cpu2intc 11 &cpu2intc 9
 225                                 &cpu3intc 11 &cpu3intc 9
 226                                 &cpu4intc 11 &cpu4intc 9>;
 227                 };
 228                 uart0: serial@20000000 {
 229                         compatible = "ns16550a";
 230                         reg = <0x0 0x20000000 0x0 0x400>;
 231                         reg-io-width = <4>;
 232                         reg-shift = <2>;
 233                         interrupt-parent = <&plic>;
 234                         interrupts = <90>;
 235                         clocks = <&clkcfg CLK_MMUART0>;
 236                         status = "okay";
 237                 };
 238                 clkcfg: clkcfg@20002000 {
 239                         compatible = "microchip,mpfs-clkcfg";
 240                         reg = <0x0 0x20002000 0x0 0x1000>;
 241                         reg-names = "mss_sysreg";
 242                         clocks = <&refclk>;
 243                         #clock-cells = <1>;
 244                         clock-output-names = "cpu", "axi", "ahb", "envm",
 245                                         "mac0", "mac1", "mmc", "timer",
 246                                         "mmuart0", "mmuart1", "mmuart2",
 247                                         "mmuart3", "mmuart4", "spi0", "spi1",
 248                                         "i2c0", "i2c1", "can0", "can1", "usb",
 249                                         "reserved", "rtc", "qspi", "gpio0",
 250                                         "gpio1", "gpio2", "ddrc", "fic0",
 251                                         "fic1", "fic2", "fic3", "athena",
 252                                         "cfm";
 253                 };
 254                 emmc: mmc@20008000 {
 255                         compatible = "cdns,sd4hc";
 256                         reg = <0x0 0x20008000 0x0 0x1000>;
 257                         interrupt-parent = <&plic>;
 258                         interrupts = <88 89>;
 259                         pinctrl-names = "default";
 260                         clocks = <&clkcfg CLK_MMC>;
 261                         bus-width = <4>;
 262                         cap-mmc-highspeed;
 263                         mmc-ddr-3_3v;
 264                         max-frequency = <200000000>;
 265                         non-removable;
 266                         no-sd;
 267                         no-sdio;
 268                         voltage-ranges = <3300 3300>;
 269                         status = "okay";
 270                 };
 271                 sdcard: sd@20008000 {
 272                         compatible = "cdns,sd4hc";
 273                         reg = <0x0 0x20008000 0x0 0x1000>;
 274                         interrupt-parent = <&plic>;
 275                         interrupts = <88>;
 276                         pinctrl-names = "default";
 277                         clocks = <&clkcfg CLK_MMC>;
 278                         bus-width = <4>;
 279                         disable-wp;
 280                         cap-sd-highspeed;
 281                         card-detect-delay = <200>;
 282                         sd-uhs-sdr12;
 283                         sd-uhs-sdr25;
 284                         sd-uhs-sdr50;
 285                         sd-uhs-sdr104;
 286                         max-frequency = <200000000>;
 287                         status = "disabled";
 288                 };
 289                 uart1: serial@20100000 {
 290                         compatible = "ns16550a";
 291                         reg = <0x0 0x20100000 0x0 0x400>;
 292                         reg-io-width = <4>;
 293                         reg-shift = <2>;
 294                         interrupt-parent = <&plic>;
 295                         interrupts = <91>;
 296                         clocks = <&clkcfg CLK_MMUART1>;
 297                         status = "okay";
 298                 };
 299                 uart2: serial@20102000 {
 300                         compatible = "ns16550a";
 301                         reg = <0x0 0x20102000 0x0 0x400>;
 302                         reg-io-width = <4>;
 303                         reg-shift = <2>;
 304                         interrupt-parent = <&plic>;
 305                         interrupts = <92>;
 306                         clocks = <&clkcfg CLK_MMUART2>;
 307                         status = "okay";
 308                 };
 309                 uart3: serial@20104000 {
 310                         compatible = "ns16550a";
 311                         reg = <0x0 0x20104000 0x0 0x400>;
 312                         reg-io-width = <4>;
 313                         reg-shift = <2>;
 314                         interrupt-parent = <&plic>;
 315                         interrupts = <93>;
 316                         clocks = <&clkcfg CLK_MMUART3>;
 317                         status = "okay";
 318                 };
 319                 i2c0: i2c@2010a000 {
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         compatible = "microchip,mpfs-mss-i2c";
 323                         reg = <0x0 0x2010a000 0x0 0x1000>;
 324                         interrupt-parent = <&plic>;
 325                         interrupts = <58>;
 326                         clocks = <&clkcfg CLK_I2C0>;
 327                         status = "disabled";
 328                 };
 329                 i2c1: i2c@2010b000 {
 330                         #address-cells = <1>;
 331                         #size-cells = <0>;
 332                         compatible = "microchip,mpfs-mss-i2c";
 333                         reg = <0x0 0x2010b000 0x0 0x1000>;
 334                         interrupt-parent = <&plic>;
 335                         interrupts = <61>;
 336                         clocks = <&clkcfg CLK_I2C1>;
 337                         status = "disabled";
 338                         pac193x@10 {
 339                                 compatible = "microchip,pac1934";
 340                                 reg = <0x10>;
 341                                 samp-rate = <64>;
 342                                 status = "disabled";
 343                                 ch1: channel0 {
 344                                         uohms-shunt-res = <10000>;
 345                                         rail-name = "VDD";
 346                                         channel_enabled;
 347                                 };
 348                                 ch2: channel1 {
 349                                         uohms-shunt-res = <10000>;
 350                                         rail-name = "VDDA25";
 351                                         channel_enabled;
 352                                 };
 353                                 ch3: channel2 {
 354                                         uohms-shunt-res = <10000>;
 355                                         rail-name = "VDD25";
 356                                         channel_enabled;
 357                                 };
 358                                 ch4: channel3 {
 359                                         uohms-shunt-res = <10000>;
 360                                         rail-name = "VDDA";
 361                                         channel_enabled;
 362                                 };
 363                         };
 364                 };
 365                 emac0: ethernet@20110000 {
 366                         compatible = "microchip,mpfs-mss-gem";
 367                         reg = <0x0 0x20110000 0x0 0x2000>;
 368                         interrupt-parent = <&plic>;
 369                         interrupts = <64 65 66 67>;
 370                         local-mac-address = [56 34 00 FC 00 02];
 371                         phy-mode = "sgmii";
 372                         clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AXI>;
 373                         clock-names = "pclk", "hclk";
 374                         status = "disabled";
 375
 376                         #address-cells = <1>;
 377                         #size-cells = <0>;
 378                         phy-handle = <&phy0>;
 379                         phy0: ethernet-phy@8 {
 380                                 reg = <8>;
 381                                 ti,fifo-depth = <0x01>;
 382                         };
 383                 };
 384                 emac1: ethernet@20112000 {
 385                         compatible = "microchip,mpfs-mss-gem";
 386                         reg = <0x0 0x20112000 0x0 0x2000>;
 387                         interrupt-parent = <&plic>;
 388                         interrupts = <70 71 72 73>;
 389                         local-mac-address = [00 00 00 00 00 00];
 390                         phy-mode = "sgmii";
 391                         clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
 392                         clock-names = "pclk", "hclk";
 393                         status = "okay";
 394
 395                         #address-cells = <1>;
 396                         #size-cells = <0>;
 397                         phy-handle = <&phy1>;
 398                         phy1: ethernet-phy@9 {
 399                                 reg = <9>;
 400                                 ti,fifo-depth = <0x01>;
 401                         };
 402                 };
 403                 gpio: gpio@20122000 {
 404                         compatible = "microchip,mpfs-mss-gpio";
 405                         interrupt-parent = <&plic>;
 406                         interrupts = <13 14 15 16 17 18 19 20 21 22 23 24 25 26
 407                                         27 28 29 30 31 32 33 34 35 36 37 38 39
 408                                         40 41 42 43 44>;
 409                         gpio-controller;
 410                         clocks = <&clkcfg CLK_GPIO2>;
 411                         reg = <0x00 0x20122000 0x0 0x1000>;
 412                         reg-names = "control";
 413                         #gpio-cells = <2>;
 414                         status = "disabled";
 415                 };
 416         };
 417 };