1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-sysctl.h>
7 #include <dt-bindings/mfd/k210-sysctl.h>
8 #include <dt-bindings/pinctrl/k210-pinctrl.h>
9 #include <dt-bindings/reset/k210-sysctl.h>
13 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
14 * wide, and the upper half of all addresses is ignored.
18 compatible = "kendryte,k210";
46 timebase-frequency = <7800000>;
49 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
51 riscv,isa = "rv64imafdgc";
53 i-cache-block-size = <64>;
54 i-cache-size = <0x8000>;
55 d-cache-block-size = <64>;
56 d-cache-size = <0x8000>;
57 clocks = <&sysclk K210_CLK_CPU>;
58 cpu0_intc: interrupt-controller {
59 #interrupt-cells = <1>;
61 compatible = "riscv,cpu-intc";
66 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
68 riscv,isa = "rv64imafdgc";
70 i-cache-block-size = <64>;
71 i-cache-size = <0x8000>;
72 d-cache-block-size = <64>;
73 d-cache-size = <0x8000>;
74 clocks = <&sysclk K210_CLK_CPU>;
75 cpu1_intc: interrupt-controller {
76 #interrupt-cells = <1>;
78 compatible = "riscv,cpu-intc";
83 sram: memory@80000000 {
84 device_type = "memory";
85 compatible = "kendryte,k210-sram";
86 reg = <0x80000000 0x400000>,
87 <0x80400000 0x200000>,
88 <0x80600000 0x200000>;
89 reg-names = "sram0", "sram1", "aisram";
90 clocks = <&sysclk K210_CLK_SRAM0>,
91 <&sysclk K210_CLK_SRAM1>,
92 <&sysclk K210_CLK_AI>;
93 clock-names = "sram0", "sram1", "aisram";
99 compatible = "fixed-clock";
101 clock-frequency = <26000000>;
107 #address-cells = <1>;
109 compatible = "kendryte,k210-soc", "simple-bus";
111 interrupt-parent = <&plic0>;
114 compatible = "kendryte,k210-debug", "riscv,debug";
119 reg = <0x1000 0x1000>;
123 clint0: clint@2000000 {
124 #interrupt-cells = <1>;
125 compatible = "kendryte,k210-clint", "riscv,clint0";
126 reg = <0x2000000 0xC000>;
127 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
128 <&cpu1_intc 3>, <&cpu1_intc 7>;
129 clocks = <&sysclk K210_CLK_CLINT>;
132 plic0: interrupt-controller@C000000 {
133 #interrupt-cells = <1>;
134 compatible = "kendryte,k210-plic", "riscv,plic0";
135 reg = <0xC000000 0x4000000>;
136 interrupt-controller;
137 interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
138 <&cpu1_intc 9>, <&cpu1_intc 11>;
140 riscv,max-priority = <7>;
143 uarths0: serial@38000000 {
144 compatible = "kendryte,k210-uarths", "sifive,uart0";
145 reg = <0x38000000 0x1000>;
147 clocks = <&sysclk K210_CLK_CPU>;
151 gpio0: gpio-controller@38001000 {
152 #interrupt-cells = <2>;
154 compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
155 reg = <0x38001000 0x1000>;
156 interrupt-controller;
157 interrupts = <34 35 36 37 38 39 40 41
158 42 43 44 45 46 47 48 49
159 50 51 52 53 54 55 56 57
160 58 59 60 61 62 63 64 65>;
167 compatible = "kendryte,k210-kpu";
168 reg = <0x40800000 0xc00000>;
170 clocks = <&sysclk K210_CLK_AI>;
175 compatible = "kendryte,k210-fft";
176 reg = <0x42000000 0x400000>;
178 clocks = <&sysclk K210_CLK_FFT>;
179 resets = <&sysrst K210_RST_FFT>;
183 dmac0: dma-controller@50000000 {
184 compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
185 reg = <0x50000000 0x1000>;
186 interrupts = <27 28 29 30 31 32>;
187 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
188 clock-names = "core-clk", "cfgr-clk";
189 resets = <&sysrst K210_RST_DMA>;
191 snps,dma-masters = <2>;
192 snps,data-width = <5>;
193 snps,block-size = <0x200000 0x200000 0x200000
194 0x200000 0x200000 0x200000>;
195 snps,axi-max-burst-len = <256>;
200 #address-cells = <1>;
202 compatible = "kendryte,k210-apb", "simple-pm-bus";
204 clocks = <&sysclk K210_CLK_APB0>;
206 gpio1: gpio-controller@50200000 {
207 #address-cells = <1>;
209 compatible = "kendryte,k210-gpio",
211 reg = <0x50200000 0x80>;
212 clocks = <&sysclk K210_CLK_GPIO>;
213 resets = <&sysrst K210_RST_GPIO>;
218 #interrupt-cells = <2>;
219 compatible = "snps,dw-apb-gpio-port";
221 interrupt-controller;
228 uart1: serial@50210000 {
229 compatible = "kendryte,k210-uart",
231 reg = <0x50210000 0x100>;
233 clocks = <&sysclk K210_CLK_UART1>;
234 resets = <&sysrst K210_RST_UART1>;
244 uart2: serial@50220000 {
245 compatible = "kendryte,k210-uart",
247 reg = <0x50220000 0x100>;
249 clocks = <&sysclk K210_CLK_UART2>;
250 resets = <&sysrst K210_RST_UART2>;
260 uart3: serial@50230000 {
261 compatible = "kendryte,k210-uart",
263 reg = <0x50230000 0x100>;
265 clocks = <&sysclk K210_CLK_UART3>;
266 resets = <&sysrst K210_RST_UART3>;
277 compatible = "canaan,kendryte-k210-spi",
278 "snps,dw-apb-ssi-4.01",
281 reg = <0x50240000 0x100>;
283 clocks = <&sysclk K210_CLK_SPI2>;
284 resets = <&sysrst K210_RST_SPI2>;
285 spi-max-frequency = <25000000>;
290 compatible = "kendryte,k210-i2s",
291 "snps,designware-i2s";
292 reg = <0x50250000 0x200>;
294 clocks = <&sysclk K210_CLK_I2S0>;
295 clock-names = "i2sclk";
296 resets = <&sysrst K210_RST_I2S0>;
300 apu0: sound@520250200 {
301 compatible = "kendryte,k210-apu";
302 reg = <0x50250200 0x200>;
307 compatible = "kendryte,k210-i2s",
308 "snps,designware-i2s";
309 reg = <0x50260000 0x200>;
311 clocks = <&sysclk K210_CLK_I2S1>;
312 clock-names = "i2sclk";
313 resets = <&sysrst K210_RST_I2S1>;
318 compatible = "kendryte,k210-i2s",
319 "snps,designware-i2s";
320 reg = <0x50270000 0x200>;
322 clocks = <&sysclk K210_CLK_I2S2>;
323 clock-names = "i2sclk";
324 resets = <&sysrst K210_RST_I2S2>;
329 compatible = "kendryte,k210-i2c",
330 "snps,designware-i2c";
331 reg = <0x50280000 0x100>;
333 clocks = <&sysclk K210_CLK_I2C0>;
334 resets = <&sysrst K210_RST_I2C0>;
339 compatible = "kendryte,k210-i2c",
340 "snps,designware-i2c";
341 reg = <0x50290000 0x100>;
343 clocks = <&sysclk K210_CLK_I2C1>;
344 resets = <&sysrst K210_RST_I2C1>;
349 compatible = "kendryte,k210-i2c",
350 "snps,designware-i2c";
351 reg = <0x502A0000 0x100>;
353 clocks = <&sysclk K210_CLK_I2C2>;
354 resets = <&sysrst K210_RST_I2C2>;
358 fpioa: pinmux@502B0000 {
359 compatible = "kendryte,k210-fpioa";
360 reg = <0x502B0000 0x100>;
361 clocks = <&sysclk K210_CLK_FPIOA>;
362 resets = <&sysrst K210_RST_FPIOA>;
363 kendryte,sysctl = <&sysctl>;
364 kendryte,power-offset = <K210_SYSCTL_POWER_SEL>;
365 pinctrl-0 = <&fpioa_jtag>;
366 pinctrl-names = "default";
370 pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
371 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
372 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
373 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
377 sha256: sha256@502C0000 {
378 compatible = "kendryte,k210-sha256";
379 reg = <0x502C0000 0x100>;
380 clocks = <&sysclk K210_CLK_SHA>;
381 resets = <&sysrst K210_RST_SHA>;
385 timer0: timer@502D0000 {
386 compatible = "kendryte,k210-timer",
388 reg = <0x502D0000 0x100>;
389 interrupts = <14 15>;
390 clocks = <&sysclk K210_CLK_TIMER0>;
391 clock-names = "timer";
392 resets = <&sysrst K210_RST_TIMER0>;
396 timer1: timer@502E0000 {
397 compatible = "kendryte,k210-timer",
399 reg = <0x502E0000 0x100>;
400 interrupts = <16 17>;
401 clocks = <&sysclk K210_CLK_TIMER1>;
402 clock-names = "timer";
403 resets = <&sysrst K210_RST_TIMER1>;
407 timer2: timer@502F0000 {
408 compatible = "kendryte,k210-timer",
410 reg = <0x502F0000 0x100>;
411 interrupts = <18 19>;
412 clocks = <&sysclk K210_CLK_TIMER2>;
413 clock-names = "timer";
414 resets = <&sysrst K210_RST_TIMER2>;
420 #address-cells = <1>;
422 compatible = "kendryte,k210-apb", "simple-pm-bus";
424 clocks = <&sysclk K210_CLK_APB1>;
426 wdt0: watchdog@50400000 {
427 compatible = "kendryte,k210-wdt", "snps,dw-wdt";
428 reg = <0x50400000 0x100>;
430 clocks = <&sysclk K210_CLK_WDT0>;
431 resets = <&sysrst K210_RST_WDT0>;
434 wdt1: watchdog@50410000 {
435 compatible = "kendryte,k210-wdt", "snps,dw-wdt";
436 reg = <0x50410000 0x100>;
438 clocks = <&sysclk K210_CLK_WDT1>;
439 resets = <&sysrst K210_RST_WDT1>;
443 otp0: nvmem@50420000 {
444 #address-cells = <1>;
446 compatible = "kendryte,k210-otp";
447 reg = <0x50420000 0x100>,
448 <0x88000000 0x20000>;
449 reg-names = "reg", "mem";
450 clocks = <&sysclk K210_CLK_ROM>;
451 resets = <&sysrst K210_RST_ROM>;
457 reg = <0x00000 0xC200>;
461 * config string as described in RISC-V
462 * privileged spec 1.9
465 reg = <0x1C000 0x1000>;
469 * Device tree containing only registers,
470 * interrupts, and cpus
473 reg = <0x1D000 0x2000>;
476 /* CPU/ROM credits */
478 reg = <0x1F000 0x1000>;
482 dvp0: camera@50430000 {
483 compatible = "kendryte,k210-dvp";
484 reg = <0x50430000 0x100>;
486 clocks = <&sysclk K210_CLK_DVP>;
487 resets = <&sysrst K210_RST_DVP>;
488 kendryte,sysctl = <&sysctl>;
489 kendryte,misc-offset = <K210_SYSCTL_MISC>;
493 sysctl: syscon@50440000 {
494 compatible = "kendryte,k210-sysctl",
495 "syscon", "simple-mfd";
496 reg = <0x50440000 0x100>;
500 sysclk: clock-controller {
502 compatible = "kendryte,k210-clk";
507 sysrst: reset-controller {
508 compatible = "kendryte,k210-rst",
512 offset = <K210_SYSCTL_PERI_RESET>;
518 compatible = "syscon-reboot";
520 offset = <K210_SYSCTL_SOFT_RESET>;
527 compatible = "kendryte,k210-aes";
528 reg = <0x50450000 0x100>;
529 clocks = <&sysclk K210_CLK_AES>;
530 resets = <&sysrst K210_RST_AES>;
535 compatible = "kendryte,k210-rtc";
536 reg = <0x50460000 0x100>;
538 resets = <&sysrst K210_RST_RTC>;
545 #address-cells = <1>;
547 compatible = "kendryte,k210-apb", "simple-pm-bus";
549 clocks = <&sysclk K210_CLK_APB2>;
552 #address-cells = <1>;
554 compatible = "canaan,kendryte-k210-spi",
555 "snps,dw-apb-ssi-4.01",
557 reg = <0x52000000 0x100>;
559 clocks = <&sysclk K210_CLK_SPI0>;
560 clock-names = "ssi_clk";
561 resets = <&sysrst K210_RST_SPI0>;
562 spi-max-frequency = <25000000>;
569 #address-cells = <1>;
571 compatible = "canaan,kendryte-k210-spi",
572 "snps,dw-apb-ssi-4.01",
574 reg = <0x53000000 0x100>;
576 clocks = <&sysclk K210_CLK_SPI1>;
577 clock-names = "ssi_clk";
578 resets = <&sysrst K210_RST_SPI1>;
579 spi-max-frequency = <25000000>;
586 #address-cells = <1>;
588 compatible = "canaan,kendryte-k210-ssi",
589 "snps,dwc-ssi-1.01a";
590 reg = <0x54000000 0x200>;
592 clocks = <&sysclk K210_CLK_SPI3>;
593 clock-names = "ssi_clk";
594 resets = <&sysrst K210_RST_SPI3>;
595 /* Could possibly go up to 200 MHz */
596 spi-max-frequency = <100000000>;