1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com>
6 #include <dt-bindings/clock/k210-sysctl.h>
7 #include <dt-bindings/mfd/k210-sysctl.h>
8 #include <dt-bindings/pinctrl/k210-pinctrl.h>
9 #include <dt-bindings/reset/k210-sysctl.h>
13 * Although the K210 is a 64-bit CPU, the address bus is only 32-bits
14 * wide, and the upper half of all addresses is ignored.
18 compatible = "kendryte,k210";
46 timebase-frequency = <7800000>;
49 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
51 riscv,isa = "rv64imafdgc";
53 i-cache-block-size = <64>;
54 i-cache-size = <0x8000>;
55 d-cache-block-size = <64>;
56 d-cache-size = <0x8000>;
57 clocks = <&sysclk K210_CLK_CPU>;
58 cpu0_intc: interrupt-controller {
59 #interrupt-cells = <1>;
61 compatible = "riscv,cpu-intc";
66 compatible = "kendryte,k210", "sifive,rocket0", "riscv";
68 riscv,isa = "rv64imafdgc";
70 i-cache-block-size = <64>;
71 i-cache-size = <0x8000>;
72 d-cache-block-size = <64>;
73 d-cache-size = <0x8000>;
74 clocks = <&sysclk K210_CLK_CPU>;
75 cpu1_intc: interrupt-controller {
76 #interrupt-cells = <1>;
78 compatible = "riscv,cpu-intc";
83 sram: memory@80000000 {
84 device_type = "memory";
85 compatible = "kendryte,k210-sram";
86 reg = <0x80000000 0x400000>,
87 <0x80400000 0x200000>,
88 <0x80600000 0x200000>;
89 reg-names = "sram0", "sram1", "airam";
90 clocks = <&sysclk K210_CLK_SRAM0>,
91 <&sysclk K210_CLK_SRAM1>,
92 <&sysclk K210_CLK_PLL1>;
93 clock-names = "sram0", "sram1", "airam";
101 ai_reserved: ai@80600000 {
102 reg = <0x80600000 0x200000>;
109 compatible = "fixed-clock";
111 clock-frequency = <26000000>;
116 #address-cells = <1>;
118 compatible = "kendryte,k210-soc", "simple-bus";
120 interrupt-parent = <&plic0>;
123 compatible = "kendryte,k210-debug", "riscv,debug";
128 reg = <0x1000 0x1000>;
132 clint0: clint@2000000 {
133 #interrupt-cells = <1>;
134 compatible = "kendryte,k210-clint", "riscv,clint0";
135 reg = <0x2000000 0xC000>;
136 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
137 <&cpu1_intc 3>, <&cpu1_intc 7>;
138 clocks = <&sysclk K210_CLK_CLINT>;
141 plic0: interrupt-controller@C000000 {
142 #interrupt-cells = <1>;
143 compatible = "kendryte,k210-plic", "riscv,plic0";
144 reg = <0xC000000 0x4000000>;
145 interrupt-controller;
146 interrupts-extended = <&cpu0_intc 9>, <&cpu0_intc 11>,
147 <&cpu1_intc 9>, <&cpu1_intc 11>;
149 riscv,max-priority = <7>;
152 uarths0: serial@38000000 {
153 compatible = "kendryte,k210-uarths", "sifive,uart0";
154 reg = <0x38000000 0x1000>;
156 clocks = <&sysclk K210_CLK_CPU>;
160 gpio0: gpio-controller@38001000 {
161 #interrupt-cells = <2>;
163 compatible = "kendryte,k210-gpiohs", "sifive,gpio0";
164 reg = <0x38001000 0x1000>;
165 interrupt-controller;
166 interrupts = <34 35 36 37 38 39 40 41
167 42 43 44 45 46 47 48 49
168 50 51 52 53 54 55 56 57
169 58 59 60 61 62 63 64 65>;
176 compatible = "kendryte,k210-kpu";
177 reg = <0x40800000 0xc00000>;
179 clocks = <&sysclk K210_CLK_AI>;
180 memory-region = <&ai_reserved>;
185 compatible = "kendryte,k210-fft";
186 reg = <0x42000000 0x400000>;
188 clocks = <&sysclk K210_CLK_FFT>;
189 resets = <&sysrst K210_RST_FFT>;
193 dmac0: dma-controller@50000000 {
194 compatible = "kendryte,k210-dmac", "snps,axi-dma-1.01a";
195 reg = <0x50000000 0x1000>;
196 interrupts = <27 28 29 30 31 32>;
197 clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
198 clock-names = "core-clk", "cfgr-clk";
199 resets = <&sysrst K210_RST_DMA>;
201 snps,dma-masters = <2>;
202 snps,data-width = <5>;
203 snps,block-size = <0x400000 0x400000 0x400000
204 0x400000 0x400000 0x400000>;
205 snps,axi-max-burst-len = <256>;
210 #address-cells = <1>;
212 compatible = "kendryte,k210-apb", "simple-pm-bus";
214 clocks = <&sysclk K210_CLK_APB0>;
216 gpio1: gpio-controller@50200000 {
217 #address-cells = <1>;
219 compatible = "kendryte,k210-gpio",
221 reg = <0x50200000 0x80>;
222 clocks = <&sysclk K210_CLK_GPIO>;
223 resets = <&sysrst K210_RST_GPIO>;
228 #interrupt-cells = <2>;
229 compatible = "snps,dw-apb-gpio-port";
231 interrupt-controller;
238 uart1: serial@50210000 {
239 compatible = "kendryte,k210-uart",
241 reg = <0x50210000 0x100>;
243 clocks = <&sysclk K210_CLK_UART1>;
244 resets = <&sysrst K210_RST_UART1>;
254 uart2: serial@50220000 {
255 compatible = "kendryte,k210-uart",
257 reg = <0x50220000 0x100>;
259 clocks = <&sysclk K210_CLK_UART2>;
260 resets = <&sysrst K210_RST_UART2>;
270 uart3: serial@50230000 {
271 compatible = "kendryte,k210-uart",
273 reg = <0x50230000 0x100>;
275 clocks = <&sysclk K210_CLK_UART3>;
276 resets = <&sysrst K210_RST_UART3>;
287 compatible = "kendryte,k120-spislave",
290 reg = <0x50240000 0x100>;
292 clocks = <&sysclk K210_CLK_SPI2>;
293 resets = <&sysrst K210_RST_SPI2>;
294 spi-max-frequency = <25000000>;
299 compatible = "kendryte,k210-i2s",
300 "snps,designware-i2s";
301 reg = <0x50250000 0x200>;
303 clocks = <&sysclk K210_CLK_I2S0>;
304 clock-names = "i2sclk";
305 resets = <&sysrst K210_RST_I2S0>;
309 apu0: sound@520250200 {
310 compatible = "kendryte,k210-apu";
311 reg = <0x50250200 0x200>;
316 compatible = "kendryte,k210-i2s",
317 "snps,designware-i2s";
318 reg = <0x50260000 0x200>;
320 clocks = <&sysclk K210_CLK_I2S1>;
321 clock-names = "i2sclk";
322 resets = <&sysrst K210_RST_I2S1>;
327 compatible = "kendryte,k210-i2s",
328 "snps,designware-i2s";
329 reg = <0x50270000 0x200>;
331 clocks = <&sysclk K210_CLK_I2S2>;
332 clock-names = "i2sclk";
333 resets = <&sysrst K210_RST_I2S2>;
338 compatible = "kendryte,k210-i2c",
339 "snps,designware-i2c";
340 reg = <0x50280000 0x100>;
342 clocks = <&sysclk K210_CLK_I2C0>;
343 resets = <&sysrst K210_RST_I2C0>;
348 compatible = "kendryte,k210-i2c",
349 "snps,designware-i2c";
350 reg = <0x50290000 0x100>;
352 clocks = <&sysclk K210_CLK_I2C1>;
353 resets = <&sysrst K210_RST_I2C1>;
358 compatible = "kendryte,k210-i2c",
359 "snps,designware-i2c";
360 reg = <0x502A0000 0x100>;
362 clocks = <&sysclk K210_CLK_I2C2>;
363 resets = <&sysrst K210_RST_I2C2>;
367 fpioa: pinmux@502B0000 {
368 compatible = "kendryte,k210-fpioa";
369 reg = <0x502B0000 0x100>;
370 clocks = <&sysclk K210_CLK_FPIOA>;
371 resets = <&sysrst K210_RST_FPIOA>;
372 kendryte,sysctl = <&sysctl>;
373 kendryte,power-offset = <K210_SYSCTL_POWER_SEL>;
374 pinctrl-0 = <&fpioa_jtag>;
375 pinctrl-names = "default";
379 pinmux = <K210_FPIOA(0, K210_PCF_JTAG_TCLK)>,
380 <K210_FPIOA(1, K210_PCF_JTAG_TDI)>,
381 <K210_FPIOA(2, K210_PCF_JTAG_TMS)>,
382 <K210_FPIOA(3, K210_PCF_JTAG_TDO)>;
386 sha256: sha256@502C0000 {
387 compatible = "kendryte,k210-sha256";
388 reg = <0x502C0000 0x100>;
389 clocks = <&sysclk K210_CLK_SHA>;
390 resets = <&sysrst K210_RST_SHA>;
394 timer0: timer@502D0000 {
395 compatible = "kendryte,k210-timer",
397 reg = <0x502D0000 0x100>;
398 interrupts = <14 15>;
399 clocks = <&sysclk K210_CLK_TIMER0>;
400 clock-names = "timer";
401 resets = <&sysrst K210_RST_TIMER0>;
405 timer1: timer@502E0000 {
406 compatible = "kendryte,k210-timer",
408 reg = <0x502E0000 0x100>;
409 interrupts = <16 17>;
410 clocks = <&sysclk K210_CLK_TIMER1>;
411 clock-names = "timer";
412 resets = <&sysrst K210_RST_TIMER1>;
416 timer2: timer@502F0000 {
417 compatible = "kendryte,k210-timer",
419 reg = <0x502F0000 0x100>;
420 interrupts = <18 19>;
421 clocks = <&sysclk K210_CLK_TIMER2>;
422 clock-names = "timer";
423 resets = <&sysrst K210_RST_TIMER2>;
429 #address-cells = <1>;
431 compatible = "kendryte,k210-apb", "simple-pm-bus";
433 clocks = <&sysclk K210_CLK_APB1>;
435 wdt0: watchdog@50400000 {
436 compatible = "kendryte,k210-wdt", "snps,dw-wdt";
437 reg = <0x50400000 0x100>;
439 clocks = <&sysclk K210_CLK_WDT0>;
440 resets = <&sysrst K210_RST_WDT0>;
444 wdt1: watchdog@50410000 {
445 compatible = "kendryte,k210-wdt", "snps,dw-wdt";
446 reg = <0x50410000 0x100>;
448 clocks = <&sysclk K210_CLK_WDT1>;
449 resets = <&sysrst K210_RST_WDT1>;
453 otp0: nvmem@50420000 {
454 #address-cells = <1>;
456 compatible = "kendryte,k210-otp";
457 reg = <0x50420000 0x100>,
458 <0x88000000 0x20000>;
459 reg-names = "reg", "mem";
460 clocks = <&sysclk K210_CLK_ROM>;
461 resets = <&sysrst K210_RST_ROM>;
467 reg = <0x00000 0xC200>;
471 * config string as described in RISC-V
472 * privileged spec 1.9
475 reg = <0x1C000 0x1000>;
479 * Device tree containing only registers,
480 * interrupts, and cpus
483 reg = <0x1D000 0x2000>;
486 /* CPU/ROM credits */
488 reg = <0x1F000 0x1000>;
492 dvp0: camera@50430000 {
493 compatible = "kendryte,k210-dvp";
494 reg = <0x50430000 0x100>;
496 clocks = <&sysclk K210_CLK_DVP>;
497 resets = <&sysrst K210_RST_DVP>;
501 sysctl: syscon@50440000 {
502 compatible = "kendryte,k210-sysctl",
503 "syscon", "simple-mfd";
504 reg = <0x50440000 0x100>;
507 sysclk: clock-controller {
509 compatible = "kendryte,k210-clk";
513 sysrst: reset-controller {
514 compatible = "kendryte,k210-rst",
518 offset = <K210_SYSCTL_PERI_RESET>;
524 compatible = "syscon-reboot";
526 offset = <K210_SYSCTL_SOFT_RESET>;
533 compatible = "kendryte,k210-aes";
534 reg = <0x50450000 0x100>;
535 clocks = <&sysclk K210_CLK_AES>;
536 resets = <&sysrst K210_RST_AES>;
541 compatible = "kendryte,k210-rtc";
542 reg = <0x50460000 0x100>;
544 resets = <&sysrst K210_RST_RTC>;
551 #address-cells = <1>;
553 compatible = "kendryte,k210-apb", "simple-pm-bus";
555 clocks = <&sysclk K210_CLK_APB2>;
558 #address-cells = <1>;
560 compatible = "kendryte,k210-spi",
562 reg = <0x52000000 0x100>;
564 clocks = <&sysclk K210_CLK_SPI0>;
565 clock-names = "ssi_clk";
566 resets = <&sysrst K210_RST_SPI0>;
567 spi-max-frequency = <25000000>;
574 #address-cells = <1>;
576 compatible = "kendryte,k210-spi",
578 reg = <0x53000000 0x100>;
580 clocks = <&sysclk K210_CLK_SPI1>;
581 clock-names = "ssi_clk";
582 resets = <&sysrst K210_RST_SPI1>;
583 spi-max-frequency = <25000000>;
590 #address-cells = <1>;
592 compatible = "kendryte,k210-spi",
594 reg = <0x54000000 0x200>;
596 clocks = <&sysclk K210_CLK_SPI3>;
597 clock-names = "ssi_clk";
598 resets = <&sysrst K210_RST_SPI3>;
599 /* Could possibly go up to 200 MHz */
600 spi-max-frequency = <100000000>;