1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
7 #include <dt-bindings/clock/starfive,jh7110-crg.h>
8 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 compatible = "starfive,jh7110";
20 compatible = "sifive,s7", "riscv";
23 i-cache-block-size = <64>;
25 i-cache-size = <16384>;
26 next-level-cache = <&ccache>;
27 riscv,isa = "rv64imac_zba_zbb";
30 cpu0_intc: interrupt-controller {
31 compatible = "riscv,cpu-intc";
33 #interrupt-cells = <1>;
38 compatible = "sifive,u74-mc", "riscv";
40 d-cache-block-size = <64>;
42 d-cache-size = <32768>;
46 i-cache-block-size = <64>;
48 i-cache-size = <32768>;
51 mmu-type = "riscv,sv39";
52 next-level-cache = <&ccache>;
53 riscv,isa = "rv64imafdc_zba_zbb";
56 cpu1_intc: interrupt-controller {
57 compatible = "riscv,cpu-intc";
59 #interrupt-cells = <1>;
64 compatible = "sifive,u74-mc", "riscv";
66 d-cache-block-size = <64>;
68 d-cache-size = <32768>;
72 i-cache-block-size = <64>;
74 i-cache-size = <32768>;
77 mmu-type = "riscv,sv39";
78 next-level-cache = <&ccache>;
79 riscv,isa = "rv64imafdc_zba_zbb";
82 cpu2_intc: interrupt-controller {
83 compatible = "riscv,cpu-intc";
85 #interrupt-cells = <1>;
90 compatible = "sifive,u74-mc", "riscv";
92 d-cache-block-size = <64>;
94 d-cache-size = <32768>;
98 i-cache-block-size = <64>;
100 i-cache-size = <32768>;
103 mmu-type = "riscv,sv39";
104 next-level-cache = <&ccache>;
105 riscv,isa = "rv64imafdc_zba_zbb";
108 cpu3_intc: interrupt-controller {
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
111 #interrupt-cells = <1>;
116 compatible = "sifive,u74-mc", "riscv";
118 d-cache-block-size = <64>;
120 d-cache-size = <32768>;
124 i-cache-block-size = <64>;
126 i-cache-size = <32768>;
129 mmu-type = "riscv,sv39";
130 next-level-cache = <&ccache>;
131 riscv,isa = "rv64imafdc_zba_zbb";
134 cpu4_intc: interrupt-controller {
135 compatible = "riscv,cpu-intc";
136 interrupt-controller;
137 #interrupt-cells = <1>;
167 compatible = "riscv,timer";
168 interrupts-extended = <&cpu0_intc 5>,
176 compatible = "fixed-clock";
177 clock-output-names = "osc";
181 rtc_osc: rtc-oscillator {
182 compatible = "fixed-clock";
183 clock-output-names = "rtc_osc";
187 gmac0_rmii_refin: gmac0-rmii-refin-clock {
188 compatible = "fixed-clock";
189 clock-output-names = "gmac0_rmii_refin";
193 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
194 compatible = "fixed-clock";
195 clock-output-names = "gmac0_rgmii_rxin";
199 gmac1_rmii_refin: gmac1-rmii-refin-clock {
200 compatible = "fixed-clock";
201 clock-output-names = "gmac1_rmii_refin";
205 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
206 compatible = "fixed-clock";
207 clock-output-names = "gmac1_rgmii_rxin";
211 i2stx_bclk_ext: i2stx-bclk-ext-clock {
212 compatible = "fixed-clock";
213 clock-output-names = "i2stx_bclk_ext";
217 i2stx_lrck_ext: i2stx-lrck-ext-clock {
218 compatible = "fixed-clock";
219 clock-output-names = "i2stx_lrck_ext";
223 i2srx_bclk_ext: i2srx-bclk-ext-clock {
224 compatible = "fixed-clock";
225 clock-output-names = "i2srx_bclk_ext";
229 i2srx_lrck_ext: i2srx-lrck-ext-clock {
230 compatible = "fixed-clock";
231 clock-output-names = "i2srx_lrck_ext";
235 tdm_ext: tdm-ext-clock {
236 compatible = "fixed-clock";
237 clock-output-names = "tdm_ext";
241 mclk_ext: mclk-ext-clock {
242 compatible = "fixed-clock";
243 clock-output-names = "mclk_ext";
247 stmmac_axi_setup: stmmac-axi-config {
249 snps,wr_osr_lmt = <4>;
250 snps,rd_osr_lmt = <4>;
251 snps,blen = <256 128 64 32 0 0 0>;
255 compatible = "simple-bus";
256 interrupt-parent = <&plic>;
257 #address-cells = <2>;
261 clint: timer@2000000 {
262 compatible = "starfive,jh7110-clint", "sifive,clint0";
263 reg = <0x0 0x2000000 0x0 0x10000>;
264 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
265 <&cpu1_intc 3>, <&cpu1_intc 7>,
266 <&cpu2_intc 3>, <&cpu2_intc 7>,
267 <&cpu3_intc 3>, <&cpu3_intc 7>,
268 <&cpu4_intc 3>, <&cpu4_intc 7>;
271 plic: interrupt-controller@c000000 {
272 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
273 reg = <0x0 0xc000000 0x0 0x4000000>;
274 interrupts-extended = <&cpu0_intc 11>,
275 <&cpu1_intc 11>, <&cpu1_intc 9>,
276 <&cpu2_intc 11>, <&cpu2_intc 9>,
277 <&cpu3_intc 11>, <&cpu3_intc 9>,
278 <&cpu4_intc 11>, <&cpu4_intc 9>;
279 interrupt-controller;
280 #interrupt-cells = <1>;
281 #address-cells = <0>;
285 ccache: cache-controller@2010000 {
286 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
287 reg = <0x0 0x2010000 0x0 0x4000>;
288 interrupts = <1>, <3>, <4>, <2>;
289 cache-block-size = <64>;
292 cache-size = <2097152>;
296 uart0: serial@10000000 {
297 compatible = "snps,dw-apb-uart";
298 reg = <0x0 0x10000000 0x0 0x10000>;
299 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
300 <&syscrg JH7110_SYSCLK_UART0_APB>;
301 clock-names = "baudclk", "apb_pclk";
302 resets = <&syscrg JH7110_SYSRST_UART0_APB>,
303 <&syscrg JH7110_SYSRST_UART0_CORE>;
310 uart1: serial@10010000 {
311 compatible = "snps,dw-apb-uart";
312 reg = <0x0 0x10010000 0x0 0x10000>;
313 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
314 <&syscrg JH7110_SYSCLK_UART1_APB>;
315 clock-names = "baudclk", "apb_pclk";
316 resets = <&syscrg JH7110_SYSRST_UART1_APB>,
317 <&syscrg JH7110_SYSRST_UART1_CORE>;
324 uart2: serial@10020000 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0x0 0x10020000 0x0 0x10000>;
327 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
328 <&syscrg JH7110_SYSCLK_UART2_APB>;
329 clock-names = "baudclk", "apb_pclk";
330 resets = <&syscrg JH7110_SYSRST_UART2_APB>,
331 <&syscrg JH7110_SYSRST_UART2_CORE>;
339 compatible = "snps,designware-i2c";
340 reg = <0x0 0x10030000 0x0 0x10000>;
341 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
343 resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
345 #address-cells = <1>;
351 compatible = "snps,designware-i2c";
352 reg = <0x0 0x10040000 0x0 0x10000>;
353 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
355 resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
357 #address-cells = <1>;
363 compatible = "snps,designware-i2c";
364 reg = <0x0 0x10050000 0x0 0x10000>;
365 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
367 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
369 #address-cells = <1>;
374 stgcrg: clock-controller@10230000 {
375 compatible = "starfive,jh7110-stgcrg";
376 reg = <0x0 0x10230000 0x0 0x10000>;
381 stg_syscon: stg_syscon@10240000 {
382 compatible = "starfive,jh7110-stg-syscon","syscon";
383 reg = <0x0 0x10240000 0x0 0x1000>;
386 uart3: serial@12000000 {
387 compatible = "snps,dw-apb-uart";
388 reg = <0x0 0x12000000 0x0 0x10000>;
389 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
390 <&syscrg JH7110_SYSCLK_UART3_APB>;
391 clock-names = "baudclk", "apb_pclk";
392 resets = <&syscrg JH7110_SYSRST_UART3_APB>,
393 <&syscrg JH7110_SYSRST_UART3_CORE>;
400 uart4: serial@12010000 {
401 compatible = "snps,dw-apb-uart";
402 reg = <0x0 0x12010000 0x0 0x10000>;
403 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
404 <&syscrg JH7110_SYSCLK_UART4_APB>;
405 clock-names = "baudclk", "apb_pclk";
406 resets = <&syscrg JH7110_SYSRST_UART4_APB>,
407 <&syscrg JH7110_SYSRST_UART4_CORE>;
414 uart5: serial@12020000 {
415 compatible = "snps,dw-apb-uart";
416 reg = <0x0 0x12020000 0x0 0x10000>;
417 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
418 <&syscrg JH7110_SYSCLK_UART5_APB>;
419 clock-names = "baudclk", "apb_pclk";
420 resets = <&syscrg JH7110_SYSRST_UART5_APB>,
421 <&syscrg JH7110_SYSRST_UART5_CORE>;
429 compatible = "snps,designware-i2c";
430 reg = <0x0 0x12030000 0x0 0x10000>;
431 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
433 resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
435 #address-cells = <1>;
441 compatible = "snps,designware-i2c";
442 reg = <0x0 0x12040000 0x0 0x10000>;
443 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
445 resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
447 #address-cells = <1>;
453 compatible = "snps,designware-i2c";
454 reg = <0x0 0x12050000 0x0 0x10000>;
455 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
457 resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
459 #address-cells = <1>;
465 compatible = "snps,designware-i2c";
466 reg = <0x0 0x12060000 0x0 0x10000>;
467 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
469 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
471 #address-cells = <1>;
477 compatible = "cdns,qspi-nor";
478 reg = <0x0 0x13010000 0x0 0x10000
479 0x0 0x21000000 0x0 0x400000>;
480 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
481 clock-names = "clk_ref";
482 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
483 <&syscrg JH7110_SYSRST_QSPI_AHB>,
484 <&syscrg JH7110_SYSRST_QSPI_REF>;
485 reset-names = "rst_apb", "rst_ahb", "rst_ref";
486 cdns,fifo-depth = <256>;
487 cdns,fifo-width = <4>;
488 #address-cells = <1>;
492 syscrg: clock-controller@13020000 {
493 compatible = "starfive,jh7110-syscrg";
494 reg = <0x0 0x13020000 0x0 0x10000>;
495 clocks = <&osc>, <&gmac1_rmii_refin>,
497 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
498 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
499 <&tdm_ext>, <&mclk_ext>,
500 <&pllclk JH7110_SYSCLK_PLL0_OUT>,
501 <&pllclk JH7110_SYSCLK_PLL1_OUT>,
502 <&pllclk JH7110_SYSCLK_PLL2_OUT>;
503 clock-names = "osc", "gmac1_rmii_refin",
505 "i2stx_bclk_ext", "i2stx_lrck_ext",
506 "i2srx_bclk_ext", "i2srx_lrck_ext",
507 "tdm_ext", "mclk_ext",
508 "pll0_out", "pll1_out", "pll2_out";
513 sys_syscon: sys_syscon@13030000 {
514 compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
515 reg = <0x0 0x13030000 0x0 0x1000>;
517 pllclk: clock-controller {
518 compatible = "starfive,jh7110-pll";
524 sysgpio: pinctrl@13040000 {
525 compatible = "starfive,jh7110-sys-pinctrl";
526 reg = <0x0 0x13040000 0x0 0x10000>;
527 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
528 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
530 interrupt-controller;
531 #interrupt-cells = <2>;
537 compatible = "starfive,jh7110-mmc";
538 reg = <0x0 0x16010000 0x0 0x10000>;
539 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
540 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
541 clock-names = "biu", "ciu";
542 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
543 reset-names = "reset";
546 fifo-watermark-aligned;
548 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
553 compatible = "starfive,jh7110-mmc";
554 reg = <0x0 0x16020000 0x0 0x10000>;
555 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
556 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
557 clock-names = "biu", "ciu";
558 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
559 reset-names = "reset";
562 fifo-watermark-aligned;
564 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
568 gmac0: ethernet@16030000 {
569 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
570 reg = <0x0 0x16030000 0x0 0x10000>;
571 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
572 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
573 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
574 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
575 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
576 clock-names = "stmmaceth", "pclk", "ptp_ref",
578 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
579 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
580 reset-names = "stmmaceth", "ahb";
581 interrupts = <7>, <6>, <5>;
582 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
583 snps,multicast-filter-bins = <64>;
584 snps,perfect-filter-entries = <8>;
585 rx-fifo-depth = <2048>;
586 tx-fifo-depth = <2048>;
589 snps,force_thresh_dma_mode;
590 snps,axi-config = <&stmmac_axi_setup>;
592 snps,en-tx-lpi-clockgating;
595 starfive,syscon = <&aon_syscon 0xc 0x12>;
599 gmac1: ethernet@16040000 {
600 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
601 reg = <0x0 0x16040000 0x0 0x10000>;
602 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
603 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
604 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
605 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
606 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
607 clock-names = "stmmaceth", "pclk", "ptp_ref",
609 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
610 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
611 reset-names = "stmmaceth", "ahb";
612 interrupts = <78>, <77>, <76>;
613 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
614 snps,multicast-filter-bins = <64>;
615 snps,perfect-filter-entries = <8>;
616 rx-fifo-depth = <2048>;
617 tx-fifo-depth = <2048>;
620 snps,force_thresh_dma_mode;
621 snps,axi-config = <&stmmac_axi_setup>;
623 snps,en-tx-lpi-clockgating;
626 starfive,syscon = <&sys_syscon 0x90 0x2>;
630 aoncrg: clock-controller@17000000 {
631 compatible = "starfive,jh7110-aoncrg";
632 reg = <0x0 0x17000000 0x0 0x10000>;
633 clocks = <&osc>, <&rtc_osc>,
634 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
635 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
636 <&syscrg JH7110_SYSCLK_APB_BUS>,
637 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
638 clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
639 "gmac0_rgmii_rxin", "stg_axiahb",
640 "apb_bus", "gmac0_gtxclk";
645 aon_syscon: aon_syscon@17010000 {
646 compatible = "starfive,jh7110-aon-syscon","syscon";
647 reg = <0x0 0x17010000 0x0 0x1000>;
650 aongpio: pinctrl@17020000 {
651 compatible = "starfive,jh7110-aon-pinctrl";
652 reg = <0x0 0x17020000 0x0 0x10000>;
653 resets = <&aoncrg JH7110_AONRST_IOMUX>;
655 interrupt-controller;
656 #interrupt-cells = <2>;
661 pcie0: pcie@2b000000 {
662 compatible = "starfive,jh7110-pcie";
663 reg = <0x0 0x2b000000 0x0 0x1000000
664 0x9 0x40000000 0x0 0x10000000>;
665 reg-names = "reg", "config";
666 #address-cells = <3>;
668 #interrupt-cells = <1>;
669 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
670 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
672 interrupt-parent = <&plic>;
673 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
674 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
675 <0x0 0x0 0x0 0x2 &plic 0x2>,
676 <0x0 0x0 0x0 0x3 &plic 0x3>,
677 <0x0 0x0 0x0 0x4 &plic 0x4>;
678 msi-parent = <&plic>;
680 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
681 bus-range = <0x0 0xff>;
682 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
683 <&stgcrg JH7110_STGCLK_PCIE0_TL>,
684 <&stgcrg JH7110_STGCLK_PCIE0_AXI>,
685 <&stgcrg JH7110_STGCLK_PCIE0_APB>;
686 clock-names = "noc", "tl", "axi", "apb";
687 resets = <&stgcrg JH7110_STGRST_PCIE0_MST0>,
688 <&stgcrg JH7110_STGRST_PCIE0_SLV0>,
689 <&stgcrg JH7110_STGRST_PCIE0_SLV>,
690 <&stgcrg JH7110_STGRST_PCIE0_BRG>,
691 <&stgcrg JH7110_STGRST_PCIE0_CORE>,
692 <&stgcrg JH7110_STGRST_PCIE0_APB>;
693 reset-names = "mst0", "slv0", "slv", "brg",
698 pcie1: pcie@2c000000 {
699 compatible = "starfive,jh7110-pcie";
700 reg = <0x0 0x2c000000 0x0 0x1000000
701 0x9 0xc0000000 0x0 0x10000000>;
702 reg-names = "reg", "config";
703 #address-cells = <3>;
705 #interrupt-cells = <1>;
706 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
707 <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
709 interrupt-parent = <&plic>;
710 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
711 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
712 <0x0 0x0 0x0 0x2 &plic 0x2>,
713 <0x0 0x0 0x0 0x3 &plic 0x3>,
714 <0x0 0x0 0x0 0x4 &plic 0x4>;
715 msi-parent = <&plic>;
717 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
718 bus-range = <0x0 0xff>;
719 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
720 <&stgcrg JH7110_STGCLK_PCIE1_TL>,
721 <&stgcrg JH7110_STGCLK_PCIE1_AXI>,
722 <&stgcrg JH7110_STGCLK_PCIE1_APB>;
723 clock-names = "noc", "tl", "axi", "apb";
724 resets = <&stgcrg JH7110_STGRST_PCIE1_MST0>,
725 <&stgcrg JH7110_STGRST_PCIE1_SLV0>,
726 <&stgcrg JH7110_STGRST_PCIE1_SLV>,
727 <&stgcrg JH7110_STGRST_PCIE1_BRG>,
728 <&stgcrg JH7110_STGRST_PCIE1_CORE>,
729 <&stgcrg JH7110_STGRST_PCIE1_APB>;
730 reset-names = "mst0", "slv0", "slv", "brg",