1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
7 #include <dt-bindings/clock/starfive,jh7110-crg.h>
8 #include <dt-bindings/reset/starfive,jh7110-crg.h>
11 compatible = "starfive,jh7110";
20 compatible = "sifive,s7", "riscv";
23 i-cache-block-size = <64>;
25 i-cache-size = <16384>;
26 next-level-cache = <&ccache>;
27 riscv,isa = "rv64imac_zba_zbb";
30 cpu0_intc: interrupt-controller {
31 compatible = "riscv,cpu-intc";
33 #interrupt-cells = <1>;
38 compatible = "sifive,u74-mc", "riscv";
40 d-cache-block-size = <64>;
42 d-cache-size = <32768>;
46 i-cache-block-size = <64>;
48 i-cache-size = <32768>;
51 mmu-type = "riscv,sv39";
52 next-level-cache = <&ccache>;
53 riscv,isa = "rv64imafdc_zba_zbb";
56 cpu1_intc: interrupt-controller {
57 compatible = "riscv,cpu-intc";
59 #interrupt-cells = <1>;
64 compatible = "sifive,u74-mc", "riscv";
66 d-cache-block-size = <64>;
68 d-cache-size = <32768>;
72 i-cache-block-size = <64>;
74 i-cache-size = <32768>;
77 mmu-type = "riscv,sv39";
78 next-level-cache = <&ccache>;
79 riscv,isa = "rv64imafdc_zba_zbb";
82 cpu2_intc: interrupt-controller {
83 compatible = "riscv,cpu-intc";
85 #interrupt-cells = <1>;
90 compatible = "sifive,u74-mc", "riscv";
92 d-cache-block-size = <64>;
94 d-cache-size = <32768>;
98 i-cache-block-size = <64>;
100 i-cache-size = <32768>;
103 mmu-type = "riscv,sv39";
104 next-level-cache = <&ccache>;
105 riscv,isa = "rv64imafdc_zba_zbb";
108 cpu3_intc: interrupt-controller {
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
111 #interrupt-cells = <1>;
116 compatible = "sifive,u74-mc", "riscv";
118 d-cache-block-size = <64>;
120 d-cache-size = <32768>;
124 i-cache-block-size = <64>;
126 i-cache-size = <32768>;
129 mmu-type = "riscv,sv39";
130 next-level-cache = <&ccache>;
131 riscv,isa = "rv64imafdc_zba_zbb";
134 cpu4_intc: interrupt-controller {
135 compatible = "riscv,cpu-intc";
136 interrupt-controller;
137 #interrupt-cells = <1>;
167 compatible = "fixed-clock";
168 clock-output-names = "osc";
172 rtc_osc: rtc-oscillator {
173 compatible = "fixed-clock";
174 clock-output-names = "rtc_osc";
178 gmac0_rmii_refin: gmac0-rmii-refin-clock {
179 compatible = "fixed-clock";
180 clock-output-names = "gmac0_rmii_refin";
184 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
185 compatible = "fixed-clock";
186 clock-output-names = "gmac0_rgmii_rxin";
190 gmac1_rmii_refin: gmac1-rmii-refin-clock {
191 compatible = "fixed-clock";
192 clock-output-names = "gmac1_rmii_refin";
196 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
197 compatible = "fixed-clock";
198 clock-output-names = "gmac1_rgmii_rxin";
202 i2stx_bclk_ext: i2stx-bclk-ext-clock {
203 compatible = "fixed-clock";
204 clock-output-names = "i2stx_bclk_ext";
208 i2stx_lrck_ext: i2stx-lrck-ext-clock {
209 compatible = "fixed-clock";
210 clock-output-names = "i2stx_lrck_ext";
214 i2srx_bclk_ext: i2srx-bclk-ext-clock {
215 compatible = "fixed-clock";
216 clock-output-names = "i2srx_bclk_ext";
220 i2srx_lrck_ext: i2srx-lrck-ext-clock {
221 compatible = "fixed-clock";
222 clock-output-names = "i2srx_lrck_ext";
226 tdm_ext: tdm-ext-clock {
227 compatible = "fixed-clock";
228 clock-output-names = "tdm_ext";
232 mclk_ext: mclk-ext-clock {
233 compatible = "fixed-clock";
234 clock-output-names = "mclk_ext";
238 stmmac_axi_setup: stmmac-axi-config {
240 snps,wr_osr_lmt = <4>;
241 snps,rd_osr_lmt = <4>;
242 snps,blen = <256 128 64 32 0 0 0>;
246 compatible = "simple-bus";
247 interrupt-parent = <&plic>;
248 #address-cells = <2>;
252 clint: timer@2000000 {
253 compatible = "starfive,jh7110-clint", "sifive,clint0";
254 reg = <0x0 0x2000000 0x0 0x10000>;
255 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
256 <&cpu1_intc 3>, <&cpu1_intc 7>,
257 <&cpu2_intc 3>, <&cpu2_intc 7>,
258 <&cpu3_intc 3>, <&cpu3_intc 7>,
259 <&cpu4_intc 3>, <&cpu4_intc 7>;
262 plic: interrupt-controller@c000000 {
263 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
264 reg = <0x0 0xc000000 0x0 0x4000000>;
265 interrupts-extended = <&cpu0_intc 11>,
266 <&cpu1_intc 11>, <&cpu1_intc 9>,
267 <&cpu2_intc 11>, <&cpu2_intc 9>,
268 <&cpu3_intc 11>, <&cpu3_intc 9>,
269 <&cpu4_intc 11>, <&cpu4_intc 9>;
270 interrupt-controller;
271 #interrupt-cells = <1>;
272 #address-cells = <0>;
276 ccache: cache-controller@2010000 {
277 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
278 reg = <0x0 0x2010000 0x0 0x4000>;
279 interrupts = <1>, <3>, <4>, <2>;
280 cache-block-size = <64>;
283 cache-size = <2097152>;
287 uart0: serial@10000000 {
288 compatible = "snps,dw-apb-uart";
289 reg = <0x0 0x10000000 0x0 0x10000>;
290 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
291 <&syscrg JH7110_SYSCLK_UART0_APB>;
292 clock-names = "baudclk", "apb_pclk";
293 resets = <&syscrg JH7110_SYSRST_UART0_APB>,
294 <&syscrg JH7110_SYSRST_UART0_CORE>;
301 uart1: serial@10010000 {
302 compatible = "snps,dw-apb-uart";
303 reg = <0x0 0x10010000 0x0 0x10000>;
304 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
305 <&syscrg JH7110_SYSCLK_UART1_APB>;
306 clock-names = "baudclk", "apb_pclk";
307 resets = <&syscrg JH7110_SYSRST_UART1_APB>,
308 <&syscrg JH7110_SYSRST_UART1_CORE>;
315 uart2: serial@10020000 {
316 compatible = "snps,dw-apb-uart";
317 reg = <0x0 0x10020000 0x0 0x10000>;
318 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
319 <&syscrg JH7110_SYSCLK_UART2_APB>;
320 clock-names = "baudclk", "apb_pclk";
321 resets = <&syscrg JH7110_SYSRST_UART2_APB>,
322 <&syscrg JH7110_SYSRST_UART2_CORE>;
330 compatible = "snps,designware-i2c";
331 reg = <0x0 0x10030000 0x0 0x10000>;
332 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
334 resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
336 #address-cells = <1>;
342 compatible = "snps,designware-i2c";
343 reg = <0x0 0x10040000 0x0 0x10000>;
344 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
346 resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
348 #address-cells = <1>;
354 compatible = "snps,designware-i2c";
355 reg = <0x0 0x10050000 0x0 0x10000>;
356 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
358 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
360 #address-cells = <1>;
365 stgcrg: clock-controller@10230000 {
366 compatible = "starfive,jh7110-stgcrg";
367 reg = <0x0 0x10230000 0x0 0x10000>;
372 stg_syscon: stg_syscon@10240000 {
373 compatible = "starfive,jh7110-stg-syscon","syscon";
374 reg = <0x0 0x10240000 0x0 0x1000>;
377 uart3: serial@12000000 {
378 compatible = "snps,dw-apb-uart";
379 reg = <0x0 0x12000000 0x0 0x10000>;
380 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
381 <&syscrg JH7110_SYSCLK_UART3_APB>;
382 clock-names = "baudclk", "apb_pclk";
383 resets = <&syscrg JH7110_SYSRST_UART3_APB>,
384 <&syscrg JH7110_SYSRST_UART3_CORE>;
391 uart4: serial@12010000 {
392 compatible = "snps,dw-apb-uart";
393 reg = <0x0 0x12010000 0x0 0x10000>;
394 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
395 <&syscrg JH7110_SYSCLK_UART4_APB>;
396 clock-names = "baudclk", "apb_pclk";
397 resets = <&syscrg JH7110_SYSRST_UART4_APB>,
398 <&syscrg JH7110_SYSRST_UART4_CORE>;
405 uart5: serial@12020000 {
406 compatible = "snps,dw-apb-uart";
407 reg = <0x0 0x12020000 0x0 0x10000>;
408 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
409 <&syscrg JH7110_SYSCLK_UART5_APB>;
410 clock-names = "baudclk", "apb_pclk";
411 resets = <&syscrg JH7110_SYSRST_UART5_APB>,
412 <&syscrg JH7110_SYSRST_UART5_CORE>;
420 compatible = "snps,designware-i2c";
421 reg = <0x0 0x12030000 0x0 0x10000>;
422 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
424 resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
426 #address-cells = <1>;
432 compatible = "snps,designware-i2c";
433 reg = <0x0 0x12040000 0x0 0x10000>;
434 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
436 resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
438 #address-cells = <1>;
444 compatible = "snps,designware-i2c";
445 reg = <0x0 0x12050000 0x0 0x10000>;
446 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
448 resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
450 #address-cells = <1>;
456 compatible = "snps,designware-i2c";
457 reg = <0x0 0x12060000 0x0 0x10000>;
458 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
460 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
462 #address-cells = <1>;
468 compatible = "cdns,qspi-nor";
469 reg = <0x0 0x13010000 0x0 0x10000
470 0x0 0x21000000 0x0 0x400000>;
471 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
472 clock-names = "clk_ref";
473 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
474 <&syscrg JH7110_SYSRST_QSPI_AHB>,
475 <&syscrg JH7110_SYSRST_QSPI_REF>;
476 reset-names = "rst_apb", "rst_ahb", "rst_ref";
477 cdns,fifo-depth = <256>;
478 cdns,fifo-width = <4>;
479 #address-cells = <1>;
483 syscrg: clock-controller@13020000 {
484 compatible = "starfive,jh7110-syscrg";
485 reg = <0x0 0x13020000 0x0 0x10000>;
486 clocks = <&osc>, <&gmac1_rmii_refin>,
488 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
489 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
490 <&tdm_ext>, <&mclk_ext>;
491 clock-names = "osc", "gmac1_rmii_refin",
493 "i2stx_bclk_ext", "i2stx_lrck_ext",
494 "i2srx_bclk_ext", "i2srx_lrck_ext",
495 "tdm_ext", "mclk_ext";
500 sys_syscon: sys_syscon@13030000 {
501 compatible = "starfive,jh7110-sys-syscon","syscon", "simple-mfd";
502 reg = <0x0 0x13030000 0x0 0x1000>;
504 pllclk: clock-controller {
505 compatible = "starfive,jh7110-pll";
511 sysgpio: pinctrl@13040000 {
512 compatible = "starfive,jh7110-sys-pinctrl";
513 reg = <0x0 0x13040000 0x0 0x10000>;
514 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
515 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
517 interrupt-controller;
518 #interrupt-cells = <2>;
524 compatible = "starfive,jh7110-mmc";
525 reg = <0x0 0x16010000 0x0 0x10000>;
526 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
527 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
528 clock-names = "biu", "ciu";
529 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
530 reset-names = "reset";
533 fifo-watermark-aligned;
535 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
540 compatible = "starfive,jh7110-mmc";
541 reg = <0x0 0x16020000 0x0 0x10000>;
542 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
543 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
544 clock-names = "biu", "ciu";
545 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
546 reset-names = "reset";
549 fifo-watermark-aligned;
551 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
555 gmac0: ethernet@16030000 {
556 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
557 reg = <0x0 0x16030000 0x0 0x10000>;
558 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
559 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
560 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
561 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
562 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
563 clock-names = "stmmaceth", "pclk", "ptp_ref",
565 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
566 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
567 reset-names = "stmmaceth", "ahb";
568 interrupts = <7>, <6>, <5>;
569 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
570 snps,multicast-filter-bins = <64>;
571 snps,perfect-filter-entries = <8>;
572 rx-fifo-depth = <2048>;
573 tx-fifo-depth = <2048>;
576 snps,force_thresh_dma_mode;
577 snps,axi-config = <&stmmac_axi_setup>;
579 snps,en-tx-lpi-clockgating;
582 starfive,syscon = <&aon_syscon 0xc 0x12>;
586 gmac1: ethernet@16040000 {
587 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
588 reg = <0x0 0x16040000 0x0 0x10000>;
589 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
590 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
591 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
592 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
593 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
594 clock-names = "stmmaceth", "pclk", "ptp_ref",
596 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
597 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
598 reset-names = "stmmaceth", "ahb";
599 interrupts = <78>, <77>, <76>;
600 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
601 snps,multicast-filter-bins = <64>;
602 snps,perfect-filter-entries = <8>;
603 rx-fifo-depth = <2048>;
604 tx-fifo-depth = <2048>;
607 snps,force_thresh_dma_mode;
608 snps,axi-config = <&stmmac_axi_setup>;
610 snps,en-tx-lpi-clockgating;
613 starfive,syscon = <&sys_syscon 0x90 0x2>;
617 aoncrg: clock-controller@17000000 {
618 compatible = "starfive,jh7110-aoncrg";
619 reg = <0x0 0x17000000 0x0 0x10000>;
620 clocks = <&osc>, <&rtc_osc>,
621 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>,
622 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
623 <&syscrg JH7110_SYSCLK_APB_BUS>,
624 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>;
625 clock-names = "osc", "rtc_osc", "gmac0_rmii_refin",
626 "gmac0_rgmii_rxin", "stg_axiahb",
627 "apb_bus", "gmac0_gtxclk";
632 aon_syscon: aon_syscon@17010000 {
633 compatible = "starfive,jh7110-aon-syscon","syscon";
634 reg = <0x0 0x17010000 0x0 0x1000>;
637 aongpio: pinctrl@17020000 {
638 compatible = "starfive,jh7110-aon-pinctrl";
639 reg = <0x0 0x17020000 0x0 0x10000>;
640 resets = <&aoncrg JH7110_AONRST_IOMUX>;
642 interrupt-controller;
643 #interrupt-cells = <2>;