arch/riscv/dts/fu740-c000.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020-2021 SiFive, Inc */
   3
   4 /dts-v1/;
   5
   6 #include <dt-bindings/clock/sifive-fu740-prci.h>
   7 #include <dt-bindings/reset/sifive-fu740-prci.h>
   8
   9 / {
  10         #address-cells = <2>;
  11         #size-cells = <2>;
  12         compatible = "sifive,fu740-c000", "sifive,fu740";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 serial1 = &uart1;
  17                 ethernet0 = &eth0;
  18         };
  19
  20         chosen {
  21         };
  22
  23         cpus {
  24                 #address-cells = <1>;
  25                 #size-cells = <0>;
  26                 cpu0: cpu@0 {
  27                         compatible = "sifive,bullet0", "riscv";
  28                         device_type = "cpu";
  29                         i-cache-block-size = <64>;
  30                         i-cache-sets = <128>;
  31                         i-cache-size = <16384>;
  32                         next-level-cache = <&ccache>;
  33                         reg = <0x0>;
  34                         riscv,isa = "rv64imac";
  35                         status = "disabled";
  36                         cpu0_intc: interrupt-controller {
  37                                 #interrupt-cells = <1>;
  38                                 compatible = "riscv,cpu-intc";
  39                                 interrupt-controller;
  40                         };
  41                 };
  42                 cpu1: cpu@1 {
  43                         compatible = "sifive,bullet0", "riscv";
  44                         d-cache-block-size = <64>;
  45                         d-cache-sets = <64>;
  46                         d-cache-size = <32768>;
  47                         d-tlb-sets = <1>;
  48                         d-tlb-size = <40>;
  49                         device_type = "cpu";
  50                         i-cache-block-size = <64>;
  51                         i-cache-sets = <128>;
  52                         i-cache-size = <32768>;
  53                         i-tlb-sets = <1>;
  54                         i-tlb-size = <40>;
  55                         mmu-type = "riscv,sv39";
  56                         next-level-cache = <&ccache>;
  57                         reg = <0x1>;
  58                         riscv,isa = "rv64imafdc";
  59                         tlb-split;
  60                         cpu1_intc: interrupt-controller {
  61                                 #interrupt-cells = <1>;
  62                                 compatible = "riscv,cpu-intc";
  63                                 interrupt-controller;
  64                         };
  65                 };
  66                 cpu2: cpu@2 {
  67                         compatible = "sifive,bullet0", "riscv";
  68                         d-cache-block-size = <64>;
  69                         d-cache-sets = <64>;
  70                         d-cache-size = <32768>;
  71                         d-tlb-sets = <1>;
  72                         d-tlb-size = <40>;
  73                         device_type = "cpu";
  74                         i-cache-block-size = <64>;
  75                         i-cache-sets = <128>;
  76                         i-cache-size = <32768>;
  77                         i-tlb-sets = <1>;
  78                         i-tlb-size = <40>;
  79                         mmu-type = "riscv,sv39";
  80                         next-level-cache = <&ccache>;
  81                         reg = <0x2>;
  82                         riscv,isa = "rv64imafdc";
  83                         tlb-split;
  84                         cpu2_intc: interrupt-controller {
  85                                 #interrupt-cells = <1>;
  86                                 compatible = "riscv,cpu-intc";
  87                                 interrupt-controller;
  88                         };
  89                 };
  90                 cpu3: cpu@3 {
  91                         compatible = "sifive,bullet0", "riscv";
  92                         d-cache-block-size = <64>;
  93                         d-cache-sets = <64>;
  94                         d-cache-size = <32768>;
  95                         d-tlb-sets = <1>;
  96                         d-tlb-size = <40>;
  97                         device_type = "cpu";
  98                         i-cache-block-size = <64>;
  99                         i-cache-sets = <128>;
 100                         i-cache-size = <32768>;
 101                         i-tlb-sets = <1>;
 102                         i-tlb-size = <40>;
 103                         mmu-type = "riscv,sv39";
 104                         next-level-cache = <&ccache>;
 105                         reg = <0x3>;
 106                         riscv,isa = "rv64imafdc";
 107                         tlb-split;
 108                         cpu3_intc: interrupt-controller {
 109                                 #interrupt-cells = <1>;
 110                                 compatible = "riscv,cpu-intc";
 111                                 interrupt-controller;
 112                         };
 113                 };
 114                 cpu4: cpu@4 {
 115                         compatible = "sifive,bullet0", "riscv";
 116                         d-cache-block-size = <64>;
 117                         d-cache-sets = <64>;
 118                         d-cache-size = <32768>;
 119                         d-tlb-sets = <1>;
 120                         d-tlb-size = <40>;
 121                         device_type = "cpu";
 122                         i-cache-block-size = <64>;
 123                         i-cache-sets = <128>;
 124                         i-cache-size = <32768>;
 125                         i-tlb-sets = <1>;
 126                         i-tlb-size = <40>;
 127                         mmu-type = "riscv,sv39";
 128                         next-level-cache = <&ccache>;
 129                         reg = <0x4>;
 130                         riscv,isa = "rv64imafdc";
 131                         tlb-split;
 132                         cpu4_intc: interrupt-controller {
 133                                 #interrupt-cells = <1>;
 134                                 compatible = "riscv,cpu-intc";
 135                                 interrupt-controller;
 136                         };
 137                 };
 138         };
 139         soc {
 140                 #address-cells = <2>;
 141                 #size-cells = <2>;
 142                 compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
 143                 ranges;
 144                 plic0: interrupt-controller@c000000 {
 145                         #interrupt-cells = <1>;
 146                         compatible = "sifive,plic-1.0.0";
 147                         reg = <0x0 0xc000000 0x0 0x4000000>;
 148                         riscv,ndev = <69>;
 149                         interrupt-controller;
 150                         interrupts-extended = <
 151                                 &cpu0_intc 0xffffffff
 152                                 &cpu1_intc 0xffffffff &cpu1_intc 9
 153                                 &cpu2_intc 0xffffffff &cpu2_intc 9
 154                                 &cpu3_intc 0xffffffff &cpu3_intc 9
 155                                 &cpu4_intc 0xffffffff &cpu4_intc 9>;
 156                 };
 157                 prci: clock-controller@10000000 {
 158                         compatible = "sifive,fu740-c000-prci";
 159                         reg = <0x0 0x10000000 0x0 0x1000>;
 160                         clocks = <&hfclk>, <&rtcclk>;
 161                         #clock-cells = <1>;
 162                         #reset-cells = <1>;
 163                 };
 164                 uart0: serial@10010000 {
 165                         compatible = "sifive,fu740-c000-uart", "sifive,uart0";
 166                         reg = <0x0 0x10010000 0x0 0x1000>;
 167                         interrupt-parent = <&plic0>;
 168                         interrupts = <39>;
 169                         clocks = <&prci PRCI_CLK_PCLK>;
 170                         status = "disabled";
 171                 };
 172                 uart1: serial@10011000 {
 173                         compatible = "sifive,fu740-c000-uart", "sifive,uart0";
 174                         reg = <0x0 0x10011000 0x0 0x1000>;
 175                         interrupt-parent = <&plic0>;
 176                         interrupts = <40>;
 177                         clocks = <&prci PRCI_CLK_PCLK>;
 178                         status = "disabled";
 179                 };
 180                 i2c0: i2c@10030000 {
 181                         compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
 182                         reg = <0x0 0x10030000 0x0 0x1000>;
 183                         interrupt-parent = <&plic0>;
 184                         interrupts = <52>;
 185                         clocks = <&prci PRCI_CLK_PCLK>;
 186                         reg-shift = <2>;
 187                         reg-io-width = <1>;
 188                         #address-cells = <1>;
 189                         #size-cells = <0>;
 190                         status = "disabled";
 191                 };
 192                 i2c1: i2c@10031000 {
 193                         compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
 194                         reg = <0x0 0x10031000 0x0 0x1000>;
 195                         interrupt-parent = <&plic0>;
 196                         interrupts = <53>;
 197                         clocks = <&prci PRCI_CLK_PCLK>;
 198                         reg-shift = <2>;
 199                         reg-io-width = <1>;
 200                         #address-cells = <1>;
 201                         #size-cells = <0>;
 202                         status = "disabled";
 203                 };
 204                 qspi0: spi@10040000 {
 205                         compatible = "sifive,fu740-c000-spi", "sifive,spi0";
 206                         reg = <0x0 0x10040000 0x0 0x1000
 207                                0x0 0x20000000 0x0 0x10000000>;
 208                         interrupt-parent = <&plic0>;
 209                         interrupts = <41>;
 210                         clocks = <&prci PRCI_CLK_PCLK>;
 211                         #address-cells = <1>;
 212                         #size-cells = <0>;
 213                         status = "disabled";
 214                 };
 215                 qspi1: spi@10041000 {
 216                         compatible = "sifive,fu740-c000-spi", "sifive,spi0";
 217                         reg = <0x0 0x10041000 0x0 0x1000
 218                                0x0 0x30000000 0x0 0x10000000>;
 219                         interrupt-parent = <&plic0>;
 220                         interrupts = <42>;
 221                         clocks = <&prci PRCI_CLK_PCLK>;
 222                         #address-cells = <1>;
 223                         #size-cells = <0>;
 224                         status = "disabled";
 225                 };
 226                 spi0: spi@10050000 {
 227                         compatible = "sifive,fu740-c000-spi", "sifive,spi0";
 228                         reg = <0x0 0x10050000 0x0 0x1000>;
 229                         interrupt-parent = <&plic0>;
 230                         interrupts = <43>;
 231                         clocks = <&prci PRCI_CLK_PCLK>;
 232                         #address-cells = <1>;
 233                         #size-cells = <0>;
 234                         status = "disabled";
 235                 };
 236                 eth0: ethernet@10090000 {
 237                         compatible = "sifive,fu540-c000-gem";
 238                         interrupt-parent = <&plic0>;
 239                         interrupts = <55>;
 240                         reg = <0x0 0x10090000 0x0 0x2000
 241                                0x0 0x100a0000 0x0 0x1000>;
 242                         local-mac-address = [00 00 00 00 00 00];
 243                         clock-names = "pclk", "hclk";
 244                         clocks = <&prci PRCI_CLK_GEMGXLPLL>,
 245                                  <&prci PRCI_CLK_GEMGXLPLL>;
 246                         #address-cells = <1>;
 247                         #size-cells = <0>;
 248                         status = "disabled";
 249                 };
 250                 pwm0: pwm@10020000 {
 251                         compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
 252                         reg = <0x0 0x10020000 0x0 0x1000>;
 253                         interrupt-parent = <&plic0>;
 254                         interrupts = <44 45 46 47>;
 255                         clocks = <&prci PRCI_CLK_PCLK>;
 256                         #pwm-cells = <3>;
 257                         status = "disabled";
 258                 };
 259                 pwm1: pwm@10021000 {
 260                         compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
 261                         reg = <0x0 0x10021000 0x0 0x1000>;
 262                         interrupt-parent = <&plic0>;
 263                         interrupts = <48 49 50 51>;
 264                         clocks = <&prci PRCI_CLK_PCLK>;
 265                         #pwm-cells = <3>;
 266                         status = "disabled";
 267                 };
 268                 ccache: cache-controller@2010000 {
 269                         compatible = "sifive,fu740-c000-ccache", "cache";
 270                         cache-block-size = <64>;
 271                         cache-level = <2>;
 272                         cache-sets = <2048>;
 273                         cache-size = <2097152>;
 274                         cache-unified;
 275                         interrupt-parent = <&plic0>;
 276                         interrupts = <19 21 22 20>;
 277                         reg = <0x0 0x2010000 0x0 0x1000>;
 278                 };
 279                 gpio: gpio@10060000 {
 280                         compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
 281                         interrupt-parent = <&plic0>;
 282                         interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
 283                                      <30>, <31>, <32>, <33>, <34>, <35>, <36>,
 284                                      <37>, <38>;
 285                         reg = <0x0 0x10060000 0x0 0x1000>;
 286                         gpio-controller;
 287                         #gpio-cells = <2>;
 288                         interrupt-controller;
 289                         #interrupt-cells = <2>;
 290                         clocks = <&prci PRCI_CLK_PCLK>;
 291                         status = "disabled";
 292                 };
 293                 pcie@e00000000 {
 294                         #address-cells = <3>;
 295                         #interrupt-cells = <1>;
 296                         #num-lanes = <8>;
 297                         #size-cells = <2>;
 298                         compatible = "sifive,fu740-pcie";
 299                         reg = <0xe 0x00000000 0x1 0x0
 300                                0xd 0xf0000000 0x0 0x10000000
 301                                0x0 0x100d0000 0x0 0x1000>;
 302                         reg-names = "dbi", "config", "mgmt";
 303                         device_type = "pci";
 304                         dma-coherent;
 305                         bus-range = <0x0 0xff>;
 306                         ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000
 307                                   0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000
 308                                   0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000
 309                                   0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;
 310                         num-lanes = <0x8>;
 311                         interrupts = <56 57 58 59 60 61 62 63 64>;
 312                         interrupt-names = "msi", "inta", "intb", "intc", "intd";
 313                         interrupt-parent = <&plic0>;
 314                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 315                         interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
 316                                         <0x0 0x0 0x0 0x2 &plic0 58>,
 317                                         <0x0 0x0 0x0 0x3 &plic0 59>,
 318                                         <0x0 0x0 0x0 0x4 &plic0 60>;
 319                         pwren-gpios = <&gpio 5 0>;
 320                         reset-gpios = <&gpio 8 0>;
 321                         clocks = <&prci PRCI_CLK_PCIEAUX>;
 322                         clock-names = "pcieaux";
 323                         resets = <&prci PRCI_RST_PCIE_POWER_UP_N>;
 324                         reset-names = "rst_n";
 325
 326                         status = "okay";
 327                 };
 328         };
 329 };