arch/riscv/dts/fu540-c000-u-boot.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /*
   3  * (C) Copyright 2019 SiFive, Inc
   4  */
   5
   6 #include <dt-bindings/reset/sifive-fu540-prci.h>
   7
   8 / {
   9         cpus {
  10                 assigned-clocks = <&prci PRCI_CLK_COREPLL>;
  11                 assigned-clock-rates = <1000000000>;
  12                 u-boot,dm-spl;
  13                 cpu0: cpu@0 {
  14                         clocks = <&prci PRCI_CLK_COREPLL>;
  15                         u-boot,dm-spl;
  16                         status = "okay";
  17                         cpu0_intc: interrupt-controller {
  18                                 u-boot,dm-spl;
  19                         };
  20                 };
  21                 cpu1: cpu@1 {
  22                         clocks = <&prci PRCI_CLK_COREPLL>;
  23                         u-boot,dm-spl;
  24                         cpu1_intc: interrupt-controller {
  25                                 u-boot,dm-spl;
  26                         };
  27                 };
  28                 cpu2: cpu@2 {
  29                         clocks = <&prci PRCI_CLK_COREPLL>;
  30                         u-boot,dm-spl;
  31                         cpu2_intc: interrupt-controller {
  32                                 u-boot,dm-spl;
  33                         };
  34                 };
  35                 cpu3: cpu@3 {
  36                         clocks = <&prci PRCI_CLK_COREPLL>;
  37                         u-boot,dm-spl;
  38                         cpu3_intc: interrupt-controller {
  39                                 u-boot,dm-spl;
  40                         };
  41                 };
  42                 cpu4: cpu@4 {
  43                         clocks = <&prci PRCI_CLK_COREPLL>;
  44                         u-boot,dm-spl;
  45                         cpu4_intc: interrupt-controller {
  46                                 u-boot,dm-spl;
  47                         };
  48                 };
  49         };
  50
  51         soc {
  52                 u-boot,dm-spl;
  53                 otp: otp@10070000 {
  54                         compatible = "sifive,fu540-c000-otp";
  55                         reg = <0x0 0x10070000 0x0 0x1000>;
  56                         fuse-count = <0x1000>;
  57                 };
  58                 clint: clint@2000000 {
  59                         compatible = "riscv,clint0";
  60                         interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
  61                                                &cpu1_intc 3 &cpu1_intc 7
  62                                                &cpu2_intc 3 &cpu2_intc 7
  63                                                &cpu3_intc 3 &cpu3_intc 7
  64                                                &cpu4_intc 3 &cpu4_intc 7>;
  65                         reg = <0x0 0x2000000 0x0 0x10000>;
  66                         u-boot,dm-spl;
  67                 };
  68                 prci: clock-controller@10000000 {
  69                         #reset-cells = <1>;
  70                         resets = <&prci PRCI_RST_DDR_CTRL_N>,
  71                                  <&prci PRCI_RST_DDR_AXI_N>,
  72                                  <&prci PRCI_RST_DDR_AHB_N>,
  73                                  <&prci PRCI_RST_DDR_PHY_N>,
  74                                  <&prci PRCI_RST_GEMGXL_N>;
  75                         reset-names = "ddr_ctrl", "ddr_axi", "ddr_ahb",
  76                                         "ddr_phy", "gemgxl_reset";
  77                 };
  78                 dmc: dmc@100b0000 {
  79                         compatible = "sifive,fu540-c000-ddr";
  80                         reg = <0x0 0x100b0000 0x0 0x0800
  81                                0x0 0x100b2000 0x0 0x2000
  82                                0x0 0x100b8000 0x0 0x1000>;
  83                         clocks = <&prci PRCI_CLK_DDRPLL>;
  84                         clock-frequency = <933333324>;
  85                         u-boot,dm-spl;
  86                 };
  87         };
  88 };
  89
  90 &prci {
  91         u-boot,dm-spl;
  92 };
  93
  94 &uart0 {
  95         u-boot,dm-spl;
  96 };
  97
  98 &qspi2 {
  99         u-boot,dm-spl;
 100 };
 101
 102 &eth0 {
 103         assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
 104         assigned-clock-rates = <125000000>;
 105 };
 106
 107 &l2cache {
 108         status = "okay";
 109 };