arch/riscv/dts/ae350_32.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2
   3 /dts-v1/;
   4
   5 #include "binman.dtsi"
   6 #include "ae350-u-boot.dtsi"
   7
   8 / {
   9         #address-cells = <1>;
  10         #size-cells = <1>;
  11         compatible = "andestech,a25";
  12         model = "andestech,a25";
  13
  14         aliases {
  15                 uart0 = &serial0;
  16                 spi0 = &spi;
  17         };
  18
  19         chosen {
  20                 bootargs = "console=ttyS0,38400n8 debug loglevel=7";
  21                 stdout-path = "uart0:38400n8";
  22         };
  23
  24         cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 timebase-frequency = <60000000>;
  28                 CPU0: cpu@0 {
  29                         device_type = "cpu";
  30                         reg = <0>;
  31                         status = "okay";
  32                         compatible = "riscv";
  33                         riscv,isa = "rv32imafdc";
  34                         riscv,priv-major = <1>;
  35                         riscv,priv-minor = <10>;
  36                         mmu-type = "riscv,sv32";
  37                         clock-frequency = <60000000>;
  38                         i-cache-size = <0x8000>;
  39                         i-cache-line-size = <32>;
  40                         d-cache-size = <0x8000>;
  41                         d-cache-line-size = <32>;
  42                         next-level-cache = <&L2>;
  43                         CPU0_intc: interrupt-controller {
  44                                 #interrupt-cells = <1>;
  45                                 interrupt-controller;
  46                                 compatible = "riscv,cpu-intc";
  47                         };
  48                 };
  49                 CPU1: cpu@1 {
  50                         device_type = "cpu";
  51                         reg = <1>;
  52                         status = "okay";
  53                         compatible = "riscv";
  54                         riscv,isa = "rv32imafdc";
  55                         riscv,priv-major = <1>;
  56                         riscv,priv-minor = <10>;
  57                         mmu-type = "riscv,sv32";
  58                         clock-frequency = <60000000>;
  59                         i-cache-size = <0x8000>;
  60                         i-cache-line-size = <32>;
  61                         d-cache-size = <0x8000>;
  62                         d-cache-line-size = <32>;
  63                         next-level-cache = <&L2>;
  64                         CPU1_intc: interrupt-controller {
  65                                 #interrupt-cells = <1>;
  66                                 interrupt-controller;
  67                                 compatible = "riscv,cpu-intc";
  68                         };
  69                 };
  70                 CPU2: cpu@2 {
  71                         device_type = "cpu";
  72                         reg = <2>;
  73                         status = "okay";
  74                         compatible = "riscv";
  75                         riscv,isa = "rv32imafdc";
  76                         riscv,priv-major = <1>;
  77                         riscv,priv-minor = <10>;
  78                         mmu-type = "riscv,sv32";
  79                         clock-frequency = <60000000>;
  80                         i-cache-size = <0x8000>;
  81                         i-cache-line-size = <32>;
  82                         d-cache-size = <0x8000>;
  83                         d-cache-line-size = <32>;
  84                         next-level-cache = <&L2>;
  85                         CPU2_intc: interrupt-controller {
  86                                 #interrupt-cells = <1>;
  87                                 interrupt-controller;
  88                                 compatible = "riscv,cpu-intc";
  89                         };
  90                 };
  91                 CPU3: cpu@3 {
  92                         device_type = "cpu";
  93                         reg = <3>;
  94                         status = "okay";
  95                         compatible = "riscv";
  96                         riscv,isa = "rv32imafdc";
  97                         riscv,priv-major = <1>;
  98                         riscv,priv-minor = <10>;
  99                         mmu-type = "riscv,sv32";
 100                         clock-frequency = <60000000>;
 101                         i-cache-size = <0x8000>;
 102                         i-cache-line-size = <32>;
 103                         d-cache-size = <0x8000>;
 104                         d-cache-line-size = <32>;
 105                         next-level-cache = <&L2>;
 106                         CPU3_intc: interrupt-controller {
 107                                 #interrupt-cells = <1>;
 108                                 interrupt-controller;
 109                                 compatible = "riscv,cpu-intc";
 110                         };
 111                 };
 112         };
 113
 114         L2: l2-cache@e0500000 {
 115                 compatible = "v5l2cache";
 116                 cache-level = <2>;
 117                 cache-size = <0x40000>;
 118                 reg = <0xe0500000 0x40000>;
 119                 andes,inst-prefetch = <3>;
 120                 andes,data-prefetch = <3>;
 121                 /* The value format is <XRAMOCTL XRAMICTL> */
 122                 andes,tag-ram-ctl = <0 0>;
 123                 andes,data-ram-ctl = <0 0>;
 124         };
 125
 126         memory@0 {
 127                 device_type = "memory";
 128                 reg = <0x00000000 0x40000000>;
 129         };
 130
 131         soc {
 132                 #address-cells = <1>;
 133                 #size-cells = <1>;
 134                 compatible = "simple-bus";
 135                 ranges;
 136
 137                 plic0: interrupt-controller@e4000000 {
 138                         compatible = "riscv,plic0";
 139                         #interrupt-cells = <2>;
 140                         interrupt-controller;
 141                         reg = <0xe4000000 0x2000000>;
 142                         riscv,ndev=<71>;
 143                         interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
 144                                 &CPU1_intc 11 &CPU1_intc 9
 145                                 &CPU2_intc 11 &CPU2_intc 9
 146                                 &CPU3_intc 11 &CPU3_intc 9>;
 147                 };
 148
 149                 plic1: interrupt-controller@e6400000 {
 150                         compatible = "riscv,plic1";
 151                         #interrupt-cells = <1>;
 152                         interrupt-controller;
 153                         reg = <0xe6400000 0x400000>;
 154                         riscv,ndev=<2>;
 155                         interrupts-extended = <&CPU0_intc 3
 156                                 &CPU1_intc 3
 157                                 &CPU2_intc 3
 158                                 &CPU3_intc 3>;
 159                 };
 160
 161                 plmt0@e6000000 {
 162                         compatible = "riscv,plmt0";
 163                         interrupts-extended = <&CPU0_intc 7
 164                                 &CPU1_intc 7
 165                                 &CPU2_intc 7
 166                                 &CPU3_intc 7>;
 167                         reg = <0xe6000000 0x100000>;
 168                 };
 169         };
 170
 171         spiclk: virt_100mhz {
 172                 #clock-cells = <0>;
 173                 compatible = "fixed-clock";
 174                 clock-frequency = <100000000>;
 175         };
 176
 177         timer0: timer@f0400000 {
 178                 compatible = "andestech,atcpit100";
 179                 reg = <0xf0400000 0x1000>;
 180                 clock-frequency = <60000000>;
 181                 interrupts = <3 4>;
 182                 interrupt-parent = <&plic0>;
 183         };
 184
 185         serial0: serial@f0300000 {
 186                 compatible = "andestech,uart16550", "ns16550a";
 187                 reg = <0xf0300000 0x1000>;
 188                 interrupts = <9 4>;
 189                 clock-frequency = <19660800>;
 190                 reg-shift = <2>;
 191                 reg-offset = <32>;
 192                 no-loopback-test = <1>;
 193                 interrupt-parent = <&plic0>;
 194         };
 195
 196         mac0: mac@e0100000 {
 197                 compatible = "andestech,atmac100";
 198                 reg = <0xe0100000 0x1000>;
 199                 interrupts = <19 4>;
 200                 interrupt-parent = <&plic0>;
 201         };
 202
 203         mmc0: mmc@f0e00000 {
 204                 compatible = "andestech,atfsdc010";
 205                 max-frequency = <100000000>;
 206                 clock-freq-min-max = <400000 100000000>;
 207                 fifo-depth = <0x10>;
 208                 reg = <0xf0e00000 0x1000>;
 209                 interrupts = <18 4>;
 210                 cap-sd-highspeed;
 211                 interrupt-parent = <&plic0>;
 212         };
 213
 214         dma0: dma@f0c00000 {
 215                 compatible = "andestech,atcdmac300";
 216                 reg = <0xf0c00000 0x1000>;
 217                 interrupts = <10 4 64 4 65 4 66 4 67 4 68 4 69 4 70 4 71 4>;
 218                 dma-channels = <8>;
 219                 interrupt-parent = <&plic0>;
 220         };
 221
 222         lcd0: lcd@e0200000 {
 223                 compatible = "andestech,atflcdc100";
 224                 reg = <0xe0200000 0x1000>;
 225                 interrupts = <20 4>;
 226                 interrupt-parent = <&plic0>;
 227         };
 228
 229         smc0: smc@e0400000 {
 230                 compatible = "andestech,atfsmc020";
 231                 reg = <0xe0400000 0x1000>;
 232         };
 233
 234         snd0: snd@f0d00000 {
 235                 compatible = "andestech,atfac97";
 236                 reg = <0xf0d00000 0x1000>;
 237                 interrupts = <17 4>;
 238                 interrupt-parent = <&plic0>;
 239         };
 240
 241         pmu {
 242                 compatible = "riscv,base-pmu";
 243         };
 244
 245         virtio_mmio@fe007000 {
 246                 interrupts = <0x17 0x4>;
 247                 interrupt-parent = <0x2>;
 248                 reg = <0xfe007000 0x1000>;
 249                 compatible = "virtio,mmio";
 250         };
 251
 252         virtio_mmio@fe006000 {
 253                 interrupts = <0x16 0x4>;
 254                 interrupt-parent = <0x2>;
 255                 reg = <0xfe006000 0x1000>;
 256                 compatible = "virtio,mmio";
 257         };
 258
 259         virtio_mmio@fe005000 {
 260                 interrupts = <0x15 0x4>;
 261                 interrupt-parent = <0x2>;
 262                 reg = <0xfe005000 0x1000>;
 263                 compatible = "virtio,mmio";
 264         };
 265
 266         virtio_mmio@fe004000 {
 267                 interrupts = <0x14 0x4>;
 268                 interrupt-parent = <0x2>;
 269                 reg = <0xfe004000 0x1000>;
 270                 compatible = "virtio,mmio";
 271         };
 272
 273         virtio_mmio@fe003000 {
 274                 interrupts = <0x13 0x4>;
 275                 interrupt-parent = <0x2>;
 276                 reg = <0xfe003000 0x1000>;
 277                 compatible = "virtio,mmio";
 278         };
 279
 280         virtio_mmio@fe002000 {
 281                 interrupts = <0x12 0x4>;
 282                 interrupt-parent = <0x2>;
 283                 reg = <0xfe002000 0x1000>;
 284                 compatible = "virtio,mmio";
 285         };
 286
 287         virtio_mmio@fe001000 {
 288                 interrupts = <0x11 0x4>;
 289                 interrupt-parent = <0x2>;
 290                 reg = <0xfe001000 0x1000>;
 291                 compatible = "virtio,mmio";
 292         };
 293
 294         virtio_mmio@fe000000 {
 295                 interrupts = <0x10 0x4>;
 296                 interrupt-parent = <0x2>;
 297                 reg = <0xfe000000 0x1000>;
 298                 compatible = "virtio,mmio";
 299         };
 300
 301         nor@0,0 {
 302                 #address-cells = <1>;
 303                 #size-cells = <1>;
 304                 compatible = "cfi-flash";
 305                 reg = <0x88000000 0x4000000>;
 306                 bank-width = <2>;
 307                 device-width = <1>;
 308         };
 309
 310         spi: spi@f0b00000 {
 311                 compatible = "andestech,atcspi200";
 312                 reg = <0xf0b00000 0x1000>;
 313                 #address-cells = <1>;
 314                 #size-cells = <0>;
 315                 num-cs = <1>;
 316                 clocks = <&spiclk>;
 317                 interrupts = <4 4>;
 318                 interrupt-parent = <&plic0>;
 319                 flash@0 {
 320                         compatible = "jedec,spi-nor";
 321                         spi-max-frequency = <50000000>;
 322                         reg = <0>;
 323                         spi-cpol;
 324                         spi-cpha;
 325                 };
 326         };
 327 };