arch/riscv/dts/ae350.dts

   1 /dts-v1/;
   2
   3 / {
   4         #address-cells = <2>;
   5         #size-cells = <2>;
   6         compatible = "andestech,ax25";
   7         model = "andestech,ax25";
   8
   9         aliases {
  10                 uart0 = &serial0;
  11                 spi0 = &spi;
  12         };
  13
  14         chosen {
  15                 bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
  16                 stdout-path = "uart0:38400n8";
  17         };
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22                 timebase-frequency = <10000000>;
  23
  24                 CPU0: cpu@0 {
  25                         device_type = "cpu";
  26                         reg = <0>;
  27                         status = "okay";
  28                         compatible = "riscv";
  29                         riscv,isa = "rv64imafdc";
  30                         mmu-type = "riscv,sv39";
  31                         clock-frequency = <60000000>;
  32
  33                         CPU0_intc: interrupt-controller {
  34                                 #interrupt-cells = <1>;
  35                                 interrupt-controller;
  36                                 compatible = "riscv,cpu-intc";
  37                         };
  38                 };
  39         };
  40
  41         memory@0 {
  42                 device_type = "memory";
  43                 reg = <0x0 0x00000000 0x0 0x40000000>;
  44         };
  45
  46         soc {
  47                 #address-cells = <2>;
  48                 #size-cells = <2>;
  49                 compatible = "andestech,riscv-ae350-soc";
  50                 ranges;
  51         };
  52
  53         plmt0@e6000000 {
  54                 compatible = "riscv,plmt0";
  55                 interrupts-extended = <&CPU0_intc 7>;
  56                 reg = <0x0 0xe6000000 0x0 0x100000>;
  57         };
  58
  59         plic0: interrupt-controller@e4000000 {
  60                 compatible = "riscv,plic0";
  61                 #address-cells = <2>;
  62                 #interrupt-cells = <2>;
  63                 interrupt-controller;
  64                 reg = <0x0 0xe4000000 0x0 0x2000000>;
  65                 riscv,ndev=<31>;
  66                 interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
  67         };
  68
  69         plic1: interrupt-controller@e6400000 {
  70                 compatible = "riscv,plic1";
  71                 #address-cells = <2>;
  72                 #interrupt-cells = <2>;
  73                 interrupt-controller;
  74                 reg = <0x0 0xe6400000 0x0 0x400000>;
  75                 riscv,ndev=<1>;
  76                 interrupts-extended = <&CPU0_intc 3>;
  77         };
  78
  79         spiclk: virt_100mhz {
  80                 #clock-cells = <0>;
  81                 compatible = "fixed-clock";
  82                 clock-frequency = <100000000>;
  83         };
  84
  85         timer0: timer@f0400000 {
  86                 compatible = "andestech,atcpit100";
  87                 reg = <0x0 0xf0400000 0x0 0x1000>;
  88                 clock-frequency = <40000000>;
  89                 interrupts = <3 4>;
  90                 interrupt-parent = <&plic0>;
  91         };
  92
  93         serial0: serial@f0300000 {
  94                 compatible = "andestech,uart16550", "ns16550a";
  95                 reg = <0x0 0xf0300000 0x0 0x1000>;
  96                 interrupts = <9 4>;
  97                 clock-frequency = <19660800>;
  98                 reg-shift = <2>;
  99                 reg-offset = <32>;
 100                 no-loopback-test = <1>;
 101                 interrupt-parent = <&plic0>;
 102         };
 103
 104         mac0: mac@e0100000 {
 105                 compatible = "andestech,atmac100";
 106                 reg = <0x0 0xe0100000 0x0 0x1000>;
 107                 interrupts = <19 4>;
 108                 interrupt-parent = <&plic0>;
 109         };
 110
 111         mmc0: mmc@f0e00000 {
 112                 compatible = "andestech,atfsdc010";
 113                 max-frequency = <100000000>;
 114                 clock-freq-min-max = <400000 100000000>;
 115                 fifo-depth = <0x10>;
 116                 reg = <0x0 0xf0e00000 0x0 0x1000>;
 117                 interrupts = <18 4>;
 118                 cap-sd-highspeed;
 119                 interrupt-parent = <&plic0>;
 120         };
 121
 122         smc0: smc@e0400000 {
 123                 compatible = "andestech,atfsmc020";
 124                 reg = <0x0 0xe0400000 0x0 0x1000>;
 125         };
 126
 127         nor@0,0 {
 128                 compatible = "cfi-flash";
 129                 reg = <0x0 0x88000000 0x0 0x1000>;
 130                 bank-width = <2>;
 131                 device-width = <1>;
 132         };
 133
 134         spi: spi@f0b00000 {
 135                 compatible = "andestech,atcspi200";
 136                 reg = <0x0 0xf0b00000 0x0 0x1000>;
 137                 #address-cells = <1>;
 138                 #size-cells = <0>;
 139                 num-cs = <1>;
 140                 clocks = <&spiclk>;
 141                 interrupts = <3 4>;
 142                 interrupt-parent = <&plic0>;
 143
 144                 flash@0 {
 145                         compatible = "spi-flash";
 146                         spi-max-frequency = <50000000>;
 147                         reg = <0>;
 148                         spi-cpol;
 149                         spi-cpha;
 150                 };
 151         };
 152 };