1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <asm/encoding.h>
17 #include <generated/asm-offsets.h>
23 #define RELOC_TYPE R_RISCV_32
30 #define RELOC_TYPE R_RISCV_64
31 #define SYM_INDEX 0x20
36 secondary_harts_relocation_error:
37 .ascii "Relocation of secondary harts has failed, error %d\n"
42 #if CONFIG_IS_ENABLED(RISCV_MMODE)
47 * Save hart id and dtb pointer. The thread pointer register is not
48 * modified by C code. It is used by secondary_hart_loop.
54 * Set the global data pointer to a known value in case we get a very
55 * early trap. The global data pointer will be set its actual value only
56 * after it has been initialized.
61 * Set the trap handler. This must happen after initializing gp because
62 * the handler may use it.
65 csrw MODE_PREFIX(tvec), t0
68 * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
69 * for U-Boot, but we will need to read m/sip to determine if we get an
72 csrw MODE_PREFIX(ie), zero
74 #if CONFIG_IS_ENABLED(SMP)
75 /* check if hart is within range */
78 bge tp, t0, hart_out_of_bounds_loop
80 /* set xSIE bit to receive IPIs */
81 #if CONFIG_IS_ENABLED(RISCV_MMODE)
86 csrs MODE_PREFIX(ie), t0
90 * Set stackpointer in internal/ex RAM to call board_init_f
94 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
95 li t1, CONFIG_SPL_STACK
97 li t1, CONFIG_SYS_INIT_SP_ADDR
99 and sp, t1, t0 /* force 16 byte alignment */
103 jal board_init_f_alloc_reserve
106 * Save global data pointer for later. We don't set it here because it
107 * is not initialized yet.
112 #if CONFIG_IS_ENABLED(SMP)
114 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
122 * Pick hart to initialize global data and run U-Boot. The other harts
123 * wait for initialization to complete.
127 amoswap.w s2, t1, 0(t0)
128 bnez s2, wait_for_gd_init
131 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
132 * encounters a pending IPI on boot it is liable to jump to whatever
133 * memory happens to be in ipi_data.addr on boot. It may also run into
134 * problems if it encounters an exception too early (because printf/puts
138 bnez tp, secondary_hart_loop
141 #ifdef CONFIG_OF_PRIOR_STAGE
142 la t0, prior_stage_fdt_address
146 jal board_init_f_init_reserve
148 SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
149 /* save the boot hart id to global_data */
150 SREG tp, GD_BOOT_HART(gp)
153 la t0, available_harts_lock
154 amoswap.w.rl zero, zero, 0(t0)
157 la t0, available_harts_lock
159 1: amoswap.w.aq t1, t1, 0(t0)
163 * Set the global data pointer only when gd_t has been initialized.
164 * This was already set by arch_setup_gd on the boot hart, but all other
165 * harts' global data pointers gets set here.
169 /* register available harts in the available_harts mask */
172 LREG t2, GD_AVAILABLE_HARTS(gp)
174 SREG t2, GD_AVAILABLE_HARTS(gp)
176 amoswap.w.rl zero, zero, 0(t0)
179 * Continue on hart lottery winner, others branch to
180 * secondary_hart_loop.
182 bnez s2, secondary_hart_loop
189 #ifdef CONFIG_DEBUG_UART
193 mv a0, zero /* a0 <-- boot_flags = 0 */
195 jalr t5 /* jump to board_init_f() */
197 #ifdef CONFIG_SPL_BUILD
201 beq t0, t1, spl_stack_gd_setup
205 addi t0, t0, REGBYTES
206 blt t0, t1, spl_clear_bss_loop
209 jal spl_relocate_stack_gd
211 /* skip setup if we did not relocate */
212 beqz a0, spl_call_board_init_r
215 /* setup stack on main hart */
216 #if CONFIG_IS_ENABLED(SMP)
218 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
224 #if CONFIG_IS_ENABLED(SMP)
225 /* set new stack and global data pointer on secondary harts */
226 spl_secondary_hart_stack_gd_setup:
227 la a0, secondary_hart_relocate
231 jal smp_call_function
233 /* hang if relocation of secondary harts has failed */
236 la a0, secondary_harts_relocation_error
241 /* set new global data pointer on main hart */
244 spl_call_board_init_r:
251 * void relocate_code(addr_sp, gd, addr_moni)
253 * This "function" does not return, instead it continues in RAM
254 * after relocating the monitor code.
259 mv s2, a0 /* save addr_sp */
260 mv s3, a1 /* save addr of gd */
261 mv s4, a2 /* save addr of destination */
267 #if CONFIG_IS_ENABLED(SMP)
269 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
276 sub t6, s4, t0 /* t6 <- relocation offset */
277 beq t0, s4, clear_bss /* skip relocation */
279 mv t1, s4 /* t1 <- scratch for copy_loop */
281 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
282 add t2, t0, t3 /* t2 <- source end address */
286 addi t0, t0, REGBYTES
288 addi t1, t1, REGBYTES
289 blt t0, t2, copy_loop
292 * Update dynamic relocations after board_init_f
295 la t1, __rel_dyn_start
297 beq t1, t2, clear_bss
298 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
299 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
302 * skip first reserved entry: address, type, addend
307 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
308 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
309 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
310 LREG t3, -(REGBYTES*3)(t1)
311 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
312 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
313 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
318 la t4, __dyn_sym_start
322 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
323 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
324 andi t5, t5, 0xFF /* t5 <--- relocation type */
326 bne t5, t3, 10f /* skip non-addned entries */
328 LREG t3, -(REGBYTES*3)(t1)
332 LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
333 LREG t5, REGBYTES(s5)
335 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
336 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
339 addi t1, t1, (REGBYTES*3)
347 csrw MODE_PREFIX(tvec), t0
350 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
351 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
352 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
353 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
354 beq t0, t1, relocate_secondary_harts
357 SREG zero, 0(t0) /* clear loop... */
358 addi t0, t0, REGBYTES
361 relocate_secondary_harts:
362 #if CONFIG_IS_ENABLED(SMP)
363 /* send relocation IPI */
364 la t0, secondary_hart_relocate
367 /* store relocation offset */
373 jal smp_call_function
375 /* hang if relocation of secondary harts has failed */
378 la a0, secondary_harts_relocation_error
382 /* restore relocation offset */
387 * We are done. Do not return, instead branch to second part of board
388 * initialization, now running from RAM.
391 jal invalidate_icache_all
393 la t0, board_init_r /* offset of board_init_r() */
394 add t4, t0, t6 /* real address of board_init_r() */
396 * setup parameters for board_init_r
399 mv a1, s4 /* dest_addr */
404 jr t4 /* jump to board_init_r() */
406 #if CONFIG_IS_ENABLED(SMP)
407 hart_out_of_bounds_loop:
408 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
410 j hart_out_of_bounds_loop
412 /* SMP relocation entry */
413 secondary_hart_relocate:
419 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
422 /* update global data pointer */
427 * Interrupts are disabled globally, but they can still be read from m/sip. The
428 * wfi function will wake us up if we get an IPI, even if we do not trap.
433 #if CONFIG_IS_ENABLED(SMP)
434 csrr t0, MODE_PREFIX(ip)
435 #if CONFIG_IS_ENABLED(RISCV_MMODE)
436 andi t0, t0, MIE_MSIE
438 andi t0, t0, SIE_SSIE
440 beqz t0, secondary_hart_loop
446 j secondary_hart_loop