1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <asm/encoding.h>
17 #include <generated/asm-offsets.h>
23 #define RELOC_TYPE R_RISCV_32
30 #define RELOC_TYPE R_RISCV_64
31 #define SYM_INDEX 0x20
36 secondary_harts_relocation_error:
37 .ascii "Relocation of secondary harts has failed, error %d\n"
42 #if CONFIG_IS_ENABLED(RISCV_MMODE)
46 /* save hart id and dtb pointer */
51 csrw MODE_PREFIX(tvec), t0
53 /* mask all interrupts */
54 csrw MODE_PREFIX(ie), zero
56 #if CONFIG_IS_ENABLED(SMP)
57 /* check if hart is within range */
60 bge tp, t0, hart_out_of_bounds_loop
62 /* set xSIE bit to receive IPIs */
63 #if CONFIG_IS_ENABLED(RISCV_MMODE)
68 /* Clear any pending IPIs */
69 csrc MODE_PREFIX(ip), t0
70 csrs MODE_PREFIX(ie), t0
74 * Set stackpointer in internal/ex RAM to call board_init_f
78 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
79 li t1, CONFIG_SPL_STACK
81 li t1, CONFIG_SYS_INIT_SP_ADDR
83 and sp, t1, t0 /* force 16 byte alignment */
87 jal board_init_f_alloc_reserve
90 * Set global data pointer here for all harts, uninitialized at this
96 #if CONFIG_IS_ENABLED(SMP)
98 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
106 * Pick hart to initialize global data and run U-Boot. The other harts
107 * wait for initialization to complete.
111 amoswap.w s2, t1, 0(t0)
112 bnez s2, wait_for_gd_init
114 bnez tp, secondary_hart_loop
117 #ifdef CONFIG_OF_PRIOR_STAGE
118 la t0, prior_stage_fdt_address
122 jal board_init_f_init_reserve
124 SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
125 /* save the boot hart id to global_data */
126 SREG tp, GD_BOOT_HART(gp)
129 la t0, available_harts_lock
131 amoswap.w zero, zero, 0(t0)
134 la t0, available_harts_lock
136 1: amoswap.w t1, t1, 0(t0)
140 /* register available harts in the available_harts mask */
143 LREG t2, GD_AVAILABLE_HARTS(gp)
145 SREG t2, GD_AVAILABLE_HARTS(gp)
148 amoswap.w zero, zero, 0(t0)
151 * Continue on hart lottery winner, others branch to
152 * secondary_hart_loop.
154 bnez s2, secondary_hart_loop
161 #ifdef CONFIG_DEBUG_UART
165 mv a0, zero /* a0 <-- boot_flags = 0 */
167 jalr t5 /* jump to board_init_f() */
169 #ifdef CONFIG_SPL_BUILD
173 beq t0, t1, spl_stack_gd_setup
177 addi t0, t0, REGBYTES
178 blt t0, t1, spl_clear_bss_loop
181 jal spl_relocate_stack_gd
183 /* skip setup if we did not relocate */
184 beqz a0, spl_call_board_init_r
187 /* setup stack on main hart */
188 #if CONFIG_IS_ENABLED(SMP)
190 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
196 #if CONFIG_IS_ENABLED(SMP)
197 /* set new stack and global data pointer on secondary harts */
198 spl_secondary_hart_stack_gd_setup:
199 la a0, secondary_hart_relocate
203 jal smp_call_function
205 /* hang if relocation of secondary harts has failed */
208 la a0, secondary_harts_relocation_error
213 /* set new global data pointer on main hart */
216 spl_call_board_init_r:
223 * void relocate_code(addr_sp, gd, addr_moni)
225 * This "function" does not return, instead it continues in RAM
226 * after relocating the monitor code.
231 mv s2, a0 /* save addr_sp */
232 mv s3, a1 /* save addr of gd */
233 mv s4, a2 /* save addr of destination */
239 #if CONFIG_IS_ENABLED(SMP)
241 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
248 sub t6, s4, t0 /* t6 <- relocation offset */
249 beq t0, s4, clear_bss /* skip relocation */
251 mv t1, s4 /* t1 <- scratch for copy_loop */
253 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
254 add t2, t0, t3 /* t2 <- source end address */
258 addi t0, t0, REGBYTES
260 addi t1, t1, REGBYTES
261 blt t0, t2, copy_loop
264 * Update dynamic relocations after board_init_f
267 la t1, __rel_dyn_start
269 beq t1, t2, clear_bss
270 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
271 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
274 * skip first reserved entry: address, type, addend
279 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
280 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
281 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
282 LREG t3, -(REGBYTES*3)(t1)
283 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
284 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
285 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
290 la t4, __dyn_sym_start
294 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
295 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
296 andi t5, t5, 0xFF /* t5 <--- relocation type */
298 bne t5, t3, 10f /* skip non-addned entries */
300 LREG t3, -(REGBYTES*3)(t1)
304 LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
305 LREG t5, REGBYTES(s5)
307 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
308 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
311 addi t1, t1, (REGBYTES*3)
319 csrw MODE_PREFIX(tvec), t0
322 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
323 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
324 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
325 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
326 beq t0, t1, relocate_secondary_harts
329 SREG zero, 0(t0) /* clear loop... */
330 addi t0, t0, REGBYTES
333 relocate_secondary_harts:
334 #if CONFIG_IS_ENABLED(SMP)
335 /* send relocation IPI */
336 la t0, secondary_hart_relocate
339 /* store relocation offset */
345 jal smp_call_function
347 /* hang if relocation of secondary harts has failed */
350 la a0, secondary_harts_relocation_error
354 /* restore relocation offset */
359 * We are done. Do not return, instead branch to second part of board
360 * initialization, now running from RAM.
363 jal invalidate_icache_all
365 la t0, board_init_r /* offset of board_init_r() */
366 add t4, t0, t6 /* real address of board_init_r() */
368 * setup parameters for board_init_r
371 mv a1, s4 /* dest_addr */
376 jr t4 /* jump to board_init_r() */
378 #if CONFIG_IS_ENABLED(SMP)
379 hart_out_of_bounds_loop:
380 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
382 j hart_out_of_bounds_loop
384 /* SMP relocation entry */
385 secondary_hart_relocate:
391 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
394 /* update global data pointer */
401 #if CONFIG_IS_ENABLED(SMP)
402 csrr t0, MODE_PREFIX(ip)
403 #if CONFIG_IS_ENABLED(RISCV_MMODE)
404 andi t0, t0, MIE_MSIE
406 andi t0, t0, SIE_SSIE
408 beqz t0, secondary_hart_loop
414 j secondary_hart_loop