1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <system-constants.h>
17 #include <asm/encoding.h>
18 #include <generated/asm-offsets.h>
24 #define RELOC_TYPE R_RISCV_32
31 #define RELOC_TYPE R_RISCV_64
32 #define SYM_INDEX 0x20
37 secondary_harts_relocation_error:
38 .ascii "Relocation of secondary harts has failed, error %d\n"
43 #if CONFIG_IS_ENABLED(RISCV_MMODE)
48 * Save hart id and dtb pointer. The thread pointer register is not
49 * modified by C code. It is used by secondary_hart_loop.
55 * Set the global data pointer to a known value in case we get a very
56 * early trap. The global data pointer will be set its actual value only
57 * after it has been initialized.
62 * Set the trap handler. This must happen after initializing gp because
63 * the handler may use it.
66 csrw MODE_PREFIX(tvec), t0
69 * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
70 * for U-Boot, but we will need to read m/sip to determine if we get an
73 csrw MODE_PREFIX(ie), zero
75 #if CONFIG_IS_ENABLED(SMP)
76 /* check if hart is within range */
79 bge tp, t0, hart_out_of_bounds_loop
81 /* set xSIE bit to receive IPIs */
82 #if CONFIG_IS_ENABLED(RISCV_MMODE)
87 csrs MODE_PREFIX(ie), t0
91 * Set stackpointer in internal/ex RAM to call board_init_f
94 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
95 li t0, CONFIG_SPL_STACK
97 li t0, SYS_INIT_SP_ADDR
99 and t0, t0, -16 /* force 16 byte alignment */
102 #if CONFIG_IS_ENABLED(SMP)
104 slli t1, tp, CONFIG_STACK_SIZE_SHIFT
110 * Now sp points to the right stack belonging to current CPU.
111 * It's essential before any function call, otherwise, we get data-race.
114 /* clear stack if necessary */
115 #if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
118 slli t1, t1, CONFIG_STACK_SIZE_SHIFT
121 SREG zero, 0(t1) /* t1 is always 16 byte aligned */
122 addi t1, t1, REGBYTES
123 blt t1, sp, clear_stack_loop
127 /* find top of reserve space */
128 #if CONFIG_IS_ENABLED(SMP)
129 li t1, CONFIG_NR_CPUS
133 slli t1, t1, CONFIG_STACK_SIZE_SHIFT
134 sub a0, t0, t1 /* t1 -> size of all CPU stacks */
135 jal board_init_f_alloc_reserve
138 * Save global data pointer for later. We don't set it here because it
139 * is not initialized yet.
144 /* Configure proprietary settings and customized CSRs of harts */
145 call_harts_early_init:
148 #if !CONFIG_IS_ENABLED(XIP)
150 * Pick hart to initialize global data and run U-Boot. The other harts
151 * wait for initialization to complete.
155 amoswap.w s2, t1, 0(t0)
156 bnez s2, wait_for_gd_init
159 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
160 * encounters a pending IPI on boot it is liable to jump to whatever
161 * memory happens to be in ipi_data.addr on boot. It may also run into
162 * problems if it encounters an exception too early (because printf/puts
166 #if CONFIG_IS_ENABLED(RISCV_MMODE)
167 bnez tp, secondary_hart_loop
172 jal board_init_f_init_reserve
174 SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
175 /* save the boot hart id to global_data */
176 SREG tp, GD_BOOT_HART(gp)
178 #if !CONFIG_IS_ENABLED(XIP)
179 #ifdef CONFIG_AVAILABLE_HARTS
180 la t0, available_harts_lock
181 amoswap.w.rl zero, zero, 0(t0)
186 * Set the global data pointer only when gd_t has been initialized.
187 * This was already set by arch_setup_gd on the boot hart, but all other
188 * harts' global data pointers gets set here.
191 #ifdef CONFIG_AVAILABLE_HARTS
192 la t0, available_harts_lock
194 1: amoswap.w.aq t1, t1, 0(t0)
197 /* register available harts in the available_harts mask */
200 LREG t2, GD_AVAILABLE_HARTS(gp)
202 SREG t2, GD_AVAILABLE_HARTS(gp)
204 amoswap.w.rl zero, zero, 0(t0)
208 * Continue on hart lottery winner, others branch to
209 * secondary_hart_loop.
211 bnez s2, secondary_hart_loop
218 #ifdef CONFIG_DEBUG_UART
222 mv a0, zero /* a0 <-- boot_flags = 0 */
224 jalr t5 /* jump to board_init_f() */
226 #ifdef CONFIG_SPL_BUILD
230 beq t0, t1, spl_stack_gd_setup
234 addi t0, t0, REGBYTES
235 blt t0, t1, spl_clear_bss_loop
238 jal spl_relocate_stack_gd
240 /* skip setup if we did not relocate */
241 beqz a0, spl_call_board_init_r
244 /* setup stack on main hart */
245 #if CONFIG_IS_ENABLED(SMP)
247 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
253 #if CONFIG_IS_ENABLED(SMP)
254 /* set new stack and global data pointer on secondary harts */
255 spl_secondary_hart_stack_gd_setup:
256 la a0, secondary_hart_relocate
260 jal smp_call_function
262 /* hang if relocation of secondary harts has failed */
265 la a0, secondary_harts_relocation_error
270 /* set new global data pointer on main hart */
273 spl_call_board_init_r:
279 #if !defined(CONFIG_SPL_BUILD)
281 * void relocate_code(addr_sp, gd, addr_moni)
283 * This "function" does not return, instead it continues in RAM
284 * after relocating the monitor code.
289 mv s2, a0 /* save addr_sp */
290 mv s3, a1 /* save addr of gd */
291 mv s4, a2 /* save addr of destination */
297 #if CONFIG_IS_ENABLED(SMP)
299 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
306 sub t6, s4, t0 /* t6 <- relocation offset */
307 beq t0, s4, clear_bss /* skip relocation */
309 mv t1, s4 /* t1 <- scratch for copy_loop */
310 la t2, __bss_start /* t2 <- source end address */
314 addi t0, t0, REGBYTES
316 addi t1, t1, REGBYTES
317 blt t0, t2, copy_loop
320 * Update dynamic relocations after board_init_f
323 la t1, __rel_dyn_start
325 beq t1, t2, clear_bss
326 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
327 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
330 LREG t5, REGBYTES(t1) /* t5 <-- relocation info:type */
331 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
332 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
334 LREG t5, (REGBYTES * 2)(t1) /* t5 <-- addend */
335 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
336 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
341 la t4, __dyn_sym_start
345 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
346 andi t5, t5, 0xFF /* t5 <--- relocation type */
348 bne t5, t3, 10f /* skip non-addned entries */
354 LREG t0, (REGBYTES * 2)(t1) /* t0 <-- addend */
355 LREG t5, REGBYTES(s5)
357 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
358 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
361 addi t1, t1, (REGBYTES * 3)
369 csrw MODE_PREFIX(tvec), t0
372 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
373 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
374 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
375 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
376 beq t0, t1, relocate_secondary_harts
379 SREG zero, 0(t0) /* clear loop... */
380 addi t0, t0, REGBYTES
383 relocate_secondary_harts:
384 #if CONFIG_IS_ENABLED(SMP)
385 /* send relocation IPI */
386 la t0, secondary_hart_relocate
389 /* store relocation offset */
395 jal smp_call_function
397 /* hang if relocation of secondary harts has failed */
400 la a0, secondary_harts_relocation_error
404 /* restore relocation offset */
409 * We are done. Do not return, instead branch to second part of board
410 * initialization, now running from RAM.
413 jal invalidate_icache_all
415 la t0, board_init_r /* offset of board_init_r() */
416 add t4, t0, t6 /* real address of board_init_r() */
418 * setup parameters for board_init_r
421 mv a1, s4 /* dest_addr */
426 jr t4 /* jump to board_init_r() */
427 #endif /* !defined(CONFIG_SPL_BUILD) */
429 #if CONFIG_IS_ENABLED(SMP)
430 hart_out_of_bounds_loop:
431 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
433 j hart_out_of_bounds_loop
435 /* SMP relocation entry */
436 secondary_hart_relocate:
442 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
445 /* update global data pointer */
450 * Interrupts are disabled globally, but they can still be read from m/sip. The
451 * wfi function will wake us up if we get an IPI, even if we do not trap.
456 #if CONFIG_IS_ENABLED(SMP)
457 csrr t0, MODE_PREFIX(ip)
458 #if CONFIG_IS_ENABLED(RISCV_MMODE)
459 andi t0, t0, MIE_MSIE
461 andi t0, t0, SIE_SSIE
463 beqz t0, secondary_hart_loop
469 j secondary_hart_loop