1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <asm/encoding.h>
17 #include <generated/asm-offsets.h>
23 #define RELOC_TYPE R_RISCV_32
30 #define RELOC_TYPE R_RISCV_64
31 #define SYM_INDEX 0x20
36 secondary_harts_relocation_error:
37 .ascii "Relocation of secondary harts has failed, error %d\n"
42 #if CONFIG_IS_ENABLED(RISCV_MMODE)
46 /* save hart id and dtb pointer */
51 csrw MODE_PREFIX(tvec), t0
53 /* mask all interrupts */
54 csrw MODE_PREFIX(ie), zero
56 #if CONFIG_IS_ENABLED(SMP)
57 /* check if hart is within range */
60 bge tp, t0, hart_out_of_bounds_loop
62 /* set xSIE bit to receive IPIs */
63 #if CONFIG_IS_ENABLED(RISCV_MMODE)
68 csrs MODE_PREFIX(ie), t0
72 * Set stackpointer in internal/ex RAM to call board_init_f
76 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
77 li t1, CONFIG_SPL_STACK
79 li t1, CONFIG_SYS_INIT_SP_ADDR
81 and sp, t1, t0 /* force 16 byte alignment */
85 jal board_init_f_alloc_reserve
88 * Set global data pointer here for all harts, uninitialized at this
94 #if CONFIG_IS_ENABLED(SMP)
96 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
104 * Pick hart to initialize global data and run U-Boot. The other harts
105 * wait for initialization to complete.
109 amoswap.w s2, t1, 0(t0)
110 bnez s2, wait_for_gd_init
112 bnez tp, secondary_hart_loop
115 #ifdef CONFIG_OF_PRIOR_STAGE
116 la t0, prior_stage_fdt_address
120 jal board_init_f_init_reserve
122 /* save the boot hart id to global_data */
123 SREG tp, GD_BOOT_HART(gp)
126 la t0, available_harts_lock
128 amoswap.w zero, zero, 0(t0)
131 la t0, available_harts_lock
133 1: amoswap.w t1, t1, 0(t0)
137 /* register available harts in the available_harts mask */
140 LREG t2, GD_AVAILABLE_HARTS(gp)
142 SREG t2, GD_AVAILABLE_HARTS(gp)
145 amoswap.w zero, zero, 0(t0)
148 * Continue on hart lottery winner, others branch to
149 * secondary_hart_loop.
151 bnez s2, secondary_hart_loop
158 #ifdef CONFIG_DEBUG_UART
162 mv a0, zero /* a0 <-- boot_flags = 0 */
164 jalr t5 /* jump to board_init_f() */
166 #ifdef CONFIG_SPL_BUILD
170 beq t0, t1, spl_stack_gd_setup
174 addi t0, t0, REGBYTES
175 blt t0, t1, spl_clear_bss_loop
178 jal spl_relocate_stack_gd
180 /* skip setup if we did not relocate */
181 beqz a0, spl_call_board_init_r
184 /* setup stack on main hart */
185 #if CONFIG_IS_ENABLED(SMP)
187 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
193 /* set new stack and global data pointer on secondary harts */
194 spl_secondary_hart_stack_gd_setup:
195 la a0, secondary_hart_relocate
199 jal smp_call_function
201 /* hang if relocation of secondary harts has failed */
204 la a0, secondary_harts_relocation_error
208 /* set new global data pointer on main hart */
211 spl_call_board_init_r:
218 * void relocate_code(addr_sp, gd, addr_moni)
220 * This "function" does not return, instead it continues in RAM
221 * after relocating the monitor code.
226 mv s2, a0 /* save addr_sp */
227 mv s3, a1 /* save addr of gd */
228 mv s4, a2 /* save addr of destination */
234 #if CONFIG_IS_ENABLED(SMP)
236 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
243 sub t6, s4, t0 /* t6 <- relocation offset */
244 beq t0, s4, clear_bss /* skip relocation */
246 mv t1, s4 /* t1 <- scratch for copy_loop */
248 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
249 add t2, t0, t3 /* t2 <- source end address */
253 addi t0, t0, REGBYTES
255 addi t1, t1, REGBYTES
256 blt t0, t2, copy_loop
259 * Update dynamic relocations after board_init_f
262 la t1, __rel_dyn_start
264 beq t1, t2, clear_bss
265 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
266 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
269 * skip first reserved entry: address, type, addend
274 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
275 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
276 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
277 LREG t3, -(REGBYTES*3)(t1)
278 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
279 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
280 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
285 la t4, __dyn_sym_start
289 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
290 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
291 andi t5, t5, 0xFF /* t5 <--- relocation type */
293 bne t5, t3, 10f /* skip non-addned entries */
295 LREG t3, -(REGBYTES*3)(t1)
299 LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
300 LREG t5, REGBYTES(s5)
302 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
303 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
306 addi t1, t1, (REGBYTES*3)
314 csrw MODE_PREFIX(tvec), t0
317 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
318 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
319 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
320 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
321 beq t0, t1, relocate_secondary_harts
324 SREG zero, 0(t0) /* clear loop... */
325 addi t0, t0, REGBYTES
328 relocate_secondary_harts:
329 #if CONFIG_IS_ENABLED(SMP)
330 /* send relocation IPI */
331 la t0, secondary_hart_relocate
334 /* store relocation offset */
340 jal smp_call_function
342 /* hang if relocation of secondary harts has failed */
345 la a0, secondary_harts_relocation_error
349 /* restore relocation offset */
354 * We are done. Do not return, instead branch to second part of board
355 * initialization, now running from RAM.
358 jal invalidate_icache_all
360 la t0, board_init_r /* offset of board_init_r() */
361 add t4, t0, t6 /* real address of board_init_r() */
363 * setup parameters for board_init_r
366 mv a1, s4 /* dest_addr */
371 jr t4 /* jump to board_init_r() */
373 #if CONFIG_IS_ENABLED(SMP)
374 hart_out_of_bounds_loop:
375 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
377 j hart_out_of_bounds_loop
379 /* SMP relocation entry */
380 secondary_hart_relocate:
386 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
389 /* update global data pointer */
396 #if CONFIG_IS_ENABLED(SMP)
397 csrr t0, MODE_PREFIX(ip)
398 #if CONFIG_IS_ENABLED(RISCV_MMODE)
399 andi t0, t0, MIE_MSIE
401 andi t0, t0, SIE_SSIE
403 beqz t0, secondary_hart_loop
409 j secondary_hart_loop