1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
17 #include <asm/encoding.h>
18 #include <generated/asm-offsets.h>
24 #define RELOC_TYPE R_RISCV_32
31 #define RELOC_TYPE R_RISCV_64
32 #define SYM_INDEX 0x20
37 secondary_harts_relocation_error:
38 .ascii "Relocation of secondary harts has failed, error %d\n"
43 #ifdef CONFIG_RISCV_MMODE
47 /* save hart id and dtb pointer */
52 csrw MODE_PREFIX(tvec), t0
54 /* mask all interrupts */
55 csrw MODE_PREFIX(ie), zero
58 /* check if hart is within range */
61 bge tp, t0, hart_out_of_bounds_loop
65 /* set xSIE bit to receive IPIs */
66 #ifdef CONFIG_RISCV_MMODE
71 csrs MODE_PREFIX(ie), t0
75 * Set stackpointer in internal/ex RAM to call board_init_f
79 li t1, CONFIG_SYS_INIT_SP_ADDR
80 and sp, t1, t0 /* force 16 byte alignment */
84 jal board_init_f_alloc_reserve
87 * Set global data pointer here for all harts, uninitialized at this
95 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
103 * Pick hart to initialize global data and run U-Boot. The other harts
104 * wait for initialization to complete.
108 amoswap.w s2, t1, 0(t0)
109 bnez s2, wait_for_gd_init
111 bnez tp, secondary_hart_loop
114 #ifdef CONFIG_OF_PRIOR_STAGE
115 la t0, prior_stage_fdt_address
119 jal board_init_f_init_reserve
121 /* save the boot hart id to global_data */
122 SREG tp, GD_BOOT_HART(gp)
125 la t0, available_harts_lock
127 amoswap.w zero, zero, 0(t0)
130 la t0, available_harts_lock
132 1: amoswap.w t1, t1, 0(t0)
136 /* register available harts in the available_harts mask */
139 LREG t2, GD_AVAILABLE_HARTS(gp)
141 SREG t2, GD_AVAILABLE_HARTS(gp)
144 amoswap.w zero, zero, 0(t0)
147 * Continue on hart lottery winner, others branch to
148 * secondary_hart_loop.
150 bnez s2, secondary_hart_loop
157 #ifdef CONFIG_DEBUG_UART
161 mv a0, zero /* a0 <-- boot_flags = 0 */
163 jr t5 /* jump to board_init_f() */
166 * void relocate_code (addr_sp, gd, addr_moni)
168 * This "function" does not return, instead it continues in RAM
169 * after relocating the monitor code.
174 mv s2, a0 /* save addr_sp */
175 mv s3, a1 /* save addr of gd */
176 mv s4, a2 /* save addr of destination */
184 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
191 sub t6, s4, t0 /* t6 <- relocation offset */
192 beq t0, s4, clear_bss /* skip relocation */
194 mv t1, s4 /* t1 <- scratch for copy_loop */
196 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
197 add t2, t0, t3 /* t2 <- source end address */
201 addi t0, t0, REGBYTES
203 addi t1, t1, REGBYTES
204 blt t0, t2, copy_loop
207 * Update dynamic relocations after board_init_f
210 la t1, __rel_dyn_start
212 beq t1, t2, clear_bss
213 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
214 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
217 * skip first reserved entry: address, type, addend
222 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
223 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
224 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
225 LREG t3, -(REGBYTES*3)(t1)
226 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
227 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
228 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
231 addi t1, t1, (REGBYTES*3)
235 la t4, __dyn_sym_start
239 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
240 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
241 andi t5, t5, 0xFF /* t5 <--- relocation type */
243 bne t5, t3, 10f /* skip non-addned entries */
245 LREG t3, -(REGBYTES*3)(t1)
249 LREG t5, REGBYTES(s5)
250 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
251 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
254 addi t1, t1, (REGBYTES*3)
262 csrw MODE_PREFIX(tvec), t0
265 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
266 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
267 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
268 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
269 beq t0, t1, relocate_secondary_harts
272 SREG zero, 0(t0) /* clear loop... */
273 addi t0, t0, REGBYTES
276 relocate_secondary_harts:
278 /* send relocation IPI */
279 la t0, secondary_hart_relocate
282 /* store relocation offset */
287 jal smp_call_function
289 /* hang if relocation of secondary harts has failed */
292 la a0, secondary_harts_relocation_error
296 /* restore relocation offset */
301 * We are done. Do not return, instead branch to second part of board
302 * initialization, now running from RAM.
305 jal invalidate_icache_all
308 mv t4, t0 /* offset of board_init_r() */
309 add t4, t4, t6 /* real address of board_init_r() */
311 * setup parameters for board_init_r
314 mv a1, s4 /* dest_addr */
319 jr t4 /* jump to board_init_r() */
322 hart_out_of_bounds_loop:
323 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
325 j hart_out_of_bounds_loop
329 /* SMP relocation entry */
330 secondary_hart_relocate:
336 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
339 /* update global data pointer */
347 csrr t0, MODE_PREFIX(ip)
348 #ifdef CONFIG_RISCV_MMODE
349 andi t0, t0, MIE_MSIE
351 andi t0, t0, SIE_SSIE
353 beqz t0, secondary_hart_loop
359 j secondary_hart_loop