1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Startup Code for RISC-V Core
5 * Copyright (c) 2017 Microsemi Corporation.
6 * Copyright (c) 2017 Padmarao Begari <Padmarao.Begari@microsemi.com>
8 * Copyright (C) 2017 Andes Technology Corporation
9 * Rick Chen, Andes Technology Corporation <rick@andestech.com>
12 #include <asm-offsets.h>
16 #include <asm/encoding.h>
17 #include <generated/asm-offsets.h>
23 #define RELOC_TYPE R_RISCV_32
30 #define RELOC_TYPE R_RISCV_64
31 #define SYM_INDEX 0x20
36 secondary_harts_relocation_error:
37 .ascii "Relocation of secondary harts has failed, error %d\n"
42 #if CONFIG_IS_ENABLED(RISCV_MMODE)
47 * Save hart id and dtb pointer. The thread pointer register is not
48 * modified by C code. It is used by secondary_hart_loop.
54 * Set the global data pointer to a known value in case we get a very
55 * early trap. The global data pointer will be set its actual value only
56 * after it has been initialized.
61 * Set the trap handler. This must happen after initializing gp because
62 * the handler may use it.
65 csrw MODE_PREFIX(tvec), t0
68 * Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
69 * for U-Boot, but we will need to read m/sip to determine if we get an
72 csrw MODE_PREFIX(ie), zero
74 #if CONFIG_IS_ENABLED(SMP)
75 /* check if hart is within range */
78 bge tp, t0, hart_out_of_bounds_loop
80 /* set xSIE bit to receive IPIs */
81 #if CONFIG_IS_ENABLED(RISCV_MMODE)
86 csrs MODE_PREFIX(ie), t0
90 * Set stackpointer in internal/ex RAM to call board_init_f
94 #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_STACK)
95 li t1, CONFIG_SPL_STACK
97 li t1, CONFIG_SYS_INIT_SP_ADDR
99 and sp, t1, t0 /* force 16 byte alignment */
103 jal board_init_f_alloc_reserve
106 * Save global data pointer for later. We don't set it here because it
107 * is not initialized yet.
112 #if CONFIG_IS_ENABLED(SMP)
114 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
120 /* Configure proprietary settings and customized CSRs of harts */
121 call_harts_early_init:
126 * Pick hart to initialize global data and run U-Boot. The other harts
127 * wait for initialization to complete.
131 amoswap.w s2, t1, 0(t0)
132 bnez s2, wait_for_gd_init
135 * FIXME: gp is set before it is initialized. If an XIP U-Boot ever
136 * encounters a pending IPI on boot it is liable to jump to whatever
137 * memory happens to be in ipi_data.addr on boot. It may also run into
138 * problems if it encounters an exception too early (because printf/puts
142 bnez tp, secondary_hart_loop
145 jal board_init_f_init_reserve
147 SREG s1, GD_FIRMWARE_FDT_ADDR(gp)
148 /* save the boot hart id to global_data */
149 SREG tp, GD_BOOT_HART(gp)
152 la t0, available_harts_lock
153 amoswap.w.rl zero, zero, 0(t0)
156 la t0, available_harts_lock
158 1: amoswap.w.aq t1, t1, 0(t0)
162 * Set the global data pointer only when gd_t has been initialized.
163 * This was already set by arch_setup_gd on the boot hart, but all other
164 * harts' global data pointers gets set here.
168 /* register available harts in the available_harts mask */
171 LREG t2, GD_AVAILABLE_HARTS(gp)
173 SREG t2, GD_AVAILABLE_HARTS(gp)
175 amoswap.w.rl zero, zero, 0(t0)
178 * Continue on hart lottery winner, others branch to
179 * secondary_hart_loop.
181 bnez s2, secondary_hart_loop
188 #ifdef CONFIG_DEBUG_UART
192 mv a0, zero /* a0 <-- boot_flags = 0 */
194 jalr t5 /* jump to board_init_f() */
196 #ifdef CONFIG_SPL_BUILD
200 beq t0, t1, spl_stack_gd_setup
204 addi t0, t0, REGBYTES
205 blt t0, t1, spl_clear_bss_loop
208 jal spl_relocate_stack_gd
210 /* skip setup if we did not relocate */
211 beqz a0, spl_call_board_init_r
214 /* setup stack on main hart */
215 #if CONFIG_IS_ENABLED(SMP)
217 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
223 #if CONFIG_IS_ENABLED(SMP)
224 /* set new stack and global data pointer on secondary harts */
225 spl_secondary_hart_stack_gd_setup:
226 la a0, secondary_hart_relocate
230 jal smp_call_function
232 /* hang if relocation of secondary harts has failed */
235 la a0, secondary_harts_relocation_error
240 /* set new global data pointer on main hart */
243 spl_call_board_init_r:
250 * void relocate_code(addr_sp, gd, addr_moni)
252 * This "function" does not return, instead it continues in RAM
253 * after relocating the monitor code.
258 mv s2, a0 /* save addr_sp */
259 mv s3, a1 /* save addr of gd */
260 mv s4, a2 /* save addr of destination */
266 #if CONFIG_IS_ENABLED(SMP)
268 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
275 sub t6, s4, t0 /* t6 <- relocation offset */
276 beq t0, s4, clear_bss /* skip relocation */
278 mv t1, s4 /* t1 <- scratch for copy_loop */
280 sub t3, t3, t0 /* t3 <- __bss_start_ofs */
281 add t2, t0, t3 /* t2 <- source end address */
285 addi t0, t0, REGBYTES
287 addi t1, t1, REGBYTES
288 blt t0, t2, copy_loop
291 * Update dynamic relocations after board_init_f
294 la t1, __rel_dyn_start
296 beq t1, t2, clear_bss
297 add t1, t1, t6 /* t1 <- rela_dyn_start in RAM */
298 add t2, t2, t6 /* t2 <- rela_dyn_end in RAM */
301 * skip first reserved entry: address, type, addend
306 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
307 li t3, R_RISCV_RELATIVE /* reloc type R_RISCV_RELATIVE */
308 bne t5, t3, 8f /* skip non-RISCV_RELOC entries */
309 LREG t3, -(REGBYTES*3)(t1)
310 LREG t5, -(REGBYTES)(t1) /* t5 <-- addend */
311 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
312 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
317 la t4, __dyn_sym_start
321 LREG t5, -(REGBYTES*2)(t1) /* t5 <-- relocation info:type */
322 srli t0, t5, SYM_INDEX /* t0 <--- sym table index */
323 andi t5, t5, 0xFF /* t5 <--- relocation type */
325 bne t5, t3, 10f /* skip non-addned entries */
327 LREG t3, -(REGBYTES*3)(t1)
331 LREG t0, -(REGBYTES)(t1) /* t0 <-- addend */
332 LREG t5, REGBYTES(s5)
334 add t5, t5, t6 /* t5 <-- location to fix up in RAM */
335 add t3, t3, t6 /* t3 <-- location to fix up in RAM */
338 addi t1, t1, (REGBYTES*3)
346 csrw MODE_PREFIX(tvec), t0
349 la t0, __bss_start /* t0 <- rel __bss_start in FLASH */
350 add t0, t0, t6 /* t0 <- rel __bss_start in RAM */
351 la t1, __bss_end /* t1 <- rel __bss_end in FLASH */
352 add t1, t1, t6 /* t1 <- rel __bss_end in RAM */
353 beq t0, t1, relocate_secondary_harts
356 SREG zero, 0(t0) /* clear loop... */
357 addi t0, t0, REGBYTES
360 relocate_secondary_harts:
361 #if CONFIG_IS_ENABLED(SMP)
362 /* send relocation IPI */
363 la t0, secondary_hart_relocate
366 /* store relocation offset */
372 jal smp_call_function
374 /* hang if relocation of secondary harts has failed */
377 la a0, secondary_harts_relocation_error
381 /* restore relocation offset */
386 * We are done. Do not return, instead branch to second part of board
387 * initialization, now running from RAM.
390 jal invalidate_icache_all
392 la t0, board_init_r /* offset of board_init_r() */
393 add t4, t0, t6 /* real address of board_init_r() */
395 * setup parameters for board_init_r
398 mv a1, s4 /* dest_addr */
403 jr t4 /* jump to board_init_r() */
405 #if CONFIG_IS_ENABLED(SMP)
406 hart_out_of_bounds_loop:
407 /* Harts in this loop are out of bounds, increase CONFIG_NR_CPUS. */
409 j hart_out_of_bounds_loop
411 /* SMP relocation entry */
412 secondary_hart_relocate:
418 slli t0, tp, CONFIG_STACK_SIZE_SHIFT
421 /* update global data pointer */
426 * Interrupts are disabled globally, but they can still be read from m/sip. The
427 * wfi function will wake us up if we get an IPI, even if we do not trap.
432 #if CONFIG_IS_ENABLED(SMP)
433 csrr t0, MODE_PREFIX(ip)
434 #if CONFIG_IS_ENABLED(RISCV_MMODE)
435 andi t0, t0, MIE_MSIE
437 andi t0, t0, SIE_SSIE
439 beqz t0, secondary_hart_loop
445 j secondary_hart_loop