arch/riscv/cpu/ax25/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Andes Technology Corporation
   4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5  */
   6
   7 /* CPU specific code */
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <irq_func.h>
  11 #include <asm/cache.h>
  12 #include <asm/csr.h>
  13
  14 #define CSR_MCACHE_CTL  0x7ca
  15 #define CSR_MMISC_CTL   0x7d0
  16 #define CSR_MARCHID             0xf12
  17
  18 #define V5_MCACHE_CTL_IC_EN_OFFSET      0
  19 #define V5_MCACHE_CTL_DC_EN_OFFSET      1
  20 #define V5_MCACHE_CTL_DC_COHEN_OFFSET   19
  21 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET  20
  22
  23 #define V5_MCACHE_CTL_IC_EN             BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
  24 #define V5_MCACHE_CTL_DC_EN                             BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
  25 #define V5_MCACHE_CTL_DC_COHEN_EN       BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
  26 #define V5_MCACHE_CTL_DC_COHSTA_EN      BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
  27
  28
  29 /*
  30  * cleanup_before_linux() is called just before we call linux
  31  * it prepares the processor for linux
  32  *
  33  * we disable interrupt and caches.
  34  */
  35 int cleanup_before_linux(void)
  36 {
  37         disable_interrupts();
  38
  39         /* turn off I/D-cache */
  40         cache_flush();
  41         icache_disable();
  42         dcache_disable();
  43
  44         return 0;
  45 }
  46
  47 void harts_early_init(void)
  48 {
  49         if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
  50                 unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
  51
  52                 if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
  53                         mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
  54                 if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
  55                         mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
  56                 if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
  57                         mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
  58                 csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
  59
  60                 /*
  61                  * Check DC_COHEN_EN, if cannot write to mcache_ctl,
  62                  * we assume this bitmap not support L2 CM
  63                  */
  64                 mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
  65                 if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
  66                 /* Wait for DC_COHSTA bit be set */
  67                         while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
  68                                 mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
  69                 }
  70         }
  71 }