arch/riscv/cpu/ax25/cpu.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2017 Andes Technology Corporation
   4  * Rick Chen, Andes Technology Corporation <rick@andestech.com>
   5  */
   6
   7 /* CPU specific code */
   8 #include <common.h>
   9 #include <cpu_func.h>
  10 #include <irq_func.h>
  11 #include <asm/cache.h>
  12 #include <asm/csr.h>
  13
  14 #define CSR_MCACHE_CTL  0x7ca
  15 #define CSR_MMISC_CTL           0x7d0
  16 #define CSR_MARCHID                     0xf12
  17
  18 #define V5_MCACHE_CTL_IC_EN_OFFSET      0
  19 #define V5_MCACHE_CTL_DC_EN_OFFSET      1
  20 #define V5_MCACHE_CTL_CCTL_SUEN_OFFSET  8
  21 #define V5_MCACHE_CTL_DC_COHEN_OFFSET           19
  22 #define V5_MCACHE_CTL_DC_COHSTA_OFFSET  20
  23
  24 #define V5_MCACHE_CTL_IC_EN                                     BIT(V5_MCACHE_CTL_IC_EN_OFFSET)
  25 #define V5_MCACHE_CTL_DC_EN                                     BIT(V5_MCACHE_CTL_DC_EN_OFFSET)
  26 #define V5_MCACHE_CTL_CCTL_SUEN                 BIT(V5_MCACHE_CTL_CCTL_SUEN_OFFSET)
  27 #define V5_MCACHE_CTL_DC_COHEN_EN   BIT(V5_MCACHE_CTL_DC_COHEN_OFFSET)
  28 #define V5_MCACHE_CTL_DC_COHSTA_EN  BIT(V5_MCACHE_CTL_DC_COHSTA_OFFSET)
  29
  30
  31 /*
  32  * cleanup_before_linux() is called just before we call linux
  33  * it prepares the processor for linux
  34  *
  35  * we disable interrupt and caches.
  36  */
  37 int cleanup_before_linux(void)
  38 {
  39         disable_interrupts();
  40
  41         /* turn off I/D-cache */
  42         cache_flush();
  43         icache_disable();
  44         dcache_disable();
  45
  46         return 0;
  47 }
  48
  49 void harts_early_init(void)
  50 {
  51         if (CONFIG_IS_ENABLED(RISCV_MMODE)) {
  52                 unsigned long long mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
  53
  54                 if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN))
  55                         mcache_ctl_val |= V5_MCACHE_CTL_DC_COHEN_EN;
  56                 if (!(mcache_ctl_val & V5_MCACHE_CTL_IC_EN))
  57                         mcache_ctl_val |= V5_MCACHE_CTL_IC_EN;
  58                 if (!(mcache_ctl_val & V5_MCACHE_CTL_DC_EN))
  59                         mcache_ctl_val |= V5_MCACHE_CTL_DC_EN;
  60                 if (!(mcache_ctl_val & V5_MCACHE_CTL_CCTL_SUEN))
  61                         mcache_ctl_val |= V5_MCACHE_CTL_CCTL_SUEN;
  62                 csr_write(CSR_MCACHE_CTL, mcache_ctl_val);
  63
  64                 /*
  65                  * Check DC_COHEN_EN, if cannot write to mcache_ctl,
  66                  * we assume this bitmap not support L2 CM
  67                  */
  68                 mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
  69                 if ((mcache_ctl_val & V5_MCACHE_CTL_DC_COHEN_EN)) {
  70                 /* Wait for DC_COHSTA bit be set */
  71                         while (!(mcache_ctl_val & V5_MCACHE_CTL_DC_COHSTA_EN))
  72                                 mcache_ctl_val = csr_read(CSR_MCACHE_CTL);
  73                 }
  74         }
  75 }