arch/riscv/boot/dts/starfive/starfive_jh7110.dts

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /dts-v1/;
   3 #include "starfive_jh7110_clk.dtsi"
   4
   5 / {
   6         #address-cells = <2>;
   7         #size-cells = <2>;
   8         compatible = "sifive,freedom-u74-arty";
   9         model = "sifive,freedom-u74-arty";
  10
  11         chosen {
  12                         linux,initrd-start = <0x0 0x46100000>;
  13                         linux,initrd-end = <0x0 0x4c000000>;
  14                         stdout-path = "/soc/serial@10000000:115200";
  15                         #bootargs = "debug console=ttyS0 rootwait";
  16         };
  17         aliases {
  18                 spi0="/soc/spi@13010000";
  19                 gpio0="/soc/gpio@13040000";
  20                 ethernet0="/soc/gmac0@16030000";
  21                 mmc0="/soc/sdio0@16010000";
  22                 mmc1="/soc/sdio1@16020000";
  23         };
  24         cpus: cpus {
  25                 #address-cells = <1>;
  26                 #size-cells = <0>;
  27                 timebase-frequency = <2000000>;
  28                 compatible = "starfive,fu74-g000";
  29                 cpu@0 {
  30                         clock-frequency = <0>;
  31                         compatible = "starfive,rocket0", "riscv";
  32                         d-cache-block-size = <64>;
  33                         d-cache-sets = <64>;
  34                         d-cache-size = <32768>;
  35                         d-tlb-sets = <1>;
  36                         d-tlb-size = <40>;
  37                         device_type = "cpu";
  38                         i-cache-block-size = <64>;
  39                         i-cache-sets = <64>;
  40                         i-cache-size = <32768>;
  41                         i-tlb-sets = <1>;
  42                         i-tlb-size = <40>;
  43                         mmu-type = "riscv,sv39";
  44                         next-level-cache = <&cachectrl>;
  45                         reg = <0>;
  46                         riscv,isa = "rv64imac";
  47                         status = "disabled";
  48                         tlb-split;
  49                         cpu0intctrl: interrupt-controller {
  50                                 #interrupt-cells = <1>;
  51                                 compatible = "riscv,cpu-intc";
  52                                 interrupt-controller;
  53                         };
  54                 };
  55                 cpu@1 {
  56                         clock-frequency = <0>;
  57                         compatible = "starfive,rocket0", "riscv";
  58                         d-cache-block-size = <64>;
  59                         d-cache-sets = <64>;
  60                         d-cache-size = <32768>;
  61                         d-tlb-sets = <1>;
  62                         d-tlb-size = <40>;
  63                         device_type = "cpu";
  64                         i-cache-block-size = <64>;
  65                         i-cache-sets = <64>;
  66                         i-cache-size = <32768>;
  67                         i-tlb-sets = <1>;
  68                         i-tlb-size = <40>;
  69                         mmu-type = "riscv,sv39";
  70                         next-level-cache = <&cachectrl>;
  71                         reg = <1>;
  72                         riscv,isa = "rv64imafdc";
  73                         status = "okay";
  74                         tlb-split;
  75                         cpu1intctrl: interrupt-controller {
  76                                 #interrupt-cells = <1>;
  77                                 compatible = "riscv,cpu-intc";
  78                                 interrupt-controller;
  79                         };
  80                 };
  81                 cpu@2 {
  82                         clock-frequency = <0>;
  83                         compatible = "starfive,rocket0", "riscv";
  84                         d-cache-block-size = <64>;
  85                         d-cache-sets = <64>;
  86                         d-cache-size = <32768>;
  87                         d-tlb-sets = <1>;
  88                         d-tlb-size = <40>;
  89                         device_type = "cpu";
  90                         i-cache-block-size = <64>;
  91                         i-cache-sets = <64>;
  92                         i-cache-size = <32768>;
  93                         i-tlb-sets = <1>;
  94                         i-tlb-size = <40>;
  95                         mmu-type = "riscv,sv39";
  96                         next-level-cache = <&cachectrl>;
  97                         reg = <2>;
  98                         riscv,isa = "rv64imafdc";
  99                         status = "okay";
 100                         tlb-split;
 101                         cpu2intctrl: interrupt-controller {
 102                                 #interrupt-cells = <1>;
 103                                 compatible = "riscv,cpu-intc";
 104                                 interrupt-controller;
 105                         };
 106                 };
 107                 cpu@3 {
 108                         clock-frequency = <0>;
 109                         compatible = "starfive,rocket0", "riscv";
 110                         d-cache-block-size = <64>;
 111                         d-cache-sets = <64>;
 112                         d-cache-size = <32768>;
 113                         d-tlb-sets = <1>;
 114                         d-tlb-size = <40>;
 115                         device_type = "cpu";
 116                         i-cache-block-size = <64>;
 117                         i-cache-sets = <64>;
 118                         i-cache-size = <32768>;
 119                         i-tlb-sets = <1>;
 120                         i-tlb-size = <40>;
 121                         mmu-type = "riscv,sv39";
 122                         next-level-cache = <&cachectrl>;
 123                         reg = <3>;
 124                         riscv,isa = "rv64imafdc";
 125                         status = "okay";
 126                         tlb-split;
 127                         cpu3intctrl: interrupt-controller {
 128                                 #interrupt-cells = <1>;
 129                                 compatible = "riscv,cpu-intc";
 130                                 interrupt-controller;
 131                         };
 132                 };
 133                 cpu@4 {
 134                         clock-frequency = <0>;
 135                         compatible = "starfive,rocket0", "riscv";
 136                         d-cache-block-size = <64>;
 137                         d-cache-sets = <64>;
 138                         d-cache-size = <32768>;
 139                         d-tlb-sets = <1>;
 140                         d-tlb-size = <40>;
 141                         device_type = "cpu";
 142                         i-cache-block-size = <64>;
 143                         i-cache-sets = <64>;
 144                         i-cache-size = <32768>;
 145                         i-tlb-sets = <1>;
 146                         i-tlb-size = <40>;
 147                         mmu-type = "riscv,sv39";
 148                         next-level-cache = <&cachectrl>;
 149                         reg = <4>;
 150                         riscv,isa = "rv64imafdc";
 151                         status = "okay";
 152                         tlb-split;
 153                         cpu4intctrl: interrupt-controller {
 154                                 #interrupt-cells = <1>;
 155                                 compatible = "riscv,cpu-intc";
 156                                 interrupt-controller;
 157                         };
 158                 };
 159         };
 160         memory@80000000 {
 161                 device_type = "memory";
 162                 reg = <0x0 0x40000000 0x1 0x0>;
 163         };
 164         reserved-memory {
 165                 #address-cells = <2>;
 166                 #size-cells = <2>;
 167                 ranges;
 168
 169                 linux,cma {
 170                         compatible = "shared-dma-pool";
 171                         reusable;
 172                         size = <0x0 0x20000000>;
 173                         alignment = <0x0 0x1000>;
 174                         alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
 175                         linux,cma-default;
 176                 };
 177         };
 178
 179         soc: soc {
 180                 #address-cells = <2>;
 181                 #size-cells = <2>;
 182                 #clock-cells = <1>;
 183                 compatible = "starfive,freedom-u74-arty", "simple-bus", "arm,amba-bus";
 184                 ranges;
 185
 186                 cachectrl: cache-controller@2010000 {
 187                         cache-block-size = <64>;
 188                         cache-level = <2>;
 189                         cache-sets = <2048>;
 190                         cache-size = <2097152>;
 191                         cache-unified;
 192                         compatible = "sifive,fu540-c000-ccache", "starfive,ccache0", "cache";
 193                         interrupt-parent = <&plic>;
 194                         interrupts = <1 3 4 2>;
 195                         /*next-level-cache = <&L40 &L36>;*/
 196                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 197                         reg-names = "control", "sideband";
 198                 };
 199                 clint: clint@2000000 {
 200                         #interrupt-cells = <1>;
 201                         compatible = "riscv,clint0";
 202                         /*interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7 &cpu1intctrl 3 &cpu1intctrl 7 >;*/
 203                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 204                                                 &cpu1intctrl 3 &cpu1intctrl 7
 205                                                 &cpu2intctrl 3 &cpu2intctrl 7
 206                                                 &cpu3intctrl 3 &cpu3intctrl 7
 207                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 208                         reg = <0x0 0x2000000 0x0 0x10000>;
 209                         reg-names = "control";
 210                 };
 211                 plic: plic@c000000 {
 212                         #interrupt-cells = <1>;
 213                         compatible = "riscv,plic0";
 214                         interrupt-controller;
 215                         /*interrupts-extended = <&cpu0intctrl 11 &cpu0intctrl 9 &cpu1intctrl 11 &cpu1intctrl 9 >;*/
 216                         interrupts-extended = <&cpu0intctrl 11
 217                                                 &cpu1intctrl 11 &cpu1intctrl 9
 218                                                 &cpu2intctrl 11 &cpu2intctrl 9
 219                                                 &cpu3intctrl 11 &cpu3intctrl 9
 220                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 221                         reg = <0x0 0xc000000 0x0 0x4000000>;
 222                         reg-names = "control";
 223                         riscv,max-priority = <7>;
 224                         riscv,ndev = <136>;
 225                 };
 226
 227                 timer: timer@13050000 {
 228                         compatible = "starfive,si5-timers";
 229                         reg = <0x0 0x13050000 0x0 0x10000>;
 230                         interrupt-parent = <&plic>;
 231                         interrupts = <69>, <70>, <71> ,<72>;
 232                         interrupt-names = "timer0", "timer1", "timer2", "timer3";
 233                         clock-frequency = <2000000>;
 234                         status = "disabled";
 235                 };
 236
 237                 wdog: wdog@13070000 {
 238                         compatible = "starfive,dskit-wdt";
 239                         reg = <0x0 0x13070000 0x0 0x10000>;
 240                         interrupt-parent = <&plic>;
 241                         interrupts = <68>;
 242                         interrupt-names = "wdog";
 243                         clock-frequency = <2000000>;
 244                         timeout-sec = <15>;
 245                         status = "okay";
 246                 };
 247
 248                 rtc: rtc@17040000 {
 249                         compatible = "starfive,rtc_hms";
 250                         reg = <0x0 0x17040000 0x0 0x10000>;
 251                         interrupt-parent = <&plic>;
 252                         interrupts = <10>, <11>, <12>;
 253                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 254                         clocks = <&rtc_hmsclk>, <&oscclk>;
 255                         clock-names = "pclk", "cal_clk";
 256                         rtc,cal-clock-freq = <1000000>;
 257                         status = "okay";
 258                 };
 259
 260                 uart0: serial@10000000 {
 261                         compatible = "snps,dw-apb-uart";
 262                         interrupt-parent = <&plic>;
 263                         interrupts = <32>;
 264                         reg = <0x0 0x10000000 0x0 0x10000>;
 265                         reg-io-width = <4>;
 266                         reg-shift = <2>;
 267                         clocks = <&oscclk>, <&apb0clk>;
 268                         clock-names = "baudclk", "apb_pclk";
 269                         status = "okay";
 270                 };
 271                 uart1: serial@10010000 {
 272                         compatible = "snps,dw-apb-uart";
 273                         interrupt-parent = <&plic>;
 274                         interrupts = <33>;
 275                         reg = <0x0 0x10010000 0x0 0x10000>;
 276                         reg-io-width = <4>;
 277                         reg-shift = <2>;
 278                         clocks = <&oscclk>, <&apb0clk>;
 279                         clock-names = "baudclk", "apb_pclk";
 280                         status = "okay";
 281                 };
 282                 uart2: serial@10020000 {
 283                         compatible = "snps,dw-apb-uart";
 284                         interrupt-parent = <&plic>;
 285                         interrupts = <34>;
 286                         reg = <0x0 0x10020000 0x0 0x10000>;
 287                         reg-io-width = <4>;
 288                         reg-shift = <2>;
 289                         clocks = <&oscclk>, <&apb0clk>;
 290                         clock-names = "baudclk", "apb_pclk";
 291                         status = "okay";
 292                 };
 293                 uart3: serial@12000000 {
 294                         compatible = "snps,dw-apb-uart";
 295                         interrupt-parent = <&plic>;
 296                         interrupts = <45>;
 297                         reg = <0x0 0x12000000 0x0 0x10000>;
 298                         reg-io-width = <4>;
 299                         reg-shift = <2>;
 300                         clocks = <&uartclk>, <&apb0clk>;
 301                         clock-names = "baudclk", "apb_pclk";
 302                         status = "okay";
 303                 };
 304                 uart4: serial@12010000 {
 305                         compatible = "snps,dw-apb-uart";
 306                         interrupt-parent = <&plic>;
 307                         interrupts = <46>;
 308                         reg = <0x0 0x12010000 0x0 0x10000>;
 309                         reg-io-width = <4>;
 310                         reg-shift = <2>;
 311                         clocks = <&uartclk>, <&apb0clk>;
 312                         clock-names = "baudclk", "apb_pclk";
 313                         status = "okay";
 314                 };
 315                 uart5: serial@12020000 {
 316                         compatible = "snps,dw-apb-uart";
 317                         interrupt-parent = <&plic>;
 318                         interrupts = <47>;
 319                         reg = <0x0 0x12020000 0x0 0x10000>;
 320                         reg-io-width = <4>;
 321                         reg-shift = <2>;
 322                         clocks = <&uartclk>, <&apb0clk>;
 323                         clock-names = "baudclk", "apb_pclk";
 324                         status = "okay";
 325                 };
 326                 dma: dma-controller@16050000 {
 327                         compatible = "starfive,axi-dma";
 328                         reg = <0x0 0x16050000 0x0 0x10000>;
 329                         clocks = <&stg_axiahb_clk>, <&stg_apbclk>;
 330                         clock-names = "core-clk", "cfgr-clk";
 331                         interrupt-parent = <&plic>;
 332                         interrupts = <73>;
 333                         #dma-cells = <2>;
 334                         dma-channels = <4>;
 335                         snps,dma-masters = <1>;
 336                         snps,data-width = <3>;
 337                         snps,num-hs-if = <56>;
 338                         snps,block-size = <65536 65536 65536 65536>;
 339                         snps,priority = <0 1 2 3>;
 340                         snps,axi-max-burst-len = <16>;
 341                         status = "okay";
 342                 };
 343                 gpio: gpio@13040000 {
 344                         compatible = "starfive,gpio7110";
 345                         interrupt-parent = <&plic>;
 346                         interrupts = <91>;
 347                         reg = <0x0 0x13040000 0x0 0x10000>;
 348                         reg-names = "control";
 349                         interrupt-controller;
 350                         #gpio-cells = <2>;
 351                         ngpios = <64>;
 352                         status = "okay";
 353                 };
 354
 355                 trng: trng@1600C000 {
 356                         compatible = "starfive,trng";
 357                         reg = <0x0 0x1600C000 0x0 0x4000>;
 358                         interrupt-parent = <&plic>;
 359                         interrupts = <30>;
 360                         clocks = <&apb12clk>;
 361                         status = "okay";
 362                 };
 363
 364
 365                 i2c6: i2c@12060000 {
 366                         #address-cells = <1>;
 367                         #size-cells = <0>;
 368                         compatible = "snps,designware-i2c";
 369                         reg = <0x0 0x12060000 0x0 0x10000>;
 370                         interrupt-parent = <&plic>;
 371                         interrupts = <51>;
 372                         clock-frequency = <100000>;
 373                         i2c-sda-hold-time-ns = <300>;
 374                         i2c-sda-falling-time-ns = <3000>;
 375                         i2c-scl-falling-time-ns = <3000>;
 376                         auto_calc_scl_lhcnt;
 377
 378                         status = "okay";
 379
 380
 381
 382                         sc2235@30 {
 383                                 compatible = "sc2235";
 384                                 reg = <0x30>;
 385                                 clocks = <&clk_ext_camera>;
 386                                 clock-names = "xclk";
 387                                 powerdown-gpios = <&gpio 0 0>;
 388                                 reset-gpios = <&gpio 0 0>;
 389                                 sc2235-18-gpios = <&gpio 11 0>;
 390                                 sc2235-15-gpios = <&gpio 12 0>;
 391                                 sc2235-28-gpios = <&gpio 10 0>;
 392                                 sc2235-reset-gpios = <&gpio 16 0>;
 393                                 sc2235-pwdn-gpios = <&gpio 15 0>;
 394                                 sc2235-esync-gpios = <&gpio 17 0>;
 395                                 sc2235-oen-gpios = <&gpio 18 0>;
 396                                 //DOVDD-supply = <&v2v8>;
 397
 398                                 port {
 399                                         /* Parallel bus endpoint */
 400                                         sc2235_to_parallel: endpoint {
 401                                                 remote-endpoint = <&parallel_from_sc2235>;
 402                                                 bus-type = <5>;      /* Parallel */
 403                                                 bus-width = <8>;
 404                                                 data-shift = <2>; /* lines 13:6 are used */
 405                                                 hsync-active = <1>;
 406                                                 vsync-active = <1>;
 407                                                 pclk-sample = <1>;
 408                                         };
 409                                 };
 410                         };
 411                 };
 412                 i2c0: i2c@10030000 {
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         compatible = "snps,designware-i2c";
 416                         reg = <0x0 0x10030000 0x0 0x10000>;
 417                         interrupt-parent = <&plic>;
 418                         interrupts = <35>;
 419                         /*clocks = <&hfclk>; */
 420                         clock-frequency = <100000>;
 421                         i2c-sda-hold-time-ns = <300>;
 422                         i2c-sda-falling-time-ns = <3000>;
 423                         i2c-scl-falling-time-ns = <3000>;
 424                         auto_calc_scl_lhcnt;
 425                         status = "okay";
 426
 427                         ac108_a: ac108@3b {
 428                                 compatible = "x-power,ac108_0";
 429                                 reg = <0x3b>;
 430                                 #sound-dai-cells = <0>;
 431                                 data-protocol = <0>;
 432                         };
 433
 434                         wm8960: codec@1a {
 435                                 compatible = "wlf,wm8960";
 436                                 reg = <0x1a>;
 437                                 #sound-dai-cells = <0>;
 438
 439                                 wlf,shared-lrclk;
 440                         };
 441                 };
 442
 443                 /*emmc*/
 444                 sdio0:sdio0@16010000{
 445                         compatible = "snps,dw-mshc";
 446                         reg = <0x0 0x16010000 0x0 0x10000>;
 447                         interrupts = <74>;
 448                         interrupt-parent = <&plic>;
 449                         clocks = <&dwmmc_biuclk>,<&dwmmc_ciuclk>;
 450                         clock-names = "biu","ciu";
 451                         clock-frequency = <4000000>;
 452                         max-frequency = <1000000>;
 453                         fifo-depth = <32>;
 454                         card-detect-delay = <300>;
 455                         fifo-watermark-aligned;
 456                         data-addr = <0>;
 457                         bus-width = <8>;
 458                         cap-sd-highspeed;
 459                         /*broken-cd;*/
 460                         cap-sdio-irq;
 461                         cap-mmc-hw-reset;
 462                         non-removable;
 463                         enable-sdio-wakeup;
 464                         keep-power-in-suspend;
 465                         /*cap-power-off-card;*/
 466                         cap-mmc-highspeed;
 467                         /*fixed-emmc-driver-type;*/
 468                         post-power-on-delay-ms = <200>;
 469
 470                 };
 471                 /*SD*/
 472                 sdio1:sdio1@16020000{
 473                         compatible = "snps,dw-mshc";
 474                         reg = <0x0 0x16020000 0x0 0x10000>;
 475                         interrupts = <75>;
 476                         interrupt-parent = <&plic>;
 477                         clocks = <&dwmmc_biuclk>,<&dwmmc_ciuclk>;
 478                         clock-names = "biu","ciu";
 479                         clock-frequency = <4000000>;
 480                         max-frequency = <1000000>;
 481                         fifo-depth = <32>;
 482                         card-detect-delay = <300>;
 483                         fifo-watermark-aligned;
 484                         data-addr = <0>;
 485                         bus-width = <4>;
 486                         cap-sd-highspeed;
 487                         /*broken-cd;*/
 488                         cap-sdio-irq;
 489                         cap-mmc-hw-reset;
 490                         non-removable;
 491                         enable-sdio-wakeup;
 492                         keep-power-in-suspend;
 493                         /*cap-power-off-card;*/
 494                         cap-mmc-highspeed;
 495                         /*fixed-emmc-driver-type;*/
 496                         post-power-on-delay-ms = <200>;
 497                 };
 498                 vin_sysctl:vin_sysctl@19800000 {
 499                         compatible = "starfive,stf-vin";
 500                         reg = <0x0 0x19800000 0x0 0x10000>,//mipi-csi-0                         mipi0
 501                                 <0x0 0x19810000 0x0 0x10000>,//dom-isp-cfg                      vclk
 502                                 <0x0 0x19820000 0x0 0x10000>,//mipirx-dphyapb config    vrst
 503                                 <0x0 0x19830000 0x0 0x10000>,//reserved                                 mipi1
 504                                 <0x0 0x19840000 0x0 0x10000>,//dom-isp-syscon                   sctrl
 505                                 <0x0 0x19870000 0x0 0x30000>,//ispv1-mini                               isp0
 506                                 <0x0 0x198a0000 0x0 0x30000>,//reserved                                 isp1
 507                                 <0x0 0x11800000 0x0 0x10000>,//reserved                                 tclk
 508                                 <0x0 0x11840000 0x0 0x10000>,//reserved                                 trst
 509                                 <0x0 0x11858000 0x0 0x10000>,//reserved                                 iopad
 510                                 <0x0 0x17030000 0x0 0x10000>,                                            //pmu
 511                                 <0x0 0x13020000 0x0 0x10000>;  //sys_crg
 512                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad", "pmu", "syscrg";
 513                         interrupt-parent = <&plic>;
 514                         interrupts = <92 87 86>;
 515                         // memory-region = <&vin_reserved>;
 516
 517                         ports {
 518                                 port@3 {
 519                                         reg = <2>; //dvp sensor
 520
 521                                         /* Parallel bus endpoint */
 522                                         parallel_from_sc2235: endpoint {
 523                                                 remote-endpoint = <&sc2235_to_parallel>;
 524                                                 bus-type = <5>;      /* Parallel */
 525                                                 bus-width = <8>;
 526                                                 data-shift = <2>; /* lines 9:2 are used */
 527                                                 hsync-active = <1>;
 528                                                 vsync-active = <1>;
 529                                                 pclk-sample = <1>;
 530                                                 status = "okay";
 531                                         };
 532                                 };
 533                         };
 534                 };
 535                 jpu: jpu@11900000 {
 536                     compatible = "starfive,jpu";
 537                     reg = <0x0 0x13090000 0x0 0x300>;
 538                     interrupt-parent = <&plic>;
 539                     interrupts = <14>;
 540                     clocks = <&jpuclk>;
 541                     clock-names = "axi_clk", "core_clk", "apb_clk";
 542                     status = "okay";
 543                 };
 544
 545                 vpu_dec: vpu_dec@130A0000 {
 546                     compatible = "starfive,vdec";
 547                     reg = <0 0x130A0000 0 0x10000>;
 548                     interrupt-parent = <&plic>;
 549                     interrupts = <13>;
 550                     clocks = <&vdec_rootclk>;
 551                     clock-names = "axi_clk",
 552                                 "bpu_clk",
 553                                 "vce_clk",
 554                                 "apb_clk",
 555                                 "aximem_128b";
 556                     //starfive,vdec_noc_ctrl;
 557                     status = "okay";
 558                 };
 559                 vpu_enc:vpu_enc@130B0000 {
 560                         compatible = "cnm,cnm420l-vpu";
 561                         reg = <0x0 0x130B0000 0x0 0x10000>;
 562                         interrupt-parent = <&plic>;
 563                         interrupts = <15>;
 564                         clocks = <&venc_rootclk>;
 565                         clock-names = "vcodec";
 566                         reg-names = "control";
 567                 };
 568                 rst: reset-controller {
 569                         compatible = "starfive,jh7110-reset";
 570                         #reset-cells = <1>;
 571                         reset-controller;
 572                 };
 573
 574                 /*gmac device configuration*/
 575                 stmmac_axi_setup: stmmac-axi-config {
 576                         snps,wr_osr_lmt = <0xf>;
 577                         snps,rd_osr_lmt = <0xf>;
 578                         snps,blen = <256 128 64 32 0 0 0>;
 579                 };
 580                 gmac0:gmac0@16030000{
 581                         compatible = "snps,dwc-qos-ethernet-5.10a";
 582                         reg = <0x0 0x16030000 0x0 0x10000>;
 583                         interrupt-parent = <&plic>;
 584                         interrupts = <7>;
 585                         phy-reset-gpios = <&gpio 63 0>;
 586                         max-frame-size = <9000>;
 587                         phy-mode = "rgmii-id";
 588                         snps,multicast-filter-bins = <256>;
 589                         snps,perfect-filter-entries = <128>;
 590                         rx-fifo-depth = <262144>;
 591                         tx-fifo-depth = <131072>;
 592                         clock-names = "stmmaceth","phy_ref_clk", "apb_pclk","ptp_ref";
 593                         clocks = <&gmac_bus_clk>, <&gmac_rxtx_clk>, <&gmac_bus_clk>,<&gmac_ptp_clk>;
 594                         snps,fixed-burst;
 595                         snps,no-pbl-x8;
 596                         /*snps,force_sf_dma_mode;*/
 597                         snps,force_thresh_dma_mode;
 598                         snps,axi-config = <&stmmac_axi_setup>;
 599                         snps,tso;
 600                         snps,en-tx-lpi-clockgating;
 601                         snps,en-lpi;
 602                         snps,write-requests = <2>;
 603                         snps,read-requests = <16>;
 604                         snps,burst-map = <0x7>;
 605                         snps,txpbl = <16>;
 606                         snps,rxpbl = <16>;
 607                 };
 608
 609                 gpu:gpu@18000000{
 610                         compatible = "img-gpu";
 611                         interrupt-parent = <&plic>;
 612                         interrupts = <82>;
 613                         reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
 614                         clocks = <&gpu_core_clk>, <&gpu_sys_clk>;
 615                         clock-names = "gpu_core_clk","gpu_sys_clk";
 616                         current-clock = <8000000>;
 617                         status = "okay";
 618                 };
 619
 620                 ipmscan0: can@130d0000  {
 621                         compatible = "ipms,can";
 622                         reg = <0x0 0x130d0000 0x0 0x1000>;
 623                         interrupts = <112>;
 624                         interrupt-parent = <&plic>;
 625                         clocks = <&canclk>;
 626                         clock-names = "ipms_can_clk";
 627                 };
 628
 629                 ipmscan1: can@130c0000  {
 630                         compatible = "ipms,canfd";
 631                         reg = <0x0 0x130c0000 0x0 0x1000>;
 632                         interrupts = <113>;
 633                         interrupt-parent = <&plic>;
 634                         clocks = <&canclk>;
 635                         clock-names = "ipms_can_clk";
 636                 };
 637
 638                 tdm: tdm@10090000  {
 639                         compatible = "starfive,tdm";
 640                         reg = <0x0 0x10090000 0x0 0x1000>;
 641                         reg-names = "tdm";
 642                         clocks = <&audioclk>;
 643                         clock-names = "audioclk";
 644                         dmas = <&dma 20 1>, <&dma 21 1>;
 645                         dma-names = "rx","tx";
 646                         #sound-dai-cells = <0>;
 647                 };
 648
 649                 spdif0: spdif0@100a0000 {
 650                         compatible = "starfive,sf-spdif";
 651                         reg = <0x0 0x100a0000 0x0 0x1000>;
 652                         interrupt-parent = <&plic>;
 653                         interrupts = <84>;
 654                         interrupt-names = "tx";
 655                         clocks = <&audioclk>;
 656                         clock-names = "audioclk";
 657                         #sound-dai-cells = <0>;
 658                 };
 659
 660                 pwmdac: pwmdac@100b0000 {
 661                         compatible = "sf,pwmdac";
 662                         reg = <0x0 0x100b0000 0x0 0x1000>;
 663                         clocks = <&apb0clk>;
 664                         dmas = <&dma 22 1>;
 665                         dma-names = "tx";
 666                         #sound-dai-cells = <0>;
 667                 };
 668
 669                 i2stx: i2stx@100c0000  {
 670                         compatible = "snps,designware-i2stx";
 671                         reg = <0x0 0x100c0000 0x0 0x1000>;
 672                         interrupt-names = "tx";
 673                         clocks = <&apb0clk>;
 674                         clock-names = "i2sclk";
 675                         #sound-dai-cells = <0>;
 676                         dmas = <&dma 28>;
 677                         dma-names = "rx";
 678                 };
 679
 680                 pdm: pdm@100d0000 {
 681                         compatible = "starfive,sf-pdm";
 682                         reg = <0x0 0x100d0000 0x0 0x1000>;
 683                         reg-names = "pdm";
 684                         clocks = <&audioclk>;
 685                         clock-names = "audioclk";
 686                         #sound-dai-cells = <0>;
 687                 };
 688
 689                 i2srx_3ch: i2srx-3ch@100e0000 {
 690                         compatible = "snps,designware-i2srx";
 691                         reg = <0x0 0x100e0000 0x0 0x1000>;
 692                         interrupt-parent = <&plic>;
 693                         /*interrupts = <42>, <43>, <44>;*/
 694                         /*interrupt-names = "rx-ch0","rx-ch1","rx-ch2";*/
 695                         interrupts = <42>;
 696                         interrupt-names = "rx";
 697                         clocks = <&apb0clk>;
 698                         clock-names = "i2sclk";
 699                         #sound-dai-cells = <0>;
 700                 };
 701
 702                 i2stx_4ch0: i2stx-4ch0@120b0000 {
 703                         compatible = "snps,designware-i2stx-4ch0";
 704                         reg = <0x0 0x120b0000 0x0 0x1000>;
 705                         interrupt-parent = <&plic>;
 706                         interrupts = <58>;
 707                         interrupt-names = "tx";
 708                         clocks = <&apb0clk>;
 709                         clock-names = "i2sclk";
 710                         #sound-dai-cells = <0>;
 711                 };
 712
 713                 i2stx_4ch1: i2sdac1@120c0000 {
 714                         compatible = "snps,designware-i2stx-4ch1";
 715                         reg = <0x0 0x120c0000 0x0 0x1000>;
 716                         interrupt-parent = <&plic>;
 717                         interrupts = <59>;
 718                         interrupt-names = "tx";
 719                         clocks = <&apb0clk>;
 720                         clock-names = "i2sclk";
 721                         #sound-dai-cells = <0>;
 722                 };
 723
 724                 ptc: pwm@120d0000 {
 725                         compatible = "starfive,pwm0";
 726                         reg = <0x0 0x120d0000 0x0 0x10000>;
 727                         reg-names = "control";
 728                         sifive,approx-period = <1000000>;
 729                         clocks = <&pwmclk>;
 730                         #pwm-cells=<3>;
 731                         sifive,npwm = <8>;
 732                 };
 733
 734                 ac108_mclk: ac108_mclk {
 735                         compatible = "fixed-clock";
 736                         #clock-cells = <0>;
 737                         clock-frequency = <24576000>;
 738                 };
 739
 740                 wm8960_mclk: wm8960_mclk {
 741                         compatible = "fixed-clock";
 742                         #clock-cells = <0>;
 743                         clock-frequency = <4000000>;
 744                 };
 745
 746                 spdif_transmitter: spdif_transmitter {
 747                         compatible = "linux,spdif-dit";
 748                         #sound-dai-cells = <0>;
 749                 };
 750
 751                 spdif_receiver: spdif_receiver {
 752                         compatible = "linux,spdif-dir";
 753                         #sound-dai-cells = <0>;
 754                 };
 755
 756                 pwmdac_codec: pwmdac-transmitter {
 757                         compatible = "linux,pwmdac-dit";
 758                         #sound-dai-cells = <0>;
 759                 };
 760
 761                 dmic_codec: dmic_codec {
 762                         compatible = "dmic-codec";
 763                         #sound-dai-cells = <0>;
 764                 };
 765
 766                 spi0:spi0@10060000 {
 767                         compatible = "arm,pl022", "arm,primecell";
 768                         reg = <0x0 0x10060000 0x0 0x10000>;
 769                         clocks = <&ahb1clk>;
 770                         clock-names = "apb_pclk";
 771                         dmas = <&dma 14 1>, <&dma 15 1>;
 772                         dma-names = "rx","tx";
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         arm,primecell-periphid = <0x00041022>;
 776                         interrupt-parent = <&plic>;
 777                         interrupts = <38>;
 778                         num-cs = <1>;
 779                         spi_dev0: spi@0 {
 780                                 compatible = "rohm,dh2228fv";
 781                                 pl022,com-mode = <1>;
 782                                 spi-max-frequency = <10000000>;
 783                                 reg = <0>;
 784                                 status = "okay";
 785                         };
 786                 };
 787
 788                 pcie0:pcie0@2B000000 {
 789                         compatible = "plda,pci-xpressrich3-axi";
 790                         reg = <0x0 0x2B000000 0x0 0x1000000
 791                                         0x9 0x40000000 0x0 0x10000000>;
 792                         reg-names = "reg", "config";
 793                         device_type = "pci";
 794                         bus-range = <0x0 0xff>;
 795                         #address-cells = <3>;
 796                         #size-cells = <2>;
 797                         #interrupt-cells = <1>;
 798                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
 799                         msi-parent = <&plic>;
 800                         interrupts = <56>;
 801                         interrupt-controller;
 802                         interrupt-names = "msi";
 803                         interrupt-parent = <&plic>;
 804                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 805                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
 806                                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
 807                                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
 808                                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
 809                         status = "disabled";
 810                 };
 811         };
 812 };
 813
 814 #include "starfive_jh7110_audio.dtsi"