1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110-clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
13 #include <dt-bindings/power/jh7110-power.h>
16 compatible = "starfive,jh7110";
20 cluster0_opp: opp-table-0 {
21 compatible = "operating-points-v2";
24 opp-hz = /bits/ 64 <375000000>;
25 opp-microvolt = <880000>;
28 opp-hz = /bits/ 64 <500000000>;
29 opp-microvolt = <880000>;
32 opp-hz = /bits/ 64 <750000000>;
33 opp-microvolt = <880000>;
36 opp-hz = /bits/ 64 <1500000000>;
37 opp-microvolt = <1000000>;
46 compatible = "sifive,u74-mc", "riscv";
48 d-cache-block-size = <64>;
50 d-cache-size = <8192>;
54 i-cache-block-size = <64>;
56 i-cache-size = <16384>;
59 mmu-type = "riscv,sv39";
60 cpu-idle-states = <&CPU_NONRET_0_0>;
61 next-level-cache = <&cachectrl>;
62 riscv,isa = "rv64imac";
66 cpu0intctrl: interrupt-controller {
67 #interrupt-cells = <1>;
68 compatible = "riscv,cpu-intc";
74 compatible = "sifive,u74-mc", "riscv";
76 d-cache-block-size = <64>;
78 d-cache-size = <32768>;
82 i-cache-block-size = <64>;
84 i-cache-size = <32768>;
87 mmu-type = "riscv,sv39";
88 cpu-idle-states = <&CPU_NONRET_0_0>;
89 next-level-cache = <&cachectrl>;
90 riscv,isa = "rv64imafdc";
93 operating-points-v2 = <&cluster0_opp>;
95 cpu1intctrl: interrupt-controller {
96 #interrupt-cells = <1>;
97 compatible = "riscv,cpu-intc";
103 compatible = "sifive,u74-mc", "riscv";
105 d-cache-block-size = <64>;
107 d-cache-size = <32768>;
111 i-cache-block-size = <64>;
113 i-cache-size = <32768>;
116 mmu-type = "riscv,sv39";
117 cpu-idle-states = <&CPU_NONRET_0_0>;
118 next-level-cache = <&cachectrl>;
119 riscv,isa = "rv64imafdc";
122 operating-points-v2 = <&cluster0_opp>;
124 cpu2intctrl: interrupt-controller {
125 #interrupt-cells = <1>;
126 compatible = "riscv,cpu-intc";
127 interrupt-controller;
132 compatible = "sifive,u74-mc", "riscv";
134 d-cache-block-size = <64>;
136 d-cache-size = <32768>;
140 i-cache-block-size = <64>;
142 i-cache-size = <32768>;
145 mmu-type = "riscv,sv39";
146 cpu-idle-states = <&CPU_NONRET_0_0>;
147 next-level-cache = <&cachectrl>;
148 riscv,isa = "rv64imafdc";
151 operating-points-v2 = <&cluster0_opp>;
153 cpu3intctrl: interrupt-controller {
154 #interrupt-cells = <1>;
155 compatible = "riscv,cpu-intc";
156 interrupt-controller;
161 compatible = "sifive,u74-mc", "riscv";
163 d-cache-block-size = <64>;
165 d-cache-size = <32768>;
169 i-cache-block-size = <64>;
171 i-cache-size = <32768>;
174 mmu-type = "riscv,sv39";
175 cpu-idle-states = <&CPU_NONRET_0_0>;
176 next-level-cache = <&cachectrl>;
177 riscv,isa = "rv64imafdc";
180 operating-points-v2 = <&cluster0_opp>;
182 cpu4intctrl: interrupt-controller {
183 #interrupt-cells = <1>;
184 compatible = "riscv,cpu-intc";
185 interrupt-controller;
191 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
192 compatible = "riscv,idle-state";
193 riscv,sbi-suspend-param = <0x80000000>;
194 entry-latency-us = <600>;
195 exit-latency-us = <1100>;
196 min-residency-us = <2700>;
197 wakeup-latency-us = <1500>;
202 compatible = "simple-bus";
203 interrupt-parent = <&plic>;
204 #address-cells = <2>;
209 cachectrl: cache-controller@2010000 {
210 compatible = "sifive,fu740-c000-ccache", "cache";
211 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
212 reg-names = "control", "sideband";
213 interrupts = <1 3 4 2>;
214 cache-block-size = <64>;
217 cache-size = <2097152>;
221 aon_syscon: aon_syscon@17010000 {
222 compatible = "syscon";
223 reg = <0x0 0x17010000 0x0 0x1000>;
226 stg_syscon: stg_syscon@10240000 {
227 compatible = "syscon";
228 reg = <0x0 0x10240000 0x0 0x1000>;
231 sys_syscon: sys_syscon@13030000 {
232 compatible = "syscon";
233 reg = <0x0 0x13030000 0x0 0x1000>;
236 clint: clint@2000000 {
237 compatible = "riscv,clint0";
238 reg = <0x0 0x2000000 0x0 0x10000>;
239 reg-names = "control";
240 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
241 &cpu1intctrl 3 &cpu1intctrl 7
242 &cpu2intctrl 3 &cpu2intctrl 7
243 &cpu3intctrl 3 &cpu3intctrl 7
244 &cpu4intctrl 3 &cpu4intctrl 7>;
245 #interrupt-cells = <1>;
249 compatible = "riscv,plic0";
250 reg = <0x0 0xc000000 0x0 0x4000000>;
251 reg-names = "control";
252 interrupts-extended = <&cpu0intctrl 11
253 &cpu1intctrl 11 &cpu1intctrl 9
254 &cpu2intctrl 11 &cpu2intctrl 9
255 &cpu3intctrl 11 &cpu3intctrl 9
256 &cpu4intctrl 11 &cpu4intctrl 9>;
257 interrupt-controller;
258 #interrupt-cells = <1>;
259 riscv,max-priority = <7>;
263 clkgen: clock-controller {
264 compatible = "starfive,jh7110-clkgen";
265 reg = <0x0 0x13020000 0x0 0x10000>,
266 <0x0 0x10230000 0x0 0x10000>,
267 <0x0 0x17000000 0x0 0x10000>;
268 reg-names = "sys", "stg", "aon";
269 clocks = <&osc>, <&gmac1_rmii_refin>,
271 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
272 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
273 <&tdm_ext>, <&mclk_ext>,
274 <&jtag_tck_inner>, <&bist_apb>,
276 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
277 clock-names = "osc", "gmac1_rmii_refin",
279 "i2stx_bclk_ext", "i2stx_lrck_ext",
280 "i2srx_bclk_ext", "i2srx_lrck_ext",
281 "tdm_ext", "mclk_ext",
282 "jtag_tck_inner", "bist_apb",
284 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
286 starfive,sys-syscon = <&sys_syscon 0x18 0x1c
287 0x20 0x24 0x28 0x2c 0x30 0x34>;
291 clkvout: clock-controller@295C0000 {
292 compatible = "starfive,jh7110-clk-vout";
293 reg = <0x0 0x295C0000 0x0 0x10000>;
295 clocks = <&hdmitx0_pixelclk>,
296 <&mipitx_dphy_rxesc>,
297 <&mipitx_dphy_txbytehs>,
298 <&clkgen JH7110_VOUT_SRC>,
299 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
300 clock-names = "hdmitx0_pixelclk",
302 "mipitx_dphy_txbytehs",
305 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
306 reset-names = "vout_src";
308 power-domains = <&pwrc JH7110_PD_VOUT>;
312 clkisp: clock-controller@19810000 {
313 compatible = "starfive,jh7110-clk-isp";
314 reg = <0x0 0x19810000 0x0 0x10000>;
317 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
318 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
319 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
320 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
321 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
322 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
323 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
324 "u0_sft7110_noc_bus_clk_isp_axi";
325 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
326 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
327 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
328 reset-names = "rst_isp_top_n", "rst_isp_top_axi",
330 power-domains = <&pwrc JH7110_PD_ISP>;
335 compatible = "cdns,qspi-nor";
336 #address-cells = <1>;
338 reg = <0x0 0x13010000 0x0 0x10000
339 0x0 0x21000000 0x0 0x400000>;
340 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
341 clock-names = "clk_ref";
342 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
343 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
344 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
345 resets-names = "rst_apb", "rst_ahb", "rst_ref";
346 cdns,fifo-depth = <256>;
347 cdns,fifo-width = <4>;
348 spi-max-frequency = <250000000>;
350 nor_flash: nor-flash@0 {
351 compatible = "jedec,spi-nor";
353 spi-max-frequency = <100000000>;
362 compatible = "starfive,jh7110-otp";
363 reg = <0x0 0x17050000 0x0 0x10000>;
364 clock-frequency = <4000000>;
365 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
370 compatible = "starfive,jh7110-cdns3";
371 reg = <0x0 0x10210000 0x0 0x1000>,
372 <0x0 0x10200000 0x0 0x1000>;
373 clocks = <&clkgen JH7110_USB_125M>,
374 <&clkgen JH7110_USB0_CLK_APP_125>,
375 <&clkgen JH7110_USB0_CLK_LPM>,
376 <&clkgen JH7110_USB0_CLK_STB>,
377 <&clkgen JH7110_USB0_CLK_USB_APB>,
378 <&clkgen JH7110_USB0_CLK_AXI>,
379 <&clkgen JH7110_USB0_CLK_UTMI_APB>,
380 <&clkgen JH7110_PCIE0_CLK_APB>;
381 clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
382 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
383 <&rstgen RSTN_U0_CDN_USB_APB>,
384 <&rstgen RSTN_U0_CDN_USB_AXI>,
385 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
386 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
387 reset-names = "pwrup","apb","axi","utmi", "phy";
388 starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
389 starfive,sys-syscon = <&sys_syscon 0x18>;
391 #address-cells = <2>;
393 #interrupt-cells = <1>;
395 usbdrd_cdns3: usb@10100000 {
396 compatible = "cdns,usb3";
397 reg = <0x0 0x10100000 0x0 0x10000>,
398 <0x0 0x10110000 0x0 0x10000>,
399 <0x0 0x10120000 0x0 0x10000>;
400 reg-names = "otg", "xhci", "dev";
401 interrupts = <100>, <108>, <110>;
402 interrupt-names = "host", "peripheral", "otg";
403 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
404 maximum-speed = "super-speed";
408 timer: timer@13050000 {
409 compatible = "starfive,jh7110-timers";
410 reg = <0x0 0x13050000 0x0 0x10000>;
411 interrupts = <69>, <70>, <71> ,<72>;
412 interrupt-names = "timer0", "timer1",
414 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
415 <&clkgen JH7110_TIMER_CLK_TIMER1>,
416 <&clkgen JH7110_TIMER_CLK_TIMER2>,
417 <&clkgen JH7110_TIMER_CLK_TIMER3>,
418 <&clkgen JH7110_TIMER_CLK_APB>;
419 clock-names = "timer0", "timer1",
420 "timer2", "timer3", "apb_clk";
421 resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
422 <&rstgen RSTN_U0_TIMER_TIMER1>,
423 <&rstgen RSTN_U0_TIMER_TIMER2>,
424 <&rstgen RSTN_U0_TIMER_TIMER3>,
425 <&rstgen RSTN_U0_TIMER_APB>;
426 reset-names = "timer0", "timer1",
427 "timer2", "timer3", "apb_rst";
428 clock-frequency = <24000000>;
432 wdog: wdog@13070000 {
433 compatible = "starfive,jh7110-wdt";
434 reg = <0x0 0x13070000 0x0 0x10000>;
436 interrupt-names = "wdog";
437 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
438 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
439 clock-names = "core_clk", "apb_clk";
440 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
441 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
442 reset-names = "rst_apb", "rst_core";
448 compatible = "starfive,jh7110-rtc";
449 reg = <0x0 0x17040000 0x0 0x10000>;
450 interrupts = <10>, <11>, <12>;
451 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
452 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
453 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
454 clock-names = "pclk", "cal_clk";
455 resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
456 <&rstgen RSTN_U0_RTC_HMS_APB>,
457 <&rstgen RSTN_U0_RTC_HMS_CAL>;
458 reset-names = "rst_osc", "rst_apb", "rst_cal";
459 rtc,cal-clock-freq = <1000000>;
463 pwrc: power-controller@17030000 {
464 compatible = "starfive,jh7110-pmu";
465 reg = <0x0 0x17030000 0x0 0x10000>;
467 #power-domain-cells = <1>;
471 uart0: serial@10000000 {
472 compatible = "snps,dw-apb-uart";
473 reg = <0x0 0x10000000 0x0 0x10000>;
476 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
477 <&clkgen JH7110_UART0_CLK_APB>;
478 clock-names = "baudclk", "apb_pclk";
479 resets = <&rstgen RSTN_U0_DW_UART_APB>,
480 <&rstgen RSTN_U0_DW_UART_CORE>;
485 uart1: serial@10010000 {
486 compatible = "snps,dw-apb-uart";
487 reg = <0x0 0x10010000 0x0 0x10000>;
490 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
491 <&clkgen JH7110_UART1_CLK_APB>;
492 clock-names = "baudclk", "apb_pclk";
493 resets = <&rstgen RSTN_U1_DW_UART_APB>,
494 <&rstgen RSTN_U1_DW_UART_CORE>;
499 uart2: serial@10020000 {
500 compatible = "snps,dw-apb-uart";
501 reg = <0x0 0x10020000 0x0 0x10000>;
504 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
505 <&clkgen JH7110_UART2_CLK_APB>;
506 clock-names = "baudclk", "apb_pclk";
507 resets = <&rstgen RSTN_U2_DW_UART_APB>,
508 <&rstgen RSTN_U2_DW_UART_CORE>;
513 uart3: serial@12000000 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x0 0x12000000 0x0 0x10000>;
518 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
519 <&clkgen JH7110_UART3_CLK_APB>;
520 clock-names = "baudclk", "apb_pclk";
521 resets = <&rstgen RSTN_U3_DW_UART_APB>,
522 <&rstgen RSTN_U3_DW_UART_CORE>;
527 uart4: serial@12010000 {
528 compatible = "snps,dw-apb-uart";
529 reg = <0x0 0x12010000 0x0 0x10000>;
532 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
533 <&clkgen JH7110_UART4_CLK_APB>;
534 clock-names = "baudclk", "apb_pclk";
535 resets = <&rstgen RSTN_U4_DW_UART_APB>,
536 <&rstgen RSTN_U4_DW_UART_CORE>;
541 uart5: serial@12020000 {
542 compatible = "snps,dw-apb-uart";
543 reg = <0x0 0x12020000 0x0 0x10000>;
546 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
547 <&clkgen JH7110_UART5_CLK_APB>;
548 clock-names = "baudclk", "apb_pclk";
549 resets = <&rstgen RSTN_U5_DW_UART_APB>,
550 <&rstgen RSTN_U5_DW_UART_CORE>;
555 dma: dma-controller@16050000 {
556 compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
557 reg = <0x0 0x16050000 0x0 0x10000>;
558 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
559 <&clkgen JH7110_DMA1P_CLK_AHB>;
560 clock-names = "core-clk", "cfgr-clk";
561 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
562 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
563 reset-names = "rst_axi", "rst_ahb";
567 snps,dma-masters = <1>;
568 snps,data-width = <3>;
569 snps,num-hs-if = <56>;
570 snps,block-size = <65536 65536 65536 65536>;
571 snps,priority = <0 1 2 3>;
572 snps,axi-max-burst-len = <16>;
576 gpio: gpio@13040000 {
577 compatible = "starfive,jh7110-sys-pinctrl";
578 reg = <0x0 0x13040000 0x0 0x10000>;
579 reg-names = "control";
580 clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
581 resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
583 interrupt-controller;
589 gpioa: gpio@17020000 {
590 compatible = "starfive,jh7110-aon-pinctrl";
591 reg = <0x0 0x17020000 0x0 0x10000>;
592 reg-names = "control";
593 resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
595 interrupt-controller;
601 sfctemp: tmon@120e0000 {
602 compatible = "starfive,jh7110-temp";
603 reg = <0x0 0x120e0000 0x0 0x10000>;
605 clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
606 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
607 clock-names = "sense", "bus";
608 resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
609 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
610 reset-names = "sense", "bus";
611 #thermal-sensor-cells = <0>;
617 polling-delay-passive = <250>;
618 polling-delay = <15000>;
620 thermal-sensors = <&sfctemp>;
626 cpu_alert0: cpu_alert0 {
628 temperature = <75000>;
635 temperature = <90000>;
643 trng: trng@1600C000 {
644 compatible = "starfive,jh7110-trng";
645 reg = <0x0 0x1600C000 0x0 0x4000>;
646 clocks = <&clkgen JH7110_SEC_HCLK>,
647 <&clkgen JH7110_SEC_MISCAHB_CLK>;
648 clock-names = "hclk", "miscahb_clk";
649 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
654 sec_dma: sec_dma@16008000 {
655 compatible = "arm,pl080", "arm,primecell";
656 arm,primecell-periphid = <0x00041080>;
657 reg = <0x0 0x16008000 0x0 0x4000>;
658 reg-names = "sec_dma";
660 clocks = <&clkgen JH7110_SEC_HCLK>,
661 <&clkgen JH7110_SEC_MISCAHB_CLK>;
662 clock-names = "sec_hclk","apb_pclk";
663 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
664 reset-names = "sec_hre";
665 lli-bus-interface-ahb1;
666 mem-bus-interface-ahb1;
667 memcpy-burst-size = <256>;
668 memcpy-bus-width = <32>;
673 crypto: crypto@16000000 {
674 compatible = "starfive,jh7110-sec";
675 reg = <0x0 0x16000000 0x0 0x4000>,
676 <0x0 0x16008000 0x0 0x4000>;
677 reg-names = "secreg","secdma";
678 interrupts = <28>, <29>;
679 interrupt-names = "secirq", "dmairq";
680 clocks = <&clkgen JH7110_SEC_HCLK>,
681 <&clkgen JH7110_SEC_MISCAHB_CLK>;
682 clock-names = "sec_hclk","sec_ahb";
683 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
684 reset-names = "sec_hre";
685 enable-side-channel-mitigation = "true";
687 dmas = <&sec_dma 1 2>,
689 dma-names = "sec_m","sec_p";
694 compatible = "snps,designware-i2c";
695 reg = <0x0 0x10030000 0x0 0x10000>;
696 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
697 <&clkgen JH7110_I2C0_CLK_APB>;
698 clock-names = "ref", "pclk";
699 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
701 #address-cells = <1>;
707 compatible = "snps,designware-i2c";
708 reg = <0x0 0x10040000 0x0 0x10000>;
709 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
710 <&clkgen JH7110_I2C1_CLK_APB>;
711 clock-names = "ref", "pclk";
712 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
714 #address-cells = <1>;
720 compatible = "snps,designware-i2c";
721 reg = <0x0 0x10050000 0x0 0x10000>;
722 clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
723 <&clkgen JH7110_I2C2_CLK_APB>;
724 clock-names = "ref", "pclk";
725 resets = <&rstgen RSTN_U2_DW_I2C_APB>;
727 #address-cells = <1>;
733 compatible = "snps,designware-i2c";
734 reg = <0x0 0x12030000 0x0 0x10000>;
735 clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
736 <&clkgen JH7110_I2C3_CLK_APB>;
737 clock-names = "ref", "pclk";
738 resets = <&rstgen RSTN_U3_DW_I2C_APB>;
740 #address-cells = <1>;
746 compatible = "snps,designware-i2c";
747 reg = <0x0 0x12040000 0x0 0x10000>;
748 clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
749 <&clkgen JH7110_I2C4_CLK_APB>;
750 clock-names = "ref", "pclk";
751 resets = <&rstgen RSTN_U4_DW_I2C_APB>;
753 #address-cells = <1>;
759 compatible = "snps,designware-i2c";
760 reg = <0x0 0x12050000 0x0 0x10000>;
761 clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
762 <&clkgen JH7110_I2C5_CLK_APB>;
763 clock-names = "ref", "pclk";
764 resets = <&rstgen RSTN_U5_DW_I2C_APB>;
766 #address-cells = <1>;
772 compatible = "snps,designware-i2c";
773 reg = <0x0 0x12060000 0x0 0x10000>;
774 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
775 <&clkgen JH7110_I2C6_CLK_APB>;
776 clock-names = "ref", "pclk";
777 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
779 #address-cells = <1>;
784 /* unremovable emmc as mmcblk0 */
785 sdio0: sdio0@16010000 {
786 compatible = "starfive,jh7110-sdio";
787 reg = <0x0 0x16010000 0x0 0x10000>;
788 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
789 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
790 clock-names = "biu","ciu";
791 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
792 reset-names = "reset";
795 fifo-watermark-aligned;
797 starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
801 sdio1: sdio1@16020000 {
802 compatible = "starfive,jh7110-sdio";
803 reg = <0x0 0x16020000 0x0 0x10000>;
804 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
805 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
806 clock-names = "biu","ciu";
807 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
808 reset-names = "reset";
811 fifo-watermark-aligned;
816 vin_sysctl: vin_sysctl@19800000 {
817 compatible = "starfive,jh7110-vin";
818 reg = <0x0 0x19800000 0x0 0x10000>,
819 <0x0 0x19810000 0x0 0x10000>,
820 <0x0 0x19820000 0x0 0x10000>,
821 <0x0 0x19840000 0x0 0x10000>,
822 <0x0 0x19870000 0x0 0x30000>,
823 <0x0 0x11840000 0x0 0x10000>,
824 <0x0 0x17030000 0x0 0x10000>,
825 <0x0 0x13020000 0x0 0x10000>;
826 reg-names = "csi2rx", "vclk", "vrst", "sctrl",
827 "isp", "trst", "pmu", "syscrg";
828 clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
829 <&clkisp JH7110_U0_VIN_PCLK>,
830 <&clkisp JH7110_U0_VIN_SYS_CLK>,
831 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
832 <&clkisp JH7110_DVP_INV>,
833 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
834 <&clkisp JH7110_MIPI_RX0_PXL>,
835 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
836 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
837 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
838 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
839 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
840 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
841 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
842 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
843 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
844 clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
845 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
846 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
847 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
848 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
849 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
850 "clk_ispcore_2x", "clk_isp_axi";
851 resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
852 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
853 <&rstgen RSTN_U0_VIN_N_PCLK>,
854 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
855 <&rstgen RSTN_U0_VIN_P_AXIRD>,
856 <&rstgen RSTN_U0_VIN_P_AXIWR>,
857 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
858 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
859 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
860 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
861 <&rstgen RSTN_U0_M31DPHY_HW>,
862 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
863 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
864 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
865 reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
866 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
867 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
868 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
869 "rst_isp_top_n", "rst_isp_top_axi";
870 starfive,aon-syscon = <&aon_syscon 0x00>;
871 power-domains = <&pwrc JH7110_PD_ISP>;
872 /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
873 interrupts = <92 87 88 89 90>;
878 compatible = "starfive,jpu";
879 reg = <0x0 0x13090000 0x0 0x300>;
881 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
882 <&clkgen JH7110_CODAJ12_CLK_CORE>,
883 <&clkgen JH7110_CODAJ12_CLK_APB>,
884 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
885 clock-names = "axi_clk", "core_clk",
886 "apb_clk", "noc_bus";
887 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
888 <&rstgen RSTN_U0_CODAJ12_CORE>,
889 <&rstgen RSTN_U0_CODAJ12_APB>;
890 reset-names = "rst_axi", "rst_core", "rst_apb";
891 power-domains = <&pwrc JH7110_PD_VDEC>;
895 vpu_dec: vpu_dec@130A0000 {
896 compatible = "starfive,vdec";
897 reg = <0x0 0x130A0000 0x0 0x10000>;
899 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
900 <&clkgen JH7110_WAVE511_CLK_BPU>,
901 <&clkgen JH7110_WAVE511_CLK_VCE>,
902 <&clkgen JH7110_WAVE511_CLK_APB>,
903 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
904 clock-names = "axi_clk", "bpu_clk", "vce_clk",
905 "apb_clk", "noc_bus";
906 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
907 <&rstgen RSTN_U0_WAVE511_BPU>,
908 <&rstgen RSTN_U0_WAVE511_VCE>,
909 <&rstgen RSTN_U0_WAVE511_APB>,
910 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
911 reset-names = "rst_axi", "rst_bpu", "rst_vce",
912 "rst_apb", "rst_sram";
913 starfive,vdec_noc_ctrl;
914 power-domains = <&pwrc JH7110_PD_VDEC>;
918 vpu_enc: vpu_enc@130B0000 {
919 compatible = "starfive,venc";
920 reg = <0x0 0x130B0000 0x0 0x10000>;
922 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
923 <&clkgen JH7110_WAVE420L_CLK_BPU>,
924 <&clkgen JH7110_WAVE420L_CLK_VCE>,
925 <&clkgen JH7110_WAVE420L_CLK_APB>,
926 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
927 clock-names = "axi_clk", "bpu_clk", "vce_clk",
928 "apb_clk", "noc_bus";
929 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
930 <&rstgen RSTN_U0_WAVE420L_BPU>,
931 <&rstgen RSTN_U0_WAVE420L_VCE>,
932 <&rstgen RSTN_U0_WAVE420L_APB>,
933 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
934 reset-names = "rst_axi", "rst_bpu", "rst_vce",
935 "rst_apb", "rst_sram";
936 starfive,venc_noc_ctrl;
937 power-domains = <&pwrc JH7110_PD_VENC>;
941 rstgen: reset-controller {
942 compatible = "starfive,jh7110-reset";
943 reg = <0x0 0x13020000 0x0 0x10000>,
944 <0x0 0x10230000 0x0 0x10000>,
945 <0x0 0x17000000 0x0 0x10000>,
946 <0x0 0x19810000 0x0 0x10000>,
947 <0x0 0x295C0000 0x0 0x10000>;
948 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
953 stmmac_axi_setup: stmmac-axi-config {
954 snps,wr_osr_lmt = <0xf>;
955 snps,rd_osr_lmt = <0xf>;
956 snps,blen = <256 128 64 32 0 0 0>;
959 gmac0: ethernet@16030000 {
960 compatible = "starfive,dwmac","snps,dwmac-5.10a";
961 reg = <0x0 0x16030000 0x0 0x10000>;
968 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
969 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
970 <&clkgen JH7110_GMAC0_PTP>,
971 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
972 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
973 <&clkgen JH7110_GMAC0_GTXC>;
974 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
975 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
976 reset-names = "ahb", "stmmaceth";
977 interrupts = <7>, <6>, <5> ;
978 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
979 max-frame-size = <9000>;
980 phy-mode = "rgmii-id";
981 snps,multicast-filter-bins = <64>;
982 snps,perfect-filter-entries = <128>;
983 rx-fifo-depth = <2048>;
984 tx-fifo-depth = <2048>;
987 snps,force_thresh_dma_mode;
988 snps,axi-config = <&stmmac_axi_setup>;
990 snps,en-tx-lpi-clockgating;
992 snps,write-requests = <4>;
993 snps,read-requests = <4>;
994 snps,burst-map = <0x7>;
1000 gmac1: ethernet@16040000 {
1001 compatible = "starfive,dwmac","snps,dwmac-5.10a";
1002 reg = <0x0 0x16040000 0x0 0x10000>;
1003 clock-names = "gtx",
1009 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1010 <&clkgen JH7110_GMAC5_CLK_TX>,
1011 <&clkgen JH7110_GMAC5_CLK_PTP>,
1012 <&clkgen JH7110_GMAC5_CLK_AHB>,
1013 <&clkgen JH7110_GMAC5_CLK_AXI>,
1014 <&clkgen JH7110_GMAC1_GTXC>;
1015 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1016 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1017 reset-names = "ahb", "stmmaceth";
1018 interrupts = <78>, <77>, <76> ;
1019 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1020 max-frame-size = <9000>;
1021 phy-mode = "rgmii-id";
1022 snps,multicast-filter-bins = <64>;
1023 snps,perfect-filter-entries = <128>;
1024 rx-fifo-depth = <2048>;
1025 tx-fifo-depth = <2048>;
1028 snps,force_thresh_dma_mode;
1029 snps,axi-config = <&stmmac_axi_setup>;
1031 snps,en-tx-lpi-clockgating;
1033 snps,write-requests = <4>;
1034 snps,read-requests = <4>;
1035 snps,burst-map = <0x7>;
1038 status = "disabled";
1042 compatible = "img-gpu";
1043 reg = <0x0 0x18000000 0x0 0x100000>,
1044 <0x0 0x130C000 0x0 0x10000>;
1045 clocks = <&clkgen JH7110_GPU_CORE>,
1046 <&clkgen JH7110_GPU_CLK_APB>,
1047 <&clkgen JH7110_GPU_RTC_TOGGLE>,
1048 <&clkgen JH7110_GPU_CORE_CLK>,
1049 <&clkgen JH7110_GPU_SYS_CLK>,
1050 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1051 clock-names = "clk_bv", "clk_apb", "clk_rtc",
1052 "clk_core", "clk_sys", "clk_axi";
1053 resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1054 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1055 reset-names = "rst_apb", "rst_doma";
1056 power-domains = <&pwrc JH7110_PD_GPUA>;
1058 current-clock = <8000000>;
1059 status = "disabled";
1062 can0: can@130d0000 {
1063 compatible = "starfive,jh7110-can", "ipms,can";
1064 reg = <0x0 0x130d0000 0x0 0x1000>;
1066 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1067 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1068 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1069 clock-names = "apb_clk", "core_clk", "timer_clk";
1070 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1071 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1072 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1073 reset-names = "rst_apb", "rst_core", "rst_timer";
1074 frequency = <40000000>;
1075 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1076 syscon,can_or_canfd = <0>;
1077 status = "disabled";
1080 can1: can@130e0000 {
1081 compatible = "starfive,jh7110-can", "ipms,can";
1082 reg = <0x0 0x130e0000 0x0 0x1000>;
1084 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1085 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1086 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1087 clock-names = "apb_clk", "core_clk", "timer_clk";
1088 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1089 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1090 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1091 reset-names = "rst_apb", "rst_core", "rst_timer";
1092 frequency = <40000000>;
1093 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1094 syscon,can_or_canfd = <1>;
1095 status = "disabled";
1099 compatible = "starfive,jh7110-tdm";
1100 reg = <0x0 0x10090000 0x0 0x1000>;
1102 clocks = <&clkgen JH7110_AHB0>,
1103 <&clkgen JH7110_TDM_CLK_AHB>,
1104 <&clkgen JH7110_APB0>,
1105 <&clkgen JH7110_TDM_CLK_APB>,
1106 <&clkgen JH7110_TDM_INTERNAL>,
1108 <&clkgen JH7110_TDM_CLK_TDM>,
1109 <&clkgen JH7110_MCLK_INNER>;
1110 clock-names = "clk_ahb0", "clk_tdm_ahb",
1111 "clk_apb0", "clk_tdm_apb",
1112 "clk_tdm_internal", "clk_tdm_ext",
1113 "clk_tdm", "mclk_inner";
1114 resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1115 <&rstgen RSTN_U0_TDM16SLOT_APB>,
1116 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1117 reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1118 dmas = <&dma 20 1>, <&dma 21 1>;
1119 dma-names = "rx","tx";
1120 #sound-dai-cells = <0>;
1121 status = "disabled";
1124 spdif0: spdif0@100a0000 {
1125 compatible = "starfive,jh7110-spdif";
1126 reg = <0x0 0x100a0000 0x0 0x1000>;
1127 clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1128 <&clkgen JH7110_SPDIF_CLK_CORE>,
1129 <&clkgen JH7110_AUDIO_ROOT>,
1130 <&clkgen JH7110_MCLK_INNER>,
1131 <&mclk_ext>, <&clkgen JH7110_MCLK>;
1132 clock-names = "spdif-apb", "spdif-core",
1133 "audroot", "mclk_inner",
1135 resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1136 reset-names = "rst_apb";
1138 interrupt-names = "tx";
1139 #sound-dai-cells = <0>;
1140 status = "disabled";
1143 pwmdac: pwmdac@100b0000 {
1144 compatible = "starfive,jh7110-pwmdac";
1145 reg = <0x0 0x100b0000 0x0 0x1000>;
1146 clocks = <&clkgen JH7110_APB0>,
1147 <&clkgen JH7110_PWMDAC_CLK_APB>,
1148 <&clkgen JH7110_PWMDAC_CLK_CORE>;
1149 clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1150 resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1151 reset-names = "rst-apb";
1154 #sound-dai-cells = <0>;
1155 status = "disabled";
1158 i2stx: i2stx@100c0000 {
1159 compatible = "snps,designware-i2stx";
1160 reg = <0x0 0x100c0000 0x0 0x1000>;
1161 interrupt-names = "tx";
1162 #sound-dai-cells = <0>;
1165 status = "disabled";
1169 compatible = "starfive,jh7110-pdm";
1170 reg = <0x0 0x100d0000 0x0 0x1000>;
1172 clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1173 <&clkgen JH7110_APB0>,
1174 <&clkgen JH7110_PDM_CLK_APB>,
1175 <&clkgen JH7110_MCLK>,
1177 clock-names = "pdm_mclk", "clk_apb0",
1178 "pdm_apb", "clk_mclk",
1180 resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1181 <&rstgen RSTN_U0_PDM_4MIC_APB>;
1182 reset-names = "pdm_dmic", "pdm_apb";
1183 #sound-dai-cells = <0>;
1186 i2srx_mst: i2srx_mst@100e0000 {
1187 compatible = "starfive,jh7110-i2srx-master";
1188 reg = <0x0 0x100e0000 0x0 0x1000>;
1189 clocks = <&clkgen JH7110_APB0>,
1190 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1191 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1192 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1193 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1194 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1195 clock-names = "apb0", "i2srx_apb",
1196 "i2srx_bclk_mst", "i2srx_lrck_mst",
1197 "i2srx_bclk", "i2srx_lrck";
1198 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1199 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1200 reset-names = "rst_apb_rx", "rst_bclk_rx";
1203 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1204 #sound-dai-cells = <0>;
1205 status = "disabled";
1208 i2srx_3ch: i2srx_3ch@100e0000 {
1209 compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1210 reg = <0x0 0x100e0000 0x0 0x1000>;
1211 clocks = <&clkgen JH7110_APB0>,
1212 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1213 <&clkgen JH7110_AUDIO_ROOT>,
1214 <&clkgen JH7110_MCLK_INNER>,
1215 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1216 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1217 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1218 <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1219 <&clkgen JH7110_MCLK>,
1222 clock-names = "apb0", "3ch-apb",
1223 "audioroot", "mclk-inner",
1224 "bclk_mst", "3ch-lrck",
1225 "rx-bclk", "rx-lrck",
1228 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1229 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1232 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1233 #sound-dai-cells = <0>;
1234 status = "disabled";
1237 i2stx_4ch0: i2stx_4ch0@120b0000 {
1238 compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1239 reg = <0x0 0x120b0000 0x0 0x1000>;
1240 clocks = <&clkgen JH7110_MCLK_INNER>,
1241 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1242 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1243 <&clkgen JH7110_MCLK>,
1244 <&clkgen JH7110_I2STX0_4CHBCLK>,
1245 <&clkgen JH7110_I2STX0_4CHLRCK>,
1246 <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1248 clock-names = "inner", "bclk-mst",
1251 "i2s_apb", "mclk_ext";
1252 resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1253 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1254 reset-names = "rst_apb", "rst_bclk";
1257 #sound-dai-cells = <0>;
1258 status = "disabled";
1261 i2stx_4ch1: i2stx_4ch1@120c0000 {
1262 compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1263 reg = <0x0 0x120c0000 0x0 0x1000>;
1264 clocks = <&clkgen JH7110_AUDIO_ROOT>,
1265 <&clkgen JH7110_MCLK_INNER>,
1266 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1267 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1268 <&clkgen JH7110_MCLK>,
1269 <&clkgen JH7110_I2STX1_4CHBCLK>,
1270 <&clkgen JH7110_I2STX1_4CHLRCK>,
1271 <&clkgen JH7110_MCLK_OUT>,
1272 <&clkgen JH7110_APB0>,
1273 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1277 clock-names = "audroot", "mclk_inner", "bclk_mst",
1278 "lrck_mst", "mclk", "4chbclk",
1279 "4chlrck", "mclk_out",
1281 "mclk_ext", "bclk_ext", "lrck_ext";
1282 resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1283 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1286 #sound-dai-cells = <0>;
1287 status = "disabled";
1291 compatible = "starfive,jh7110-pwm";
1292 reg = <0x0 0x120d0000 0x0 0x10000>;
1293 reg-names = "control";
1294 clocks = <&clkgen JH7110_PWM_CLK_APB>;
1295 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1296 starfive,approx-freq = <2000000>;
1298 starfive,npwm = <8>;
1299 status = "disabled";
1302 spdif_transmitter: spdif_transmitter {
1303 compatible = "linux,spdif-dit";
1304 #sound-dai-cells = <0>;
1305 status = "disabled";
1308 pwmdac_codec: pwmdac-transmitter {
1309 compatible = "starfive,jh7110-pwmdac-dit";
1310 #sound-dai-cells = <0>;
1311 status = "disabled";
1314 dmic_codec: dmic_codec {
1315 compatible = "dmic-codec";
1316 #sound-dai-cells = <0>;
1317 status = "disabled";
1320 spi0: spi@10060000 {
1321 compatible = "arm,pl022", "arm,primecell";
1322 reg = <0x0 0x10060000 0x0 0x10000>;
1323 clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1324 clock-names = "apb_pclk";
1325 resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1326 reset-names = "rst_apb";
1328 /* shortage of dma channel that not be used */
1329 /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1330 /*dma-names = "rx","tx";*/
1331 arm,primecell-periphid = <0x00041022>;
1333 #address-cells = <1>;
1335 status = "disabled";
1338 spi1: spi@10070000 {
1339 compatible = "arm,pl022", "arm,primecell";
1340 reg = <0x0 0x10070000 0x0 0x10000>;
1341 clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1342 clock-names = "apb_pclk";
1343 resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1344 reset-names = "rst_apb";
1346 /* shortage of dma channel that not be used */
1347 /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1348 /*dma-names = "rx","tx";*/
1349 arm,primecell-periphid = <0x00041022>;
1351 #address-cells = <1>;
1353 status = "disabled";
1356 spi2: spi@10080000 {
1357 compatible = "arm,pl022", "arm,primecell";
1358 reg = <0x0 0x10080000 0x0 0x10000>;
1359 clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1360 clock-names = "apb_pclk";
1361 resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1362 reset-names = "rst_apb";
1364 /* shortage of dma channel that not be used */
1365 /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1366 /*dma-names = "rx","tx";*/
1367 arm,primecell-periphid = <0x00041022>;
1369 #address-cells = <1>;
1371 status = "disabled";
1374 spi3: spi@12070000 {
1375 compatible = "arm,pl022", "arm,primecell";
1376 reg = <0x0 0x12070000 0x0 0x10000>;
1377 clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1378 clock-names = "apb_pclk";
1379 resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1380 reset-names = "rst_apb";
1382 /* shortage of dma channel that not be used */
1383 /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1384 /*dma-names = "rx","tx";*/
1385 arm,primecell-periphid = <0x00041022>;
1387 #address-cells = <1>;
1389 status = "disabled";
1392 spi4: spi@12080000 {
1393 compatible = "arm,pl022", "arm,primecell";
1394 reg = <0x0 0x12080000 0x0 0x10000>;
1395 clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1396 clock-names = "apb_pclk";
1397 resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1398 reset-names = "rst_apb";
1400 /* shortage of dma channel that not be used */
1401 /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1402 /*dma-names = "rx","tx";*/
1403 arm,primecell-periphid = <0x00041022>;
1405 #address-cells = <1>;
1407 status = "disabled";
1410 spi5: spi@12090000 {
1411 compatible = "arm,pl022", "arm,primecell";
1412 reg = <0x0 0x12090000 0x0 0x10000>;
1413 clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1414 clock-names = "apb_pclk";
1415 resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1416 reset-names = "rst_apb";
1418 /* shortage of dma channel that not be used */
1419 /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1420 /*dma-names = "rx","tx";*/
1421 arm,primecell-periphid = <0x00041022>;
1423 #address-cells = <1>;
1425 status = "disabled";
1428 spi6: spi@120A0000 {
1429 compatible = "arm,pl022", "arm,primecell";
1430 reg = <0x0 0x120A0000 0x0 0x10000>;
1431 clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1432 clock-names = "apb_pclk";
1433 resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1434 reset-names = "rst_apb";
1436 /* shortage of dma channel that not be used */
1437 /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1438 /*dma-names = "rx","tx";*/
1439 arm,primecell-periphid = <0x00041022>;
1441 #address-cells = <1>;
1443 status = "disabled";
1446 pcie0: pcie@2B000000 {
1447 compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1448 #address-cells = <3>;
1450 #interrupt-cells = <1>;
1451 reg = <0x0 0x2B000000 0x0 0x1000000
1452 0x9 0x40000000 0x0 0x10000000>;
1453 reg-names = "reg", "config";
1454 device_type = "pci";
1455 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1456 bus-range = <0x0 0xff>;
1457 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
1458 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
1459 msi-parent = <&plic>;
1461 interrupt-controller;
1462 interrupt-names = "msi";
1463 interrupt-parent = <&plic>;
1464 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1465 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1466 <0x0 0x0 0x0 0x2 &plic 0x2>,
1467 <0x0 0x0 0x0 0x3 &plic 0x3>,
1468 <0x0 0x0 0x0 0x4 &plic 0x4>;
1469 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1470 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1471 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1472 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1473 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1474 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1475 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1476 "rst_brg", "rst_core", "rst_apb";
1477 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1478 <&clkgen JH7110_PCIE0_CLK_TL>,
1479 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1480 <&clkgen JH7110_PCIE0_CLK_APB>;
1481 clock-names = "noc", "tl", "axi_mst0", "apb";
1482 status = "disabled";
1485 pcie1: pcie@2C000000 {
1486 compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1487 #address-cells = <3>;
1489 #interrupt-cells = <1>;
1490 reg = <0x0 0x2C000000 0x0 0x1000000
1491 0x9 0xc0000000 0x0 0x10000000>;
1492 reg-names = "reg", "config";
1493 device_type = "pci";
1494 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1495 bus-range = <0x0 0xff>;
1496 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
1497 <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
1498 msi-parent = <&plic>;
1500 interrupt-controller;
1501 interrupt-names = "msi";
1502 interrupt-parent = <&plic>;
1503 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1504 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1505 <0x0 0x0 0x0 0x2 &plic 0x2>,
1506 <0x0 0x0 0x0 0x3 &plic 0x3>,
1507 <0x0 0x0 0x0 0x4 &plic 0x4>;
1508 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1509 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1510 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1511 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1512 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1513 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1514 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1515 "rst_brg", "rst_core", "rst_apb";
1516 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1517 <&clkgen JH7110_PCIE1_CLK_TL>,
1518 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1519 <&clkgen JH7110_PCIE1_CLK_APB>;
1520 clock-names = "noc", "tl", "axi_mst0", "apb";
1521 status = "disabled";
1524 mailbox_contrl0: mailbox@0 {
1525 compatible = "starfive,mail_box";
1526 reg = <0x0 0x13060000 0x0 0x0001000>;
1527 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1528 clock-names = "clk_apb";
1529 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1530 reset-names = "mbx_rre";
1531 interrupts = <26 27>;
1533 status = "disabled";
1536 mailbox_client0: mailbox_client@0 {
1537 compatible = "starfive,mailbox-test";
1538 mbox-names = "rx", "tx";
1539 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1540 status = "disabled";
1543 display: display-subsystem {
1544 compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1545 ports = <&dc_out_dpi0>;
1546 status = "disabled";
1549 dssctrl: dssctrl@295B0000 {
1550 compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1551 reg = <0 0x295B0000 0 0x90>;
1554 tda988x_pin: tda988x_pin {
1555 compatible = "starfive,tda998x_rgb_pin";
1556 status = "disabled";
1559 rgb_output: rgb-output {
1560 compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1561 //verisilicon,dss-syscon = <&dssctrl>;
1562 //verisilicon,mux-mask = <0x70 0x380>;
1563 //verisilicon,mux-val = <0x40 0x280>;
1564 status = "disabled";
1567 dc8200: dc8200@29400000 {
1568 compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1569 verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1570 reg = <0x0 0x29400000 0x0 0x100>,
1571 <0x0 0x29400800 0x0 0x2000>,
1572 <0x0 0x17030000 0x0 0x1000>;
1574 status = "disabled";
1575 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1576 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1577 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1578 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1579 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1580 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1581 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1582 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1583 <&clkgen JH7110_VOUT_SRC>,
1584 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1585 <&clkgen JH7110_AHB1>,
1586 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1587 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1588 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1589 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1590 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1591 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1592 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1593 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1594 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1595 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1596 <&hdmitx0_pixelclk>,
1597 <&clkvout JH7110_DC8200_PIX0>,
1598 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1599 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1600 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1601 "noc_disp","noc_isp","noc_stg","vout_src",
1602 "top_vout_axi","ahb1","top_vout_ahb",
1603 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1604 "axi_clk","core_clk","vout_ahb",
1605 "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1606 "dc8200_pix0_out","dc8200_pix1_out";
1607 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1608 <&rstgen RSTN_U0_DC8200_AXI>,
1609 <&rstgen RSTN_U0_DC8200_AHB>,
1610 <&rstgen RSTN_U0_DC8200_CORE>,
1611 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1612 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1613 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1614 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1615 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1616 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1617 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1618 "rst_noc_disp","rst_noc_stg";
1619 power-domains = <&pwrc JH7110_PD_VOUT>;
1622 dsi_output: dsi-output {
1623 compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1624 status = "disabled";
1627 mipi_dphy: mipi-dphy@295e0000{
1628 compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1629 reg = <0x0 0x295e0000 0x0 0x10000>;
1630 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1631 clock-names = "dphy_txesc";
1632 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1633 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1634 reset-names = "dphy_sys", "dphy_txbytehs";
1636 status = "disabled";
1639 mipi_dsi: mipi@295d0000 {
1640 compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1641 reg = <0x0 0x295d0000 0x0 0x10000>;
1644 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1645 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1646 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1647 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1648 clock-names = "sys", "apb", "txesc", "dpi";
1649 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1650 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1651 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1652 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1653 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1654 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1655 reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1656 "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1657 phys = <&mipi_dphy>;
1659 status = "disabled";
1662 dsi_out_port: endpoint@0 {
1663 remote-endpoint = <&panel_dsi_port>;
1665 dsi_in_port: endpoint@1 {
1666 remote-endpoint = <&mipi_out>;
1670 mipi_panel: panel@0 {
1671 /*compatible = "";*/
1676 hdmi: hdmi@29590000 {
1677 compatible = "starfive,jh7110-hdmi","inno,hdmi";
1678 reg = <0x0 0x29590000 0x0 0x4000>;
1680 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1681 /*clocks = <&cru PCLK_HDMI>;*/
1682 /*clock-names = "pclk";*/
1683 /*pinctrl-names = "default";*/
1684 /*pinctrl-0 = <&hdmi_ctl>;*/
1685 status = "disabled";
1686 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1687 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1688 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1689 <&hdmitx0_pixelclk>;
1690 clock-names = "sysclk", "mclk", "bclk", "pclk";
1691 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1692 reset-names = "hdmi_tx";
1693 #sound-dai-cells = <0>;
1697 compatible = "simple-audio-card";
1698 simple-audio-card,name = "Starfive-Multi-Sound-Card";
1699 #address-cells = <1>;
1704 compatible = "starfive,e24";
1705 reg = <0x0 0xc0110000 0x0 0x00001000>,
1706 <0x0 0xc0111000 0x0 0x0001f000>;
1707 reg-names = "ecmd", "espace";
1708 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1709 <&clkgen JH7110_E2_CLK_CORE>,
1710 <&clkgen JH7110_E2_CLK_DBG>;
1711 clock-names = "clk_rtc", "clk_core", "clk_dbg";
1712 resets = <&rstgen RSTN_U0_E24_CORE>;
1713 reset-names = "e24_core";
1714 starfive,stg-syscon = <&stg_syscon>;
1715 interrupt-parent = <&plic>;
1716 firmware-name = "e24_elf";
1718 mbox-names = "tx", "rx";
1719 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1720 #address-cells = <1>;
1722 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1723 status = "disabled";
1728 compatible = "cdns,xrp";
1729 reg = <0x0 0x10230000 0x0 0x00010000
1730 0x0 0x10240000 0x0 0x00010000>;
1731 memory-region = <&xrp_reserved>;
1732 clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1733 clock-names = "core_clk";
1734 resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1735 <&rstgen RSTN_U0_HIFI4_AXI>;
1736 reset-names = "rst_core","rst_axi";
1737 starfive,stg-syscon = <&stg_syscon>;
1738 firmware-name = "hifi4_elf";
1739 #address-cells = <1>;
1741 ranges = <0x40000000 0x0 0x20000000 0x040000
1742 0xf0000000 0x0 0xf0000000 0x03000000>;
1743 status = "disabled";
1748 starfive_cpufreq: starfive,jh7110-cpufreq {
1749 compatible = "starfive,jh7110-cpufreq";
1750 clocks = <&clkgen JH7110_CPU_CORE>;
1751 clock-names = "cpu_clk";