arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <880000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <880000>;
  30                         };
  31                         opp-625000000 {
  32                                         opp-hz = /bits/ 64 <625000000>;
  33                                         opp-microvolt = <880000>;
  34                         };
  35                         opp-750000000 {
  36                                         opp-hz = /bits/ 64 <750000000>;
  37                                         opp-microvolt = <880000>;
  38                         };
  39                         opp-875000000 {
  40                                         opp-hz = /bits/ 64 <875000000>;
  41                                         opp-microvolt = <880000>;
  42                         };
  43                         opp-1000000000 {
  44                                         opp-hz = /bits/ 64 <1000000000>;
  45                                         opp-microvolt = <900000>;
  46                         };
  47                         opp-1250000000 {
  48                                         opp-hz = /bits/ 64 <1250000000>;
  49                                         opp-microvolt = <950000>;
  50                         };
  51                         opp-1375000000 {
  52                                         opp-hz = /bits/ 64 <1375000000>;
  53                                         opp-microvolt = <1000000>;
  54                         };
  55                         opp-1500000000 {
  56                                         opp-hz = /bits/ 64 <1500000000>;
  57                                         opp-microvolt = <1100000>;
  58                         };
  59                         opp-1625000000 {
  60                                         opp-hz = /bits/ 64 <1625000000>;
  61                                         opp-microvolt = <1100000>;
  62                         };
  63                         opp-1750000000 {
  64                                         opp-hz = /bits/ 64 <1750000000>;
  65                                         opp-microvolt = <1200000>;
  66                         };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <0>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <8192>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <16384>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  89                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  90                         next-level-cache = <&cachectrl>;
  91                         riscv,isa = "rv64imac";
  92                         tlb-split;
  93                         status = "disabled";
  94
  95                         cpu0intctrl: interrupt-controller {
  96                                 #interrupt-cells = <1>;
  97                                 compatible = "riscv,cpu-intc";
  98                                 interrupt-controller;
  99                         };
 100                 };
 101
 102                 cpu1: cpu@1 {
 103                         compatible = "sifive,u74-mc", "riscv";
 104                         reg = <1>;
 105                         d-cache-block-size = <64>;
 106                         d-cache-sets = <64>;
 107                         d-cache-size = <32768>;
 108                         d-tlb-sets = <1>;
 109                         d-tlb-size = <40>;
 110                         device_type = "cpu";
 111                         i-cache-block-size = <64>;
 112                         i-cache-sets = <64>;
 113                         i-cache-size = <32768>;
 114                         i-tlb-sets = <1>;
 115                         i-tlb-size = <40>;
 116                         mmu-type = "riscv,sv39";
 117                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 118                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 119                         next-level-cache = <&cachectrl>;
 120                         riscv,isa = "rv64imafdc";
 121                         tlb-split;
 122                         status = "okay";
 123                         operating-points-v2 = <&cluster0_opp>;
 124
 125                         cpu1intctrl: interrupt-controller {
 126                                 #interrupt-cells = <1>;
 127                                 compatible = "riscv,cpu-intc";
 128                                 interrupt-controller;
 129                         };
 130                 };
 131
 132                 cpu2: cpu@2 {
 133                         compatible = "sifive,u74-mc", "riscv";
 134                         reg = <2>;
 135                         d-cache-block-size = <64>;
 136                         d-cache-sets = <64>;
 137                         d-cache-size = <32768>;
 138                         d-tlb-sets = <1>;
 139                         d-tlb-size = <40>;
 140                         device_type = "cpu";
 141                         i-cache-block-size = <64>;
 142                         i-cache-sets = <64>;
 143                         i-cache-size = <32768>;
 144                         i-tlb-sets = <1>;
 145                         i-tlb-size = <40>;
 146                         mmu-type = "riscv,sv39";
 147                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 148                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 149                         next-level-cache = <&cachectrl>;
 150                         riscv,isa = "rv64imafdc";
 151                         tlb-split;
 152                         status = "okay";
 153                         operating-points-v2 = <&cluster0_opp>;
 154
 155                         cpu2intctrl: interrupt-controller {
 156                                 #interrupt-cells = <1>;
 157                                 compatible = "riscv,cpu-intc";
 158                                 interrupt-controller;
 159                         };
 160                 };
 161
 162                 cpu3: cpu@3 {
 163                         compatible = "sifive,u74-mc", "riscv";
 164                         reg = <3>;
 165                         d-cache-block-size = <64>;
 166                         d-cache-sets = <64>;
 167                         d-cache-size = <32768>;
 168                         d-tlb-sets = <1>;
 169                         d-tlb-size = <40>;
 170                         device_type = "cpu";
 171                         i-cache-block-size = <64>;
 172                         i-cache-sets = <64>;
 173                         i-cache-size = <32768>;
 174                         i-tlb-sets = <1>;
 175                         i-tlb-size = <40>;
 176                         mmu-type = "riscv,sv39";
 177                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 178                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 179                         next-level-cache = <&cachectrl>;
 180                         riscv,isa = "rv64imafdc";
 181                         tlb-split;
 182                         status = "okay";
 183                         operating-points-v2 = <&cluster0_opp>;
 184
 185                         cpu3intctrl: interrupt-controller {
 186                                 #interrupt-cells = <1>;
 187                                 compatible = "riscv,cpu-intc";
 188                                 interrupt-controller;
 189                         };
 190                 };
 191
 192                 cpu4: cpu@4 {
 193                         compatible = "sifive,u74-mc", "riscv";
 194                         reg = <4>;
 195                         d-cache-block-size = <64>;
 196                         d-cache-sets = <64>;
 197                         d-cache-size = <32768>;
 198                         d-tlb-sets = <1>;
 199                         d-tlb-size = <40>;
 200                         device_type = "cpu";
 201                         i-cache-block-size = <64>;
 202                         i-cache-sets = <64>;
 203                         i-cache-size = <32768>;
 204                         i-tlb-sets = <1>;
 205                         i-tlb-size = <40>;
 206                         mmu-type = "riscv,sv39";
 207                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 208                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 209                         next-level-cache = <&cachectrl>;
 210                         riscv,isa = "rv64imafdc";
 211                         tlb-split;
 212                         status = "okay";
 213                         operating-points-v2 = <&cluster0_opp>;
 214
 215                         cpu4intctrl: interrupt-controller {
 216                                 #interrupt-cells = <1>;
 217                                 compatible = "riscv,cpu-intc";
 218                                 interrupt-controller;
 219                         };
 220                 };
 221         };
 222
 223     idle-states {
 224         CPU_RET_0_0: cpu-retentive-0-0 {
 225             compatible = "starfive,jh7110-idle-state";
 226             riscv,sbi-suspend-param = <0x10000000>;
 227             entry-latency-us = <20>;
 228             exit-latency-us = <40>;
 229             min-residency-us = <80>;
 230         };
 231
 232         CPU_NONRET_0_0: cpu-nonretentive-0-0 {
 233             compatible = "starfive,jh7110-idle-state";
 234             riscv,sbi-suspend-param = <0x90000000>;
 235             entry-latency-us = <250>;
 236             exit-latency-us = <500>;
 237             min-residency-us = <950>;
 238         };
 239
 240         CLUSTER_RET_0: cluster-retentive-0 {
 241             compatible = "starfive,jh7110-idle-state";
 242             riscv,sbi-suspend-param = <0x11000000>;
 243             local-timer-stop;
 244             entry-latency-us = <50>;
 245             exit-latency-us = <100>;
 246             min-residency-us = <250>;
 247             wakeup-latency-us = <130>;
 248         };
 249
 250         CLUSTER_NONRET_0: cluster-nonretentive-0 {
 251             compatible = "starfive,jh7110-idle-state";
 252             riscv,sbi-suspend-param = <0x91000000>;
 253             local-timer-stop;
 254             entry-latency-us = <600>;
 255             exit-latency-us = <1100>;
 256             min-residency-us = <2700>;
 257             wakeup-latency-us = <1500>;
 258         };
 259         };
 260
 261         soc: soc {
 262                 compatible = "simple-bus";
 263                 interrupt-parent = <&plic>;
 264                 #address-cells = <2>;
 265                 #size-cells = <2>;
 266                 #clock-cells = <1>;
 267                 ranges;
 268
 269                 cachectrl: cache-controller@2010000 {
 270                         compatible = "sifive,fu740-c000-ccache", "cache";
 271                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 272                         reg-names = "control", "sideband";
 273                         interrupts = <1 3 4 2>;
 274                         cache-block-size = <64>;
 275                         cache-level = <2>;
 276                         cache-sets = <2048>;
 277                         cache-size = <2097152>;
 278                         cache-unified;
 279                 };
 280
 281                 aon_syscon: aon_syscon@17010000 {
 282                         compatible = "syscon";
 283                         reg = <0x0 0x17010000 0x0 0x1000>;
 284                 };
 285
 286                 stg_syscon: stg_syscon@10240000 {
 287                         compatible = "syscon";
 288                         reg = <0x0 0x10240000 0x0 0x1000>;
 289                 };
 290
 291                 sys_syscon: sys_syscon@13030000 {
 292                         compatible = "syscon";
 293                         reg = <0x0 0x13030000 0x0 0x1000>;
 294                 };
 295
 296                 clint: clint@2000000 {
 297                         compatible = "riscv,clint0";
 298                         reg = <0x0 0x2000000 0x0 0x10000>;
 299                         reg-names = "control";
 300                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 301                                                 &cpu1intctrl 3 &cpu1intctrl 7
 302                                                 &cpu2intctrl 3 &cpu2intctrl 7
 303                                                 &cpu3intctrl 3 &cpu3intctrl 7
 304                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 305                         #interrupt-cells = <1>;
 306                 };
 307
 308                 plic: plic@c000000 {
 309                         compatible = "riscv,plic0";
 310                         reg = <0x0 0xc000000 0x0 0x4000000>;
 311                         reg-names = "control";
 312                         interrupts-extended = <&cpu0intctrl 11
 313                                                 &cpu1intctrl 11 &cpu1intctrl 9
 314                                                 &cpu2intctrl 11 &cpu2intctrl 9
 315                                                 &cpu3intctrl 11 &cpu3intctrl 9
 316                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <1>;
 319                         riscv,max-priority = <7>;
 320                         riscv,ndev = <136>;
 321                 };
 322
 323                 clkgen: clock-controller {
 324                         compatible = "starfive,jh7110-clkgen";
 325                         reg = <0x0 0x13020000 0x0 0x10000>,
 326                                 <0x0 0x10230000 0x0 0x10000>,
 327                                 <0x0 0x17000000 0x0 0x10000>;
 328                         reg-names = "sys", "stg", "aon";
 329                         clocks = <&osc>, <&gmac1_rmii_refin>,
 330                                  <&gmac1_rgmii_rxin>,
 331                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 332                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 333                                  <&tdm_ext>, <&mclk_ext>,
 334                                  <&jtag_tck_inner>, <&bist_apb>,
 335                                  <&clk_rtc>,
 336                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 337                         clock-names = "osc", "gmac1_rmii_refin",
 338                                 "gmac1_rgmii_rxin",
 339                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 340                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 341                                 "tdm_ext", "mclk_ext",
 342                                 "jtag_tck_inner", "bist_apb",
 343                                 "clk_rtc",
 344                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 345                         #clock-cells = <1>;
 346                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 347                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 348                         status = "okay";
 349                 };
 350
 351                 clkvout: clock-controller@295C0000 {
 352                         compatible = "starfive,jh7110-clk-vout";
 353                         reg = <0x0 0x295C0000 0x0 0x10000>;
 354                         reg-names = "vout";
 355                         clocks = <&hdmitx0_pixelclk>,
 356                                  <&mipitx_dphy_rxesc>,
 357                                  <&mipitx_dphy_txbytehs>,
 358                                  <&clkgen JH7110_VOUT_SRC>,
 359                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 360                         clock-names = "hdmitx0_pixelclk",
 361                                       "mipitx_dphy_rxesc",
 362                                       "mipitx_dphy_txbytehs",
 363                                       "vout_src",
 364                                       "vout_top_ahb";
 365                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 366                         reset-names = "vout_src";
 367                         #clock-cells = <1>;
 368                         power-domains = <&pwrc JH7110_PD_VOUT>;
 369                         status = "okay";
 370                 };
 371
 372                 clkisp: clock-controller@19810000 {
 373                         compatible = "starfive,jh7110-clk-isp";
 374                         reg = <0x0 0x19810000 0x0 0x10000>;
 375                         reg-names = "isp";
 376                         #clock-cells = <1>;
 377                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 378                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 379                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 380                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 381                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 382                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 383                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 384                                       "u0_sft7110_noc_bus_clk_isp_axi";
 385                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 386                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 387                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 388                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 389                                       "rst_isp_noc_bus_n";
 390                         power-domains = <&pwrc JH7110_PD_ISP>;
 391                         status = "okay";
 392                 };
 393
 394                 qspi: spi@13010000 {
 395                         compatible = "cdns,qspi-nor";
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         reg = <0x0 0x13010000 0x0 0x10000
 399                                 0x0 0x21000000 0x0 0x400000>;
 400                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 401                         clock-names = "clk_ref";
 402                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 403                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 404                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 405                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 406                         cdns,fifo-depth = <256>;
 407                         cdns,fifo-width = <4>;
 408                         spi-max-frequency = <250000000>;
 409
 410                         nor_flash: nor-flash@0 {
 411                                 compatible = "jedec,spi-nor";
 412                                 reg=<0>;
 413                                 spi-max-frequency = <100000000>;
 414                                 cdns,tshsl-ns = <1>;
 415                                 cdns,tsd2d-ns = <1>;
 416                                 cdns,tchsh-ns = <1>;
 417                                 cdns,tslch-ns = <1>;
 418                         };
 419                 };
 420
 421                 otp: otp@17050000 {
 422                         compatible = "starfive,jh7110-otp";
 423                         reg = <0x0 0x17050000 0x0 0x10000>;
 424                         clock-frequency = <4000000>;
 425                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 426                         clock-names = "apb";
 427                 };
 428
 429                 usbdrd30: usbdrd{
 430                         compatible = "starfive,jh7110-cdns3";
 431                         reg = <0x0 0x10210000 0x0 0x1000>,
 432                               <0x0 0x10200000 0x0 0x1000>;
 433                         clocks = <&clkgen JH7110_USB_125M>,
 434                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 435                                  <&clkgen JH7110_USB0_CLK_LPM>,
 436                                  <&clkgen JH7110_USB0_CLK_STB>,
 437                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 438                                  <&clkgen JH7110_USB0_CLK_AXI>,
 439                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 440                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 441                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 442                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 443                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 444                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 445                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 446                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 447                         reset-names = "pwrup","apb","axi","utmi", "phy";
 448                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 449                         starfive,sys-syscon = <&sys_syscon 0x18>;
 450                         status = "disabled";
 451                         #address-cells = <2>;
 452                         #size-cells = <2>;
 453                         #interrupt-cells = <1>;
 454                         ranges;
 455                         usbdrd_cdns3: usb@10100000 {
 456                                 compatible = "cdns,usb3";
 457                                 reg = <0x0 0x10100000 0x0 0x10000>,
 458                                       <0x0 0x10110000 0x0 0x10000>,
 459                                       <0x0 0x10120000 0x0 0x10000>;
 460                                 reg-names = "otg", "xhci", "dev";
 461                                 interrupts = <100>, <108>, <110>;
 462                                 interrupt-names = "host", "peripheral", "otg";
 463                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 464                                 maximum-speed = "super-speed";
 465                         };
 466                 };
 467
 468                 timer: timer@13050000 {
 469                         compatible = "starfive,jh7110-timers";
 470                         reg = <0x0 0x13050000 0x0 0x10000>;
 471                         interrupts = <69>, <70>, <71> ,<72>;
 472                         interrupt-names = "timer0", "timer1",
 473                                           "timer2", "timer3";
 474                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 475                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 476                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 477                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 478                                  <&clkgen JH7110_TIMER_CLK_APB>;
 479                         clock-names = "timer0", "timer1",
 480                                       "timer2", "timer3", "apb_clk";
 481                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 482                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 483                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 484                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 485                                  <&rstgen RSTN_U0_TIMER_APB>;
 486                         reset-names = "timer0", "timer1",
 487                                       "timer2", "timer3", "apb_rst";
 488                         clock-frequency = <24000000>;
 489                         status = "okay";
 490                 };
 491
 492                 wdog: wdog@13070000 {
 493                         compatible = "starfive,jh7110-wdt";
 494                         reg = <0x0 0x13070000 0x0 0x10000>;
 495                         interrupts = <68>;
 496                         interrupt-names = "wdog";
 497                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 498                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 499                         clock-names = "core_clk", "apb_clk";
 500                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 501                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 502                         reset-names = "rst_apb", "rst_core";
 503                         timeout-sec = <15>;
 504                         status = "okay";
 505                 };
 506
 507                 rtc: rtc@17040000 {
 508                         compatible = "starfive,jh7110-rtc";
 509                         reg = <0x0 0x17040000 0x0 0x10000>;
 510                         interrupts = <10>, <11>, <12>;
 511                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 512                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 513                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 514                         clock-names = "pclk", "cal_clk";
 515                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 516                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 517                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 518                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 519                         rtc,cal-clock-freq = <1000000>;
 520                         status = "okay";
 521                 };
 522
 523                 pwrc: power-controller@17030000 {
 524                         compatible = "starfive,jh7110-pmu";
 525                         reg = <0x0 0x17030000 0x0 0x10000>;
 526                         interrupts = <111>;
 527                         #power-domain-cells = <1>;
 528                         status = "okay";
 529                 };
 530
 531                 uart0: serial@10000000 {
 532                         compatible = "snps,dw-apb-uart";
 533                         reg = <0x0 0x10000000 0x0 0x10000>;
 534                         reg-io-width = <4>;
 535                         reg-shift = <2>;
 536                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 537                                  <&clkgen JH7110_UART0_CLK_APB>;
 538                         clock-names = "baudclk", "apb_pclk";
 539                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 540                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 541                         interrupts = <32>;
 542                         status = "disabled";
 543                 };
 544
 545                 uart1: serial@10010000 {
 546                         compatible = "snps,dw-apb-uart";
 547                         reg = <0x0 0x10010000 0x0 0x10000>;
 548                         reg-io-width = <4>;
 549                         reg-shift = <2>;
 550                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 551                                  <&clkgen JH7110_UART1_CLK_APB>;
 552                         clock-names = "baudclk", "apb_pclk";
 553                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 554                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 555                         interrupts = <33>;
 556                         status = "disabled";
 557                 };
 558
 559                 uart2: serial@10020000 {
 560                         compatible = "snps,dw-apb-uart";
 561                         reg = <0x0 0x10020000 0x0 0x10000>;
 562                         reg-io-width = <4>;
 563                         reg-shift = <2>;
 564                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 565                                  <&clkgen JH7110_UART2_CLK_APB>;
 566                         clock-names = "baudclk", "apb_pclk";
 567                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 568                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 569                         interrupts = <34>;
 570                         status = "disabled";
 571                 };
 572
 573                 uart3: serial@12000000 {
 574                         compatible = "snps,dw-apb-uart";
 575                         reg = <0x0 0x12000000 0x0 0x10000>;
 576                         reg-io-width = <4>;
 577                         reg-shift = <2>;
 578                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 579                                  <&clkgen JH7110_UART3_CLK_APB>;
 580                         clock-names = "baudclk", "apb_pclk";
 581                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 582                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 583                         interrupts = <45>;
 584                         status = "disabled";
 585                 };
 586
 587                 uart4: serial@12010000 {
 588                         compatible = "snps,dw-apb-uart";
 589                         reg = <0x0 0x12010000 0x0 0x10000>;
 590                         reg-io-width = <4>;
 591                         reg-shift = <2>;
 592                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 593                                  <&clkgen JH7110_UART4_CLK_APB>;
 594                         clock-names = "baudclk", "apb_pclk";
 595                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 596                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 597                         interrupts = <46>;
 598                         status = "disabled";
 599                 };
 600
 601                 uart5: serial@12020000 {
 602                         compatible = "snps,dw-apb-uart";
 603                         reg = <0x0 0x12020000 0x0 0x10000>;
 604                         reg-io-width = <4>;
 605                         reg-shift = <2>;
 606                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 607                                  <&clkgen JH7110_UART5_CLK_APB>;
 608                         clock-names = "baudclk", "apb_pclk";
 609                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 610                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 611                         interrupts = <47>;
 612                         status = "disabled";
 613                 };
 614
 615                 dma: dma-controller@16050000 {
 616                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 617                         reg = <0x0 0x16050000 0x0 0x10000>;
 618                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 619                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 620                         clock-names = "core-clk", "cfgr-clk";
 621                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 622                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 623                         reset-names = "rst_axi", "rst_ahb";
 624                         interrupts = <73>;
 625                         #dma-cells = <2>;
 626                         dma-channels = <4>;
 627                         snps,dma-masters = <1>;
 628                         snps,data-width = <3>;
 629                         snps,num-hs-if = <56>;
 630                         snps,block-size = <65536 65536 65536 65536>;
 631                         snps,priority = <0 1 2 3>;
 632                         snps,axi-max-burst-len = <16>;
 633                         status = "disabled";
 634                 };
 635
 636                 gpio: gpio@13040000 {
 637                         compatible = "starfive,jh7110-sys-pinctrl";
 638                         reg = <0x0 0x13040000 0x0 0x10000>;
 639                         reg-names = "control";
 640                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 641                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 642                         interrupts = <86>;
 643                         interrupt-controller;
 644                         #gpio-cells = <2>;
 645                         ngpios = <64>;
 646                         status = "okay";
 647                 };
 648
 649                 gpioa: gpio@17020000 {
 650                         compatible = "starfive,jh7110-aon-pinctrl";
 651                         reg = <0x0 0x17020000 0x0 0x10000>;
 652                         reg-names = "control";
 653                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 654                         interrupts = <85>;
 655                         interrupt-controller;
 656                         #gpio-cells = <2>;
 657                         ngpios = <4>;
 658                         status = "okay";
 659                 };
 660
 661                 sfctemp: tmon@120e0000  {
 662                         compatible = "starfive,jh7110-temp";
 663                         reg = <0x0 0x120e0000 0x0 0x10000>;
 664                         interrupts = <81>;
 665                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 666                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 667                         clock-names = "sense", "bus";
 668                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 669                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 670                         reset-names = "sense", "bus";
 671                         #thermal-sensor-cells = <0>;
 672                         status = "disabled";
 673                 };
 674
 675                 thermal-zones {
 676                         cpu-thermal {
 677                                 polling-delay-passive = <250>;
 678                                 polling-delay = <15000>;
 679
 680                                 thermal-sensors = <&sfctemp>;
 681
 682                                 cooling-maps {
 683                                 };
 684
 685                                 trips {
 686                                         cpu_alert0: cpu_alert0 {
 687                                                 /* milliCelsius */
 688                                                 temperature = <75000>;
 689                                                 hysteresis = <2000>;
 690                                                 type = "passive";
 691                                         };
 692
 693                                         cpu_crit: cpu_crit {
 694                                                 /* milliCelsius */
 695                                                 temperature = <90000>;
 696                                                 hysteresis = <2000>;
 697                                                 type = "critical";
 698                                         };
 699                                 };
 700                         };
 701                 };
 702
 703                 trng: trng@1600C000 {
 704                         compatible = "starfive,jh7110-trng";
 705                         reg = <0x0 0x1600C000 0x0 0x4000>;
 706                         clocks = <&clkgen JH7110_SEC_HCLK>,
 707                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 708                         clock-names = "hclk", "miscahb_clk";
 709                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 710                         interrupts = <30>;
 711                         status = "disabled";
 712                 };
 713
 714                 sec_dma: sec_dma@16008000 {
 715                         compatible = "starfive,pl080", "arm,pl080", "arm,primecell";
 716                         reg = <0x0 0x16008000 0x0 0x4000>;
 717                         reg-names = "sec_dma";
 718                         interrupts = <29>;
 719                         clocks = <&clkgen JH7110_SEC_HCLK>,
 720                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 721                         clock-names = "sec_hclk","sec_ahb";
 722                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 723                         reset-names = "sec_hre";
 724                         lli-bus-interface-ahb1;
 725                         mem-bus-interface-ahb1;
 726                         memcpy-burst-size = <256>;
 727                         memcpy-bus-width = <32>;
 728                         #dma-cells = <2>;
 729                         status = "disabled";
 730                 };
 731
 732                 crypto: crypto@16000000 {
 733                         compatible = "starfive,jh7110-sec";
 734                         reg = <0x0 0x16000000 0x0 0x4000>,
 735                               <0x0 0x16008000 0x0 0x4000>;
 736                         reg-names = "secreg","secdma";
 737                         interrupts = <28>, <29>;
 738                         interrupt-names = "secirq", "dmairq";
 739                         clocks = <&clkgen JH7110_SEC_HCLK>,
 740                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 741                         clock-names = "sec_hclk","sec_ahb";
 742                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 743                         reset-names = "sec_hre";
 744                         enable-side-channel-mitigation = "true";
 745                         enable-dma = "true";
 746                         dmas = <&sec_dma 1 2>,
 747                                <&sec_dma 0 2>;
 748                         dma-names = "sec_m","sec_p";
 749                         status = "disabled";
 750                 };
 751
 752                 i2c0: i2c@10030000 {
 753                         compatible = "snps,designware-i2c";
 754                         reg = <0x0 0x10030000 0x0 0x10000>;
 755                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 756                                  <&clkgen JH7110_I2C0_CLK_APB>;
 757                         clock-names = "ref", "pclk";
 758                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 759                         interrupts = <35>;
 760                         #address-cells = <1>;
 761                         #size-cells = <0>;
 762                         status = "disabled";
 763                 };
 764
 765                 i2c1: i2c@10040000 {
 766                         compatible = "snps,designware-i2c";
 767                         reg = <0x0 0x10040000 0x0 0x10000>;
 768                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 769                                  <&clkgen JH7110_I2C1_CLK_APB>;
 770                         clock-names = "ref", "pclk";
 771                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 772                         interrupts = <36>;
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         status = "disabled";
 776                 };
 777
 778                 i2c2: i2c@10050000 {
 779                         compatible = "snps,designware-i2c";
 780                         reg = <0x0 0x10050000 0x0 0x10000>;
 781                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 782                                  <&clkgen JH7110_I2C2_CLK_APB>;
 783                         clock-names = "ref", "pclk";
 784                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 785                         interrupts = <37>;
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788                         status = "disabled";
 789                 };
 790
 791                 i2c3: i2c@12030000 {
 792                         compatible = "snps,designware-i2c";
 793                         reg = <0x0 0x12030000 0x0 0x10000>;
 794                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 795                                  <&clkgen JH7110_I2C3_CLK_APB>;
 796                         clock-names = "ref", "pclk";
 797                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 798                         interrupts = <48>;
 799                         #address-cells = <1>;
 800                         #size-cells = <0>;
 801                         status = "disabled";
 802                 };
 803
 804                 i2c4: i2c@12040000 {
 805                         compatible = "snps,designware-i2c";
 806                         reg = <0x0 0x12040000 0x0 0x10000>;
 807                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 808                                  <&clkgen JH7110_I2C4_CLK_APB>;
 809                         clock-names = "ref", "pclk";
 810                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 811                         interrupts = <49>;
 812                         #address-cells = <1>;
 813                         #size-cells = <0>;
 814                         status = "disabled";
 815                 };
 816
 817                 i2c5: i2c@12050000 {
 818                         compatible = "snps,designware-i2c";
 819                         reg = <0x0 0x12050000 0x0 0x10000>;
 820                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 821                                  <&clkgen JH7110_I2C5_CLK_APB>;
 822                         clock-names = "ref", "pclk";
 823                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 824                         interrupts = <50>;
 825                         #address-cells = <1>;
 826                         #size-cells = <0>;
 827                         status = "disabled";
 828                 };
 829
 830                 i2c6: i2c@12060000 {
 831                         compatible = "snps,designware-i2c";
 832                         reg = <0x0 0x12060000 0x0 0x10000>;
 833                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 834                                  <&clkgen JH7110_I2C6_CLK_APB>;
 835                         clock-names = "ref", "pclk";
 836                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 837                         interrupts = <51>;
 838                         #address-cells = <1>;
 839                         #size-cells = <0>;
 840                         status = "disabled";
 841                 };
 842
 843                 /* unremovable emmc as mmcblk0 */
 844                 sdio0: sdio0@16010000 {
 845                         compatible = "starfive,jh7110-sdio", "snps,dw-mshc";
 846                         reg = <0x0 0x16010000 0x0 0x10000>;
 847                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 848                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 849                         clock-names = "biu","ciu";
 850                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 851                         reset-names = "reset";
 852                         interrupts = <74>;
 853                         fifo-depth = <32>;
 854                         fifo-watermark-aligned;
 855                         data-addr = <0>;
 856                         status = "disabled";
 857                 };
 858
 859                 sdio1: sdio1@16020000 {
 860                         compatible = "starfive,jh7110-sdio", "snps,dw-mshc";
 861                         reg = <0x0 0x16020000 0x0 0x10000>;
 862                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 863                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 864                         clock-names = "biu","ciu";
 865                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 866                         reset-names = "reset";
 867                         interrupts = <75>;
 868                         fifo-depth = <32>;
 869                         fifo-watermark-aligned;
 870                         data-addr = <0>;
 871                         status = "disabled";
 872                 };
 873
 874                 vin_sysctl: vin_sysctl@19800000 {
 875                         compatible = "starfive,jh7110-vin";
 876                         reg = <0x0 0x19800000 0x0 0x10000>,
 877                                 <0x0 0x19810000 0x0 0x10000>,
 878                                 <0x0 0x19820000 0x0 0x10000>,
 879                                 <0x0 0x19840000 0x0 0x10000>,
 880                                 <0x0 0x19870000 0x0 0x30000>,
 881                                 <0x0 0x11840000 0x0 0x10000>,
 882                                 <0x0 0x17030000 0x0 0x10000>,
 883                                 <0x0 0x13020000 0x0 0x10000>;
 884                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 885                                 "isp", "trst", "pmu", "syscrg";
 886                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 887                                  <&clkisp JH7110_U0_VIN_PCLK>,
 888                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 889                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 890                                  <&clkisp JH7110_DVP_INV>,
 891                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 892                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 893                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 894                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 895                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 896                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 897                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 898                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 899                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 900                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 901                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 902                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 903                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 904                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 905                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 906                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 907                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 908                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 909                                 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
 910                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 911                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 912                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 913                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 914                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 915                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 916                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 917                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 918                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 919                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 920                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 921                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 922                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 923                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 924                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 925                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 926                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 927                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 928                                 "rst_isp_top_n", "rst_isp_top_axi";
 929                         starfive,aon-syscon = <&aon_syscon 0x00>;
 930                         power-domains = <&pwrc JH7110_PD_ISP>;
 931                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 932                         interrupts = <92 87 88 89 90>;
 933                         status = "disabled";
 934                 };
 935
 936                 jpu: jpu@11900000 {
 937                         compatible = "starfive,jpu";
 938                         reg = <0x0 0x13090000 0x0 0x300>;
 939                         interrupts = <14>;
 940                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 941                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 942                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 943                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 944                         clock-names = "axi_clk", "core_clk",
 945                                       "apb_clk", "noc_bus";
 946                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 947                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 948                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 949                         reset-names = "rst_axi", "rst_core", "rst_apb";
 950                         power-domains = <&pwrc JH7110_PD_VDEC>;
 951                         status = "disabled";
 952                 };
 953
 954                 vpu_dec: vpu_dec@130A0000 {
 955                         compatible = "starfive,vdec";
 956                         reg = <0x0 0x130A0000 0x0 0x10000>;
 957                         interrupts = <13>;
 958                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 959                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 960                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 961                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 962                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 963                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 964                                       "apb_clk", "noc_bus";
 965                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 966                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 967                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 968                                 <&rstgen RSTN_U0_WAVE511_APB>,
 969                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 970                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 971                                       "rst_apb", "rst_sram";
 972                         starfive,vdec_noc_ctrl;
 973                         power-domains = <&pwrc JH7110_PD_VDEC>;
 974                         status = "disabled";
 975                 };
 976
 977                 vpu_enc: vpu_enc@130B0000 {
 978                         compatible = "starfive,venc";
 979                         reg = <0x0 0x130B0000 0x0 0x10000>;
 980                         interrupts = <15>;
 981                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 982                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 983                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 984                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 985                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 986                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 987                                       "apb_clk", "noc_bus";
 988                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 989                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 990                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 991                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 992                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 993                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 994                                       "rst_apb", "rst_sram";
 995                         starfive,venc_noc_ctrl;
 996                         power-domains = <&pwrc JH7110_PD_VENC>;
 997                         status = "disabled";
 998                 };
 999
1000                 rstgen: reset-controller {
1001                         compatible = "starfive,jh7110-reset";
1002                         reg = <0x0 0x13020000 0x0 0x10000>,
1003                                 <0x0 0x10230000 0x0 0x10000>,
1004                                 <0x0 0x17000000 0x0 0x10000>,
1005                                 <0x0 0x19810000 0x0 0x10000>,
1006                                 <0x0 0x295C0000 0x0 0x10000>;
1007                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
1008                         #reset-cells = <1>;
1009                         status = "okay";
1010                 };
1011
1012                 stmmac_axi_setup: stmmac-axi-config {
1013                         snps,wr_osr_lmt = <0xf>;
1014                         snps,rd_osr_lmt = <0xf>;
1015                         snps,blen = <256 128 64 32 0 0 0>;
1016                 };
1017
1018                 gmac0: ethernet@16030000 {
1019                         compatible = "starfive,jh7110-eqos-5.20";
1020                         reg = <0x0 0x16030000 0x0 0x10000>;
1021                         clock-names = "gtx",
1022                                 "tx",
1023                                 "ptp_ref",
1024                                 "stmmaceth",
1025                                 "pclk",
1026                                 "gtxc";
1027                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
1028                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
1029                                  <&clkgen JH7110_GMAC0_PTP>,
1030                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
1031                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
1032                                  <&clkgen JH7110_GMAC0_GTXC>;
1033                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
1034                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
1035                         reset-names = "ahb", "stmmaceth";
1036                         interrupts = <7>, <6>, <5> ;
1037                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1038                         max-frame-size = <9000>;
1039                         phy-mode = "rgmii-id";
1040                         snps,multicast-filter-bins = <64>;
1041                         snps,perfect-filter-entries = <128>;
1042                         rx-fifo-depth = <2048>;
1043                         tx-fifo-depth = <2048>;
1044                         snps,fixed-burst;
1045                         snps,no-pbl-x8;
1046                         snps,force_thresh_dma_mode;
1047                         snps,axi-config = <&stmmac_axi_setup>;
1048                         snps,tso;
1049                         snps,en-tx-lpi-clockgating;
1050                         snps,en-lpi;
1051                         snps,write-requests = <4>;
1052                         snps,read-requests = <4>;
1053                         snps,burst-map = <0x7>;
1054                         snps,txpbl = <16>;
1055                         snps,rxpbl = <16>;
1056                         status = "disabled";
1057                 };
1058
1059                 gmac1: ethernet@16040000 {
1060                         compatible = "starfive,jh7110-eqos-5.20";
1061                         reg = <0x0 0x16040000 0x0 0x10000>;
1062                         clock-names = "gtx",
1063                                 "tx",
1064                                 "ptp_ref",
1065                                 "stmmaceth",
1066                                 "pclk",
1067                                 "gtxc";
1068                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1069                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1070                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1071                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1072                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1073                                  <&clkgen JH7110_GMAC1_GTXC>;
1074                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1075                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1076                         reset-names = "ahb", "stmmaceth";
1077                         interrupts = <78>, <77>, <76> ;
1078                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1079                         max-frame-size = <9000>;
1080                         phy-mode = "rgmii-id";
1081                         snps,multicast-filter-bins = <64>;
1082                         snps,perfect-filter-entries = <128>;
1083                         rx-fifo-depth = <2048>;
1084                         tx-fifo-depth = <2048>;
1085                         snps,fixed-burst;
1086                         snps,no-pbl-x8;
1087                         snps,force_thresh_dma_mode;
1088                         snps,axi-config = <&stmmac_axi_setup>;
1089                         snps,tso;
1090                         snps,en-tx-lpi-clockgating;
1091                         snps,en-lpi;
1092                         snps,write-requests = <4>;
1093                         snps,read-requests = <4>;
1094                         snps,burst-map = <0x7>;
1095                         snps,txpbl = <16>;
1096                         snps,rxpbl = <16>;
1097                         status = "disabled";
1098                 };
1099
1100                 gpu: gpu@18000000 {
1101                         compatible = "img-gpu";
1102                         reg = <0x0 0x18000000 0x0 0x100000>,
1103                                 <0x0 0x130C000 0x0 0x10000>;
1104                         clocks = <&clkgen JH7110_GPU_CLK_APB>,
1105                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1106                                  <&clkgen JH7110_GPU_CORE_CLK>,
1107                                  <&clkgen JH7110_GPU_SYS_CLK>,
1108                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1109                         clock-names = "clk_apb", "clk_rtc", "clk_core",
1110                                         "clk_sys", "clk_axi";
1111                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1112                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1113                         reset-names = "rst_apb", "rst_doma";
1114                         power-domains = <&pwrc JH7110_PD_GPUA>;
1115                         interrupts = <82>;
1116                         current-clock = <8000000>;
1117                         status = "disabled";
1118                 };
1119
1120                 can0: can@130d0000 {
1121                         compatible = "starfive,jh7110-can", "ipms,can";
1122                         reg = <0x0 0x130d0000 0x0 0x1000>;
1123                         interrupts = <112>;
1124                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1125                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1126                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1127                         clock-names = "apb_clk", "core_clk", "timer_clk";
1128                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1129                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1130                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1131                         reset-names = "rst_apb", "rst_core", "rst_timer";
1132                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1133                         status = "disabled";
1134                 };
1135
1136                 can1: can@130e0000 {
1137                         compatible = "starfive,jh7110-can", "ipms,can";
1138                         reg = <0x0 0x130e0000 0x0 0x1000>;
1139                         interrupts = <113>;
1140                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1141                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1142                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1143                         clock-names = "apb_clk", "core_clk", "timer_clk";
1144                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1145                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1146                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1147                         reset-names = "rst_apb", "rst_core", "rst_timer";
1148                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1149                         status = "disabled";
1150                 };
1151
1152                 tdm: tdm@10090000 {
1153                         compatible = "starfive,jh7110-tdm";
1154                         reg = <0x0 0x10090000 0x0 0x1000>;
1155                         reg-names = "tdm";
1156                         clocks = <&clkgen JH7110_AHB0>,
1157                                  <&clkgen JH7110_TDM_CLK_AHB>,
1158                                  <&clkgen JH7110_APB0>,
1159                                  <&clkgen JH7110_TDM_CLK_APB>,
1160                                  <&clkgen JH7110_TDM_INTERNAL>,
1161                                  <&tdm_ext>,
1162                                  <&clkgen JH7110_TDM_CLK_TDM>,
1163                                  <&clkgen JH7110_MCLK_INNER>;
1164                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1165                                       "clk_apb0", "clk_tdm_apb",
1166                                       "clk_tdm_internal", "clk_tdm_ext",
1167                                       "clk_tdm", "mclk_inner";
1168                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1169                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1170                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1171                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1172                         dmas = <&dma 20 1>, <&dma 21 1>;
1173                         dma-names = "rx","tx";
1174                         #sound-dai-cells = <0>;
1175                         status = "disabled";
1176                 };
1177
1178                 spdif0: spdif0@100a0000 {
1179                         compatible = "starfive,jh7110-spdif";
1180                         reg = <0x0 0x100a0000 0x0 0x1000>;
1181                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1182                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1183                                  <&clkgen JH7110_AUDIO_ROOT>,
1184                                  <&clkgen JH7110_MCLK_INNER>;
1185                         clock-names = "spdif-apb", "spdif-core",
1186                                       "audroot", "mclk_inner";
1187                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1188                         reset-names = "rst_apb";
1189                         interrupts = <84>;
1190                         interrupt-names = "tx";
1191                         #sound-dai-cells = <0>;
1192                         status = "disabled";
1193                 };
1194
1195                 pwmdac: pwmdac@100b0000 {
1196                         compatible = "starfive,jh7110-pwmdac";
1197                         reg = <0x0 0x100b0000 0x0 0x1000>;
1198                         clocks = <&clkgen JH7110_APB0>,
1199                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1200                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1201                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1202                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1203                         reset-names = "rst-apb";
1204                         dmas = <&dma 22 1>;
1205                         dma-names = "tx";
1206                         #sound-dai-cells = <0>;
1207                         status = "disabled";
1208                 };
1209
1210                 i2stx: i2stx@100c0000 {
1211                         compatible = "snps,designware-i2stx";
1212                         reg = <0x0 0x100c0000 0x0 0x1000>;
1213                         interrupt-names = "tx";
1214                         #sound-dai-cells = <0>;
1215                         dmas = <&dma 28 1>;
1216                         dma-names = "rx";
1217                         status = "disabled";
1218                 };
1219
1220                 pdm: pdm@100d0000 {
1221                         compatible = "starfive,jh7110-pdm";
1222                         reg = <0x0 0x100d0000 0x0 0x1000>;
1223                         reg-names = "pdm";
1224                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1225                                  <&clkgen JH7110_APB0>,
1226                                  <&clkgen JH7110_PDM_CLK_APB>,
1227                                  <&clkgen JH7110_MCLK_INNER>,
1228                                  <&clkgen JH7110_MCLK>,
1229                                  <&clkgen JH7110_MCLK_OUT>;
1230                         clock-names = "pdm_mclk", "clk_apb0",
1231                                       "pdm_apb", "mclk_inner",
1232                                       "clk_mclk", "mclk_out";
1233                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1234                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1235                         reset-names = "pdm_dmic", "pdm_apb";
1236                         #sound-dai-cells = <0>;
1237                 };
1238
1239                 i2srx_mst: i2srx_mst@100e0000 {
1240                         compatible = "starfive,jh7110-i2srx-master";
1241                         reg = <0x0 0x100e0000 0x0 0x1000>;
1242                         clocks = <&clkgen JH7110_APB0>,
1243                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1244                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1245                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1246                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1247                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1248                         clock-names = "apb0", "i2srx_apb",
1249                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1250                                       "i2srx_bclk", "i2srx_lrck";
1251                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1252                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1253                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1254                         dmas = <&dma 24 1>;
1255                         dma-names = "rx";
1256                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1257                         #sound-dai-cells = <0>;
1258                         status = "disabled";
1259                 };
1260
1261                 i2srx_3ch: i2srx_3ch@100e0000 {
1262                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1263                         reg = <0x0 0x100e0000 0x0 0x1000>;
1264                         clocks = <&clkgen JH7110_APB0>,
1265                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1266                                  <&clkgen JH7110_AUDIO_ROOT>,
1267                                  <&clkgen JH7110_MCLK_INNER>,
1268                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1269                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1270                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1271                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1272                                  <&clkgen JH7110_MCLK>,
1273                                  <&i2srx_bclk_ext>,
1274                                  <&i2srx_lrck_ext>;
1275                         clock-names = "apb0", "3ch-apb",
1276                                       "audioroot", "mclk-inner",
1277                                       "bclk_mst", "3ch-lrck",
1278                                       "rx-bclk", "rx-lrck",
1279                                       "mclk", "bclk-ext",
1280                                       "lrck-ext";
1281                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1282                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1283                         dmas = <&dma 24 1>;
1284                         dma-names = "rx";
1285                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1286                         #sound-dai-cells = <0>;
1287                         status = "disabled";
1288                 };
1289
1290                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1291                         compatible = "snps,designware-i2stx-4ch0";
1292                         reg = <0x0 0x120b0000 0x0 0x1000>;
1293                         clocks = <&clkgen JH7110_MCLK_INNER>,
1294                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1295                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1296                                  <&clkgen JH7110_MCLK>,
1297                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1298                                  <&clkgen JH7110_I2STX0_4CHLRCK>;
1299                         clock-names = "inner", "bclk-mst",
1300                                         "lrck-mst", "mclk",
1301                                         "bclk0", "lrck0";
1302                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1303                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1304                         dmas = <&dma 47 1>;
1305                         dma-names = "tx";
1306                         #sound-dai-cells = <0>;
1307                         status = "disabled";
1308                 };
1309
1310                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1311                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1312                         reg = <0x0 0x120c0000 0x0 0x1000>;
1313                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1314                                  <&clkgen JH7110_MCLK_INNER>,
1315                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1316                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1317                                  <&clkgen JH7110_MCLK>,
1318                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1319                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1320                                  <&clkgen JH7110_MCLK_OUT>,
1321                                  <&clkgen JH7110_APB0>,
1322                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1323                                  <&mclk_ext>,
1324                                  <&i2stx_bclk_ext>,
1325                                  <&i2stx_lrck_ext>;
1326                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1327                                       "lrck_mst", "mclk", "4chbclk",
1328                                       "4chlrck", "mclk_out",
1329                                       "apb0", "clk_apb",
1330                                       "mclk_ext", "bclk_ext", "lrck_ext";
1331                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1332                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1333                         dmas = <&dma 48 1>;
1334                         dma-names = "tx";
1335                         #sound-dai-cells = <0>;
1336                         status = "disabled";
1337                 };
1338
1339                 ptc: pwm@120d0000 {
1340                         compatible = "starfive,jh7110-pwm";
1341                         reg = <0x0 0x120d0000 0x0 0x10000>;
1342                         reg-names = "control";
1343                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1344                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1345                         starfive,approx-freq = <2000000>;
1346                         #pwm-cells=<3>;
1347                         starfive,npwm = <8>;
1348                         status = "disabled";
1349                 };
1350
1351                 spdif_transmitter: spdif_transmitter {
1352                         compatible = "linux,spdif-dit";
1353                         #sound-dai-cells = <0>;
1354                         status = "disabled";
1355                 };
1356
1357                 pwmdac_codec: pwmdac-transmitter {
1358                         compatible = "starfive,jh7110-pwmdac-dit";
1359                         #sound-dai-cells = <0>;
1360                         status = "disabled";
1361                 };
1362
1363                 dmic_codec: dmic_codec {
1364                         compatible = "dmic-codec";
1365                         #sound-dai-cells = <0>;
1366                         status = "disabled";
1367                 };
1368
1369                 spi0: spi@10060000 {
1370                         compatible = "arm,pl022", "arm,primecell";
1371                         reg = <0x0 0x10060000 0x0 0x10000>;
1372                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1373                         clock-names = "apb_pclk";
1374                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1375                         reset-names = "rst_apb";
1376                         interrupts = <38>;
1377                         /* shortage of dma channel that not be used */
1378                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1379                         /*dma-names = "rx","tx";*/
1380                         arm,primecell-periphid = <0x00041022>;
1381                         num-cs = <1>;
1382                         #address-cells = <1>;
1383                         #size-cells = <0>;
1384                         status = "disabled";
1385                 };
1386
1387                 spi1: spi@10070000 {
1388                         compatible = "arm,pl022", "arm,primecell";
1389                         reg = <0x0 0x10070000 0x0 0x10000>;
1390                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1391                         clock-names = "apb_pclk";
1392                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1393                         reset-names = "rst_apb";
1394                         interrupts = <39>;
1395                         /* shortage of dma channel that not be used */
1396                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1397                         /*dma-names = "rx","tx";*/
1398                         arm,primecell-periphid = <0x00041022>;
1399                         num-cs = <1>;
1400                         #address-cells = <1>;
1401                         #size-cells = <0>;
1402                         status = "disabled";
1403                 };
1404
1405                 spi2: spi@10080000 {
1406                         compatible = "arm,pl022", "arm,primecell";
1407                         reg = <0x0 0x10080000 0x0 0x10000>;
1408                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1409                         clock-names = "apb_pclk";
1410                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1411                         reset-names = "rst_apb";
1412                         interrupts = <40>;
1413                         /* shortage of dma channel that not be used */
1414                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1415                         /*dma-names = "rx","tx";*/
1416                         arm,primecell-periphid = <0x00041022>;
1417                         num-cs = <1>;
1418                         #address-cells = <1>;
1419                         #size-cells = <0>;
1420                         status = "disabled";
1421                 };
1422
1423                 spi3: spi@12070000 {
1424                         compatible = "arm,pl022", "arm,primecell";
1425                         reg = <0x0 0x12070000 0x0 0x10000>;
1426                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1427                         clock-names = "apb_pclk";
1428                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1429                         reset-names = "rst_apb";
1430                         interrupts = <52>;
1431                         /* shortage of dma channel that not be used */
1432                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1433                         /*dma-names = "rx","tx";*/
1434                         arm,primecell-periphid = <0x00041022>;
1435                         num-cs = <1>;
1436                         #address-cells = <1>;
1437                         #size-cells = <0>;
1438                         status = "disabled";
1439                 };
1440
1441                 spi4: spi@12080000 {
1442                         compatible = "arm,pl022", "arm,primecell";
1443                         reg = <0x0 0x12080000 0x0 0x10000>;
1444                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1445                         clock-names = "apb_pclk";
1446                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1447                         reset-names = "rst_apb";
1448                         interrupts = <53>;
1449                         /* shortage of dma channel that not be used */
1450                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1451                         /*dma-names = "rx","tx";*/
1452                         arm,primecell-periphid = <0x00041022>;
1453                         num-cs = <1>;
1454                         #address-cells = <1>;
1455                         #size-cells = <0>;
1456                         status = "disabled";
1457                 };
1458
1459                 spi5: spi@12090000 {
1460                         compatible = "arm,pl022", "arm,primecell";
1461                         reg = <0x0 0x12090000 0x0 0x10000>;
1462                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1463                         clock-names = "apb_pclk";
1464                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1465                         reset-names = "rst_apb";
1466                         interrupts = <54>;
1467                         /* shortage of dma channel that not be used */
1468                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1469                         /*dma-names = "rx","tx";*/
1470                         arm,primecell-periphid = <0x00041022>;
1471                         num-cs = <1>;
1472                         #address-cells = <1>;
1473                         #size-cells = <0>;
1474                         status = "disabled";
1475                 };
1476
1477                 spi6: spi@120A0000 {
1478                         compatible = "arm,pl022", "arm,primecell";
1479                         reg = <0x0 0x120A0000 0x0 0x10000>;
1480                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1481                         clock-names = "apb_pclk";
1482                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1483                         reset-names = "rst_apb";
1484                         interrupts = <55>;
1485                         /* shortage of dma channel that not be used */
1486                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1487                         /*dma-names = "rx","tx";*/
1488                         arm,primecell-periphid = <0x00041022>;
1489                         num-cs = <1>;
1490                         #address-cells = <1>;
1491                         #size-cells = <0>;
1492                         status = "disabled";
1493                 };
1494
1495                 pcie0: pcie@2B000000 {
1496                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1497                         #address-cells = <3>;
1498                         #size-cells = <2>;
1499                         #interrupt-cells = <1>;
1500                         reg = <0x0 0x2B000000 0x0 0x1000000
1501                                0x9 0x40000000 0x0 0x10000000>;
1502                         reg-names = "reg", "config";
1503                         device_type = "pci";
1504                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1505                         bus-range = <0x0 0xff>;
1506                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>;
1507                         msi-parent = <&plic>;
1508                         interrupts = <56>;
1509                         interrupt-controller;
1510                         interrupt-names = "msi";
1511                         interrupt-parent = <&plic>;
1512                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1513                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1514                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1515                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1516                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1517                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1518                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1519                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1520                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1521                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1522                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1523                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1524                                       "rst_brg", "rst_core", "rst_apb";
1525                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1526                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1527                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1528                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1529                         clock-names = "noc", "tl", "axi_mst0", "apb";
1530                         status = "disabled";
1531                 };
1532
1533                 pcie1: pcie@2C000000 {
1534                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1535                         #address-cells = <3>;
1536                         #size-cells = <2>;
1537                         #interrupt-cells = <1>;
1538                         reg = <0x0 0x2C000000 0x0 0x1000000
1539                                0x9 0xc0000000 0x0 0x10000000>;
1540                         reg-names = "reg", "config";
1541                         device_type = "pci";
1542                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1543                         bus-range = <0x0 0xff>;
1544                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>;
1545                         msi-parent = <&plic>;
1546                         interrupts = <57>;
1547                         interrupt-controller;
1548                         interrupt-names = "msi";
1549                         interrupt-parent = <&plic>;
1550                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1551                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1552                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1553                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1554                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1555                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1556                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1557                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1558                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1559                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1560                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1561                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1562                                       "rst_brg", "rst_core", "rst_apb";
1563                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1564                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1565                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1566                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1567                         clock-names = "noc", "tl", "axi_mst0", "apb";
1568                         status = "disabled";
1569                 };
1570
1571                 mailbox_contrl0: mailbox@0 {
1572                         compatible = "starfive,mail_box";
1573                         reg = <0x0 0x13060000 0x0 0x0001000>;
1574                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1575                         clock-names = "clk_apb";
1576                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1577                         reset-names = "mbx_rre";
1578                         interrupts = <26 27>;
1579                         #mbox-cells = <2>;
1580                         status = "disabled";
1581                 };
1582
1583                 mailbox_client0: mailbox_client@0 {
1584                         compatible = "starfive,mailbox-test";
1585                         mbox-names = "rx", "tx";
1586                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1587                         status = "disabled";
1588                 };
1589
1590                 display: display-subsystem {
1591                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1592                         ports = <&dc_out_dpi0>;
1593                         status = "disabled";
1594                 };
1595
1596                 dssctrl: dssctrl@295B0000 {
1597                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1598                         reg = <0 0x295B0000 0 0x90>;
1599                 };
1600
1601                 tda988x_pin: tda988x_pin {
1602                         compatible = "starfive,tda998x_rgb_pin";
1603                         status = "disabled";
1604                 };
1605
1606                 rgb_output: rgb-output {
1607                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1608                         //verisilicon,dss-syscon = <&dssctrl>;
1609                         //verisilicon,mux-mask = <0x70 0x380>;
1610                         //verisilicon,mux-val = <0x40 0x280>;
1611                         status = "disabled";
1612                 };
1613
1614                 dc8200: dc8200@29400000 {
1615                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1616                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1617                         reg = <0x0 0x29400000 0x0 0x100>,
1618                               <0x0 0x29400800 0x0 0x2000>,
1619                               <0x0 0x17030000 0x0 0x1000>;
1620                         interrupts = <95>;
1621                         status = "disabled";
1622                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1623                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1624                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1625                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1626                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1627                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1628                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1629                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1630                                  <&clkgen JH7110_VOUT_SRC>,
1631                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1632                                  <&clkgen JH7110_AHB1>,
1633                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1634                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1635                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1636                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1637                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1638                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1639                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1640                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1641                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1642                                  <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1643                                  <&hdmitx0_pixelclk>,
1644                                  <&clkvout JH7110_DC8200_PIX0>,
1645                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1646                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1647                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1648                                         "noc_disp","noc_isp","noc_stg","vout_src",
1649                                         "top_vout_axi","ahb1","top_vout_ahb",
1650                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1651                                         "axi_clk","core_clk","vout_ahb",
1652                                         "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1653                                         "dc8200_pix0_out","dc8200_pix1_out";
1654                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1655                                  <&rstgen RSTN_U0_DC8200_AXI>,
1656                                  <&rstgen RSTN_U0_DC8200_AHB>,
1657                                  <&rstgen RSTN_U0_DC8200_CORE>,
1658                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1659                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1660                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1661                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1662                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1663                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1664                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1665                                         "rst_noc_disp","rst_noc_stg";
1666                         power-domains = <&pwrc JH7110_PD_VOUT>;
1667                 };
1668
1669                 dsi_output: dsi-output {
1670                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1671                         status = "disabled";
1672                 };
1673
1674                 mipi_dphy: mipi-dphy@295e0000{
1675                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1676                         reg = <0x0 0x295e0000 0x0 0x10000>;
1677                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1678                         clock-names = "dphy_txesc";
1679                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1680                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1681                         reset-names = "dphy_sys", "dphy_txbytehs";
1682                         #phy-cells = <0>;
1683                         status = "disabled";
1684                 };
1685
1686                  mipi_dsi: mipi@295d0000 {
1687                         compatible = "starfive,jh7100-mipi_dsi","cdns,dsi";
1688                         reg = <0x0 0x295d0000 0x0 0x10000>;
1689                         interrupts = <98>;
1690                         reg-names = "dsi";
1691                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1692                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1693                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1694                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1695                         clock-names = "sys", "apb", "txesc", "dpi";
1696                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1697                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1698                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1699                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1700                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1701                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1702                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1703                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1704                         phys = <&mipi_dphy>;
1705                         phy-names = "dphy";
1706                         status = "disabled";
1707
1708                         port {
1709                                 dsi_out_port: endpoint@0 {
1710                                         remote-endpoint = <&panel_dsi_port>;
1711                                 };
1712                                 dsi_in_port: endpoint@1 {
1713                                         remote-endpoint = <&mipi_out>;
1714                                 };
1715                         };
1716
1717                         mipi_panel: panel@0 {
1718                                 /*compatible = "";*/
1719                                 status = "okay";
1720                         };
1721                 };
1722
1723                 hdmi: hdmi@29590000 {
1724                         compatible = "starfive,jh7100-hdmi","inno,hdmi";
1725                         reg = <0x0 0x29590000 0x0 0x4000>;
1726                         interrupts = <99>;
1727                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1728                         /*clocks = <&cru  PCLK_HDMI>;*/
1729                         /*clock-names = "pclk";*/
1730                         /*pinctrl-names = "default";*/
1731                         /*pinctrl-0 = <&hdmi_ctl>;*/
1732                         status = "disabled";
1733                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1734                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1735                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1736                                  <&hdmitx0_pixelclk>;
1737                         clock-names = "sysclk", "mclk","bclk","pclk";
1738                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1739                         reset-names = "hdmi_tx";
1740                 };
1741
1742                 sound: snd-card {
1743                         compatible = "simple-audio-card";
1744                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1745                         #address-cells = <1>;
1746                         #size-cells = <0>;
1747                 };
1748
1749                 co_process: e24@0 {
1750                         compatible = "starfive,e24";
1751                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1752                                 <0x0 0xc0111000 0x0 0x0001f000>;
1753                         reg-names = "ecmd", "espace";
1754                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1755                                  <&clkgen JH7110_E2_CLK_CORE>,
1756                                  <&clkgen JH7110_E2_CLK_DBG>;
1757                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1758                         resets = <&rstgen RSTN_U0_E24_CORE>;
1759                         reset-names = "e24_core";
1760                         starfive,stg-syscon = <&stg_syscon>;
1761                         interrupt-parent = <&plic>;
1762                         firmware-name = "e24_elf";
1763                         irq-mode = <1>;
1764                         mbox-names = "tx", "rx";
1765                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1766                         #address-cells = <1>;
1767                         #size-cells = <1>;
1768                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1769                         status = "disabled";
1770                         dsp@0 {};
1771                 };
1772
1773                 xrp: xrp@0 {
1774                         compatible = "cdns,xrp";
1775                         reg = <0x0  0x10230000 0x0 0x00010000
1776                                 0x0  0x10240000 0x0 0x00010000>;
1777                         memory-region = <&xrp_reserved>;
1778                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1779                         clock-names = "core_clk";
1780                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1781                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1782                         reset-names = "rst_core","rst_axi";
1783                         starfive,stg-syscon = <&stg_syscon>;
1784                         firmware-name = "hifi4_elf";
1785                         #address-cells = <1>;
1786                         #size-cells = <1>;
1787                         ranges = <0x40000000 0x0 0x20000000 0x040000
1788                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1789                         status = "disabled";
1790                         dsp@0 {
1791                         };
1792                 };
1793
1794                 starfive_cpufreq: starfive,jh7110-cpufreq {
1795                         compatible = "starfive,jh7110-cpufreq";
1796                         clocks = <&clkgen JH7110_PLL0_OUT>,
1797                                          <&clkgen JH7110_CPU_ROOT>,
1798                                          <&osc>;
1799                         clock-names = "pll0", "cpu_clk", "osc";
1800                 };
1801         };
1802 };