arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
   9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
  10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
  11
  12 / {
  13         compatible = "starfive,jh7110";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 S7_0: cpu@0 {
  22                         compatible = "sifive,s7", "riscv";
  23                         reg = <0>;
  24                         d-cache-block-size = <64>;
  25                         d-cache-sets = <64>;
  26                         d-cache-size = <8192>;
  27                         d-tlb-sets = <1>;
  28                         d-tlb-size = <40>;
  29                         device_type = "cpu";
  30                         i-cache-block-size = <64>;
  31                         i-cache-sets = <64>;
  32                         i-cache-size = <16384>;
  33                         i-tlb-sets = <1>;
  34                         i-tlb-size = <40>;
  35                         mmu-type = "riscv,sv39";
  36                         next-level-cache = <&ccache>;
  37                         riscv,isa = "rv64imac_zba_zbb";
  38                         tlb-split;
  39                         status = "disabled";
  40
  41                         cpu0_intc: interrupt-controller {
  42                                 compatible = "riscv,cpu-intc";
  43                                 interrupt-controller;
  44                                 #interrupt-cells = <1>;
  45                         };
  46                 };
  47
  48                 U74_1: cpu@1 {
  49                         compatible = "sifive,u74-mc", "riscv";
  50                         reg = <1>;
  51                         d-cache-block-size = <64>;
  52                         d-cache-sets = <64>;
  53                         d-cache-size = <32768>;
  54                         d-tlb-sets = <1>;
  55                         d-tlb-size = <40>;
  56                         device_type = "cpu";
  57                         i-cache-block-size = <64>;
  58                         i-cache-sets = <64>;
  59                         i-cache-size = <32768>;
  60                         i-tlb-sets = <1>;
  61                         i-tlb-size = <40>;
  62                         mmu-type = "riscv,sv39";
  63                         next-level-cache = <&ccache>;
  64                         riscv,isa = "rv64imafdc_zba_zbb";
  65                         tlb-split;
  66
  67                         cpu1_intc: interrupt-controller {
  68                                 compatible = "riscv,cpu-intc";
  69                                 interrupt-controller;
  70                                 #interrupt-cells = <1>;
  71                         };
  72                 };
  73
  74                 U74_2: cpu@2 {
  75                         compatible = "sifive,u74-mc", "riscv";
  76                         reg = <2>;
  77                         d-cache-block-size = <64>;
  78                         d-cache-sets = <64>;
  79                         d-cache-size = <32768>;
  80                         d-tlb-sets = <1>;
  81                         d-tlb-size = <40>;
  82                         device_type = "cpu";
  83                         i-cache-block-size = <64>;
  84                         i-cache-sets = <64>;
  85                         i-cache-size = <32768>;
  86                         i-tlb-sets = <1>;
  87                         i-tlb-size = <40>;
  88                         mmu-type = "riscv,sv39";
  89                         next-level-cache = <&ccache>;
  90                         riscv,isa = "rv64imafdc_zba_zbb";
  91                         tlb-split;
  92
  93                         cpu2_intc: interrupt-controller {
  94                                 compatible = "riscv,cpu-intc";
  95                                 interrupt-controller;
  96                                 #interrupt-cells = <1>;
  97                         };
  98                 };
  99
 100                 U74_3: cpu@3 {
 101                         compatible = "sifive,u74-mc", "riscv";
 102                         reg = <3>;
 103                         d-cache-block-size = <64>;
 104                         d-cache-sets = <64>;
 105                         d-cache-size = <32768>;
 106                         d-tlb-sets = <1>;
 107                         d-tlb-size = <40>;
 108                         device_type = "cpu";
 109                         i-cache-block-size = <64>;
 110                         i-cache-sets = <64>;
 111                         i-cache-size = <32768>;
 112                         i-tlb-sets = <1>;
 113                         i-tlb-size = <40>;
 114                         mmu-type = "riscv,sv39";
 115                         next-level-cache = <&ccache>;
 116                         riscv,isa = "rv64imafdc_zba_zbb";
 117                         tlb-split;
 118
 119                         cpu3_intc: interrupt-controller {
 120                                 compatible = "riscv,cpu-intc";
 121                                 interrupt-controller;
 122                                 #interrupt-cells = <1>;
 123                         };
 124                 };
 125
 126                 U74_4: cpu@4 {
 127                         compatible = "sifive,u74-mc", "riscv";
 128                         reg = <4>;
 129                         d-cache-block-size = <64>;
 130                         d-cache-sets = <64>;
 131                         d-cache-size = <32768>;
 132                         d-tlb-sets = <1>;
 133                         d-tlb-size = <40>;
 134                         device_type = "cpu";
 135                         i-cache-block-size = <64>;
 136                         i-cache-sets = <64>;
 137                         i-cache-size = <32768>;
 138                         i-tlb-sets = <1>;
 139                         i-tlb-size = <40>;
 140                         mmu-type = "riscv,sv39";
 141                         next-level-cache = <&ccache>;
 142                         riscv,isa = "rv64imafdc_zba_zbb";
 143                         tlb-split;
 144
 145                         cpu4_intc: interrupt-controller {
 146                                 compatible = "riscv,cpu-intc";
 147                                 interrupt-controller;
 148                                 #interrupt-cells = <1>;
 149                         };
 150                 };
 151
 152                 cpu-map {
 153                         cluster0 {
 154                                 core0 {
 155                                         cpu = <&S7_0>;
 156                                 };
 157
 158                                 core1 {
 159                                         cpu = <&U74_1>;
 160                                 };
 161
 162                                 core2 {
 163                                         cpu = <&U74_2>;
 164                                 };
 165
 166                                 core3 {
 167                                         cpu = <&U74_3>;
 168                                 };
 169
 170                                 core4 {
 171                                         cpu = <&U74_4>;
 172                                 };
 173                         };
 174                 };
 175         };
 176
 177         dvp_clk: dvp-clock {
 178                 compatible = "fixed-clock";
 179                 clock-output-names = "dvp_clk";
 180                 #clock-cells = <0>;
 181         };
 182
 183         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 184                 compatible = "fixed-clock";
 185                 clock-output-names = "gmac0_rgmii_rxin";
 186                 #clock-cells = <0>;
 187         };
 188
 189         gmac0_rmii_refin: gmac0-rmii-refin-clock {
 190                 compatible = "fixed-clock";
 191                 clock-output-names = "gmac0_rmii_refin";
 192                 #clock-cells = <0>;
 193         };
 194
 195         gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 196                 compatible = "fixed-clock";
 197                 clock-output-names = "gmac1_rgmii_rxin";
 198                 #clock-cells = <0>;
 199         };
 200
 201         gmac1_rmii_refin: gmac1-rmii-refin-clock {
 202                 compatible = "fixed-clock";
 203                 clock-output-names = "gmac1_rmii_refin";
 204                 #clock-cells = <0>;
 205         };
 206
 207         hdmitx0_pixelclk: hdmitx0-pixel-clock {
 208                 compatible = "fixed-clock";
 209                 clock-output-names = "hdmitx0_pixelclk";
 210                 #clock-cells = <0>;
 211         };
 212
 213         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 214                 compatible = "fixed-clock";
 215                 clock-output-names = "i2srx_bclk_ext";
 216                 #clock-cells = <0>;
 217         };
 218
 219         i2srx_lrck_ext: i2srx-lrck-ext-clock {
 220                 compatible = "fixed-clock";
 221                 clock-output-names = "i2srx_lrck_ext";
 222                 #clock-cells = <0>;
 223         };
 224
 225         i2stx_bclk_ext: i2stx-bclk-ext-clock {
 226                 compatible = "fixed-clock";
 227                 clock-output-names = "i2stx_bclk_ext";
 228                 #clock-cells = <0>;
 229         };
 230
 231         i2stx_lrck_ext: i2stx-lrck-ext-clock {
 232                 compatible = "fixed-clock";
 233                 clock-output-names = "i2stx_lrck_ext";
 234                 #clock-cells = <0>;
 235         };
 236
 237         mclk_ext: mclk-ext-clock {
 238                 compatible = "fixed-clock";
 239                 clock-output-names = "mclk_ext";
 240                 #clock-cells = <0>;
 241         };
 242
 243         osc: oscillator {
 244                 compatible = "fixed-clock";
 245                 clock-output-names = "osc";
 246                 #clock-cells = <0>;
 247         };
 248
 249         rtc_osc: rtc-oscillator {
 250                 compatible = "fixed-clock";
 251                 clock-output-names = "rtc_osc";
 252                 #clock-cells = <0>;
 253         };
 254
 255         stmmac_axi_setup: stmmac-axi-config {
 256                 snps,lpi_en;
 257                 snps,wr_osr_lmt = <4>;
 258                 snps,rd_osr_lmt = <4>;
 259                 snps,blen = <256 128 64 32 0 0 0>;
 260         };
 261
 262         tdm_ext: tdm-ext-clock {
 263                 compatible = "fixed-clock";
 264                 clock-output-names = "tdm_ext";
 265                 #clock-cells = <0>;
 266         };
 267
 268         soc {
 269                 compatible = "simple-bus";
 270                 interrupt-parent = <&plic>;
 271                 #address-cells = <2>;
 272                 #size-cells = <2>;
 273                 ranges;
 274
 275                 clint: timer@2000000 {
 276                         compatible = "starfive,jh7110-clint", "sifive,clint0";
 277                         reg = <0x0 0x2000000 0x0 0x10000>;
 278                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 279                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 280                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 281                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 282                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 283                 };
 284
 285                 ccache: cache-controller@2010000 {
 286                         compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
 287                         reg = <0x0 0x2010000 0x0 0x4000>;
 288                         interrupts = <1>, <3>, <4>, <2>;
 289                         cache-block-size = <64>;
 290                         cache-level = <2>;
 291                         cache-sets = <2048>;
 292                         cache-size = <2097152>;
 293                         cache-unified;
 294                 };
 295
 296                 plic: interrupt-controller@c000000 {
 297                         compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 298                         reg = <0x0 0xc000000 0x0 0x4000000>;
 299                         interrupts-extended = <&cpu0_intc 11>,
 300                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 301                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 302                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 303                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 304                         interrupt-controller;
 305                         #interrupt-cells = <1>;
 306                         #address-cells = <0>;
 307                         riscv,ndev = <136>;
 308                 };
 309
 310                 uart0: serial@10000000 {
 311                         compatible = "snps,dw-apb-uart";
 312                         reg = <0x0 0x10000000 0x0 0x10000>;
 313                         clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
 314                                  <&syscrg JH7110_SYSCLK_UART0_APB>;
 315                         clock-names = "baudclk", "apb_pclk";
 316                         resets = <&syscrg JH7110_SYSRST_UART0_APB>;
 317                         interrupts = <32>;
 318                         reg-io-width = <4>;
 319                         reg-shift = <2>;
 320                         status = "disabled";
 321                 };
 322
 323                 uart1: serial@10010000 {
 324                         compatible = "snps,dw-apb-uart";
 325                         reg = <0x0 0x10010000 0x0 0x10000>;
 326                         clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
 327                                  <&syscrg JH7110_SYSCLK_UART1_APB>;
 328                         clock-names = "baudclk", "apb_pclk";
 329                         resets = <&syscrg JH7110_SYSRST_UART1_APB>;
 330                         interrupts = <33>;
 331                         reg-io-width = <4>;
 332                         reg-shift = <2>;
 333                         status = "disabled";
 334                 };
 335
 336                 uart2: serial@10020000 {
 337                         compatible = "snps,dw-apb-uart";
 338                         reg = <0x0 0x10020000 0x0 0x10000>;
 339                         clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
 340                                  <&syscrg JH7110_SYSCLK_UART2_APB>;
 341                         clock-names = "baudclk", "apb_pclk";
 342                         resets = <&syscrg JH7110_SYSRST_UART2_APB>;
 343                         interrupts = <34>;
 344                         reg-io-width = <4>;
 345                         reg-shift = <2>;
 346                         status = "disabled";
 347                 };
 348
 349                 i2c0: i2c@10030000 {
 350                         compatible = "snps,designware-i2c";
 351                         reg = <0x0 0x10030000 0x0 0x10000>;
 352                         clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
 353                         clock-names = "ref";
 354                         resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
 355                         interrupts = <35>;
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         status = "disabled";
 359                 };
 360
 361                 i2c1: i2c@10040000 {
 362                         compatible = "snps,designware-i2c";
 363                         reg = <0x0 0x10040000 0x0 0x10000>;
 364                         clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
 365                         clock-names = "ref";
 366                         resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
 367                         interrupts = <36>;
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                         status = "disabled";
 371                 };
 372
 373                 i2c2: i2c@10050000 {
 374                         compatible = "snps,designware-i2c";
 375                         reg = <0x0 0x10050000 0x0 0x10000>;
 376                         clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
 377                         clock-names = "ref";
 378                         resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
 379                         interrupts = <37>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         status = "disabled";
 383                 };
 384
 385                 usb0: usb@10100000 {
 386                         compatible = "starfive,jh7110-usb";
 387                         clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
 388                                  <&stgcrg JH7110_STGCLK_USB0_STB>,
 389                                  <&stgcrg JH7110_STGCLK_USB0_APB>,
 390                                  <&stgcrg JH7110_STGCLK_USB0_AXI>,
 391                                  <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
 392                         clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
 393                         resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
 394                                  <&stgcrg JH7110_STGRST_USB0_APB>,
 395                                  <&stgcrg JH7110_STGRST_USB0_AXI>,
 396                                  <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
 397                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 398                         starfive,sys-syscon = <&sys_syscon 0x18>;
 399                         status = "disabled";
 400                         #address-cells = <1>;
 401                         #size-cells = <1>;
 402                         ranges = <0x0 0x0 0x10100000 0x100000>;
 403
 404                         usbdrd_cdns3: usb@0 {
 405                                 compatible = "cdns,usb3";
 406                                 reg = <0x0 0x10000>,
 407                                       <0x10000 0x10000>,
 408                                       <0x20000 0x10000>;
 409                                 reg-names = "otg", "xhci", "dev";
 410                                 interrupts = <100>, <108>, <110>;
 411                                 interrupt-names = "host", "peripheral", "otg";
 412                                 phys = <&usbphy0>;
 413                                 phy-names = "cdns3,usb2-phy";
 414                                 maximum-speed = "super-speed";
 415                         };
 416                 };
 417
 418                 usbphy0: phy@10200000 {
 419                         compatible = "starfive,jh7110-usb-phy";
 420                         reg = <0x0 0x10200000 0x0 0x10000>;
 421                         clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
 422                                  <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 423                         clock-names = "125m", "app_125";
 424                         #phy-cells = <0>;
 425                 };
 426
 427                 pciephy0: phy@10210000 {
 428                         compatible = "starfive,jh7110-pcie-phy";
 429                         reg = <0x0 0x10210000 0x0 0x10000>;
 430                         #phy-cells = <0>;
 431                 };
 432
 433                 pciephy1: phy@10220000 {
 434                         compatible = "starfive,jh7110-pcie-phy";
 435                         reg = <0x0 0x10220000 0x0 0x10000>;
 436                         #phy-cells = <0>;
 437                 };
 438
 439                 stgcrg: clock-controller@10230000 {
 440                         compatible = "starfive,jh7110-stgcrg";
 441                         reg = <0x0 0x10230000 0x0 0x10000>;
 442                         clocks = <&osc>,
 443                                  <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
 444                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 445                                  <&syscrg JH7110_SYSCLK_USB_125M>,
 446                                  <&syscrg JH7110_SYSCLK_CPU_BUS>,
 447                                  <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
 448                                  <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
 449                                  <&syscrg JH7110_SYSCLK_APB_BUS>;
 450                         clock-names = "osc", "hifi4_core",
 451                                       "stg_axiahb", "usb_125m",
 452                                       "cpu_bus", "hifi4_axi",
 453                                       "nocstg_bus", "apb_bus";
 454                         #clock-cells = <1>;
 455                         #reset-cells = <1>;
 456                 };
 457
 458                 stg_syscon: syscon@10240000 {
 459                         compatible = "starfive,jh7110-stg-syscon", "syscon";
 460                         reg = <0x0 0x10240000 0x0 0x1000>;
 461                 };
 462
 463                 uart3: serial@12000000 {
 464                         compatible = "snps,dw-apb-uart";
 465                         reg = <0x0 0x12000000 0x0 0x10000>;
 466                         clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
 467                                  <&syscrg JH7110_SYSCLK_UART3_APB>;
 468                         clock-names = "baudclk", "apb_pclk";
 469                         resets = <&syscrg JH7110_SYSRST_UART3_APB>;
 470                         interrupts = <45>;
 471                         reg-io-width = <4>;
 472                         reg-shift = <2>;
 473                         status = "disabled";
 474                 };
 475
 476                 uart4: serial@12010000 {
 477                         compatible = "snps,dw-apb-uart";
 478                         reg = <0x0 0x12010000 0x0 0x10000>;
 479                         clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
 480                                  <&syscrg JH7110_SYSCLK_UART4_APB>;
 481                         clock-names = "baudclk", "apb_pclk";
 482                         resets = <&syscrg JH7110_SYSRST_UART4_APB>;
 483                         interrupts = <46>;
 484                         reg-io-width = <4>;
 485                         reg-shift = <2>;
 486                         status = "disabled";
 487                 };
 488
 489                 uart5: serial@12020000 {
 490                         compatible = "snps,dw-apb-uart";
 491                         reg = <0x0 0x12020000 0x0 0x10000>;
 492                         clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
 493                                  <&syscrg JH7110_SYSCLK_UART5_APB>;
 494                         clock-names = "baudclk", "apb_pclk";
 495                         resets = <&syscrg JH7110_SYSRST_UART5_APB>;
 496                         interrupts = <47>;
 497                         reg-io-width = <4>;
 498                         reg-shift = <2>;
 499                         status = "disabled";
 500                 };
 501
 502                 i2c3: i2c@12030000 {
 503                         compatible = "snps,designware-i2c";
 504                         reg = <0x0 0x12030000 0x0 0x10000>;
 505                         clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
 506                         clock-names = "ref";
 507                         resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
 508                         interrupts = <48>;
 509                         #address-cells = <1>;
 510                         #size-cells = <0>;
 511                         status = "disabled";
 512                 };
 513
 514                 i2c4: i2c@12040000 {
 515                         compatible = "snps,designware-i2c";
 516                         reg = <0x0 0x12040000 0x0 0x10000>;
 517                         clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
 518                         clock-names = "ref";
 519                         resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
 520                         interrupts = <49>;
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         status = "disabled";
 524                 };
 525
 526                 i2c5: i2c@12050000 {
 527                         compatible = "snps,designware-i2c";
 528                         reg = <0x0 0x12050000 0x0 0x10000>;
 529                         clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
 530                         clock-names = "ref";
 531                         resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
 532                         interrupts = <50>;
 533                         #address-cells = <1>;
 534                         #size-cells = <0>;
 535                         status = "disabled";
 536                 };
 537
 538                 i2c6: i2c@12060000 {
 539                         compatible = "snps,designware-i2c";
 540                         reg = <0x0 0x12060000 0x0 0x10000>;
 541                         clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
 542                         clock-names = "ref";
 543                         resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
 544                         interrupts = <51>;
 545                         #address-cells = <1>;
 546                         #size-cells = <0>;
 547                         status = "disabled";
 548                 };
 549
 550                 ptc: pwm@120d0000 {
 551                         compatible = "starfive,jh7110-pwm";
 552                         reg = <0x0 0x120d0000 0x0 0x10000>;
 553                         clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
 554                         resets = <&syscrg JH7110_SYSRST_PWM_APB>;
 555                         #pwm-cells=<3>;
 556                         status = "disabled";
 557                 };
 558
 559                 sfctemp: temperature-sensor@120e0000 {
 560                         compatible = "starfive,jh7110-temp";
 561                         reg = <0x0 0x120e0000 0x0 0x10000>;
 562                         clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
 563                                  <&syscrg JH7110_SYSCLK_TEMP_APB>;
 564                         clock-names = "sense", "bus";
 565                         resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
 566                                  <&syscrg JH7110_SYSRST_TEMP_APB>;
 567                         reset-names = "sense", "bus";
 568                         #thermal-sensor-cells = <0>;
 569                 };
 570
 571                 qspi: spi@13010000 {
 572                         compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
 573                         #address-cells = <1>;
 574                         #size-cells = <0>;
 575                         reg = <0x0 0x13010000 0x0 0x10000
 576                                0x0 0x21000000 0x0 0x400000>;
 577                         interrupts = <25>;
 578                         clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
 579                         resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 580                                  <&syscrg JH7110_SYSRST_QSPI_AHB>,
 581                                  <&syscrg JH7110_SYSRST_QSPI_REF>;
 582                         reset-names = "qspi", "qspi-ocp", "rstc_ref";
 583                         cdns,fifo-depth = <256>;
 584                         cdns,fifo-width = <4>;
 585                         cdns,trigger-address = <0x0>;
 586
 587                         nor_flash: nor-flash@0 {
 588                                 compatible = "jedec,spi-nor";
 589                                 reg=<0>;
 590                                 cdns,read-delay = <5>;
 591                                 spi-max-frequency = <12000000>;
 592                                 cdns,tshsl-ns = <1>;
 593                                 cdns,tsd2d-ns = <1>;
 594                                 cdns,tchsh-ns = <1>;
 595                                 cdns,tslch-ns = <1>;
 596
 597                                 partitions {
 598                                         compatible = "fixed-partitions";
 599                                         #address-cells = <1>;
 600                                         #size-cells = <1>;
 601
 602                                         spl@0 {
 603                                                 reg = <0x0 0x20000>;
 604                                         };
 605                                         uboot@100000 {
 606                                                 reg = <0x100000 0x300000>;
 607                                         };
 608                                         data@f00000 {
 609                                                 reg = <0xf00000 0x100000>;
 610                                         };
 611                                 };
 612                         };
 613                 };
 614
 615                 syscrg: clock-controller@13020000 {
 616                         compatible = "starfive,jh7110-syscrg";
 617                         reg = <0x0 0x13020000 0x0 0x10000>;
 618                         clocks = <&osc>, <&gmac1_rmii_refin>,
 619                                  <&gmac1_rgmii_rxin>,
 620                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 621                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 622                                  <&tdm_ext>, <&mclk_ext>,
 623                                  <&pllclk JH7110_CLK_PLL0_OUT>,
 624                                  <&pllclk JH7110_CLK_PLL1_OUT>,
 625                                  <&pllclk JH7110_CLK_PLL2_OUT>;
 626                         clock-names = "osc", "gmac1_rmii_refin",
 627                                       "gmac1_rgmii_rxin",
 628                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
 629                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
 630                                       "tdm_ext", "mclk_ext",
 631                                       "pll0_out", "pll1_out", "pll2_out";
 632                         #clock-cells = <1>;
 633                         #reset-cells = <1>;
 634                 };
 635
 636                 sys_syscon: syscon@13030000 {
 637                         compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 638                         reg = <0x0 0x13030000 0x0 0x1000>;
 639
 640                         pllclk: pll-clock-controller {
 641                                 compatible = "starfive,jh7110-pll";
 642                                 clocks = <&osc>;
 643                                 #clock-cells = <1>;
 644                         };
 645                 };
 646
 647                 sysgpio: pinctrl@13040000 {
 648                         compatible = "starfive,jh7110-sys-pinctrl";
 649                         reg = <0x0 0x13040000 0x0 0x10000>;
 650                         clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
 651                         resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
 652                         interrupts = <86>;
 653                         interrupt-controller;
 654                         #interrupt-cells = <2>;
 655                         gpio-controller;
 656                         #gpio-cells = <2>;
 657                 };
 658
 659                 timer@13050000 {
 660                         compatible = "starfive,jh7110-timer";
 661                         reg = <0x0 0x13050000 0x0 0x10000>;
 662                         interrupts = <69>, <70>, <71> ,<72>;
 663                         clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
 664                                  <&syscrg JH7110_SYSCLK_TIMER0>,
 665                                  <&syscrg JH7110_SYSCLK_TIMER1>,
 666                                  <&syscrg JH7110_SYSCLK_TIMER2>,
 667                                  <&syscrg JH7110_SYSCLK_TIMER3>;
 668                         clock-names = "apb", "ch0", "ch1",
 669                                       "ch2", "ch3";
 670                         resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
 671                                  <&syscrg JH7110_SYSRST_TIMER0>,
 672                                  <&syscrg JH7110_SYSRST_TIMER1>,
 673                                  <&syscrg JH7110_SYSRST_TIMER2>,
 674                                  <&syscrg JH7110_SYSRST_TIMER3>;
 675                         reset-names = "apb", "ch0", "ch1",
 676                                       "ch2", "ch3";
 677                 };
 678
 679                 wdog: watchdog@13070000 {
 680                         compatible = "starfive,jh7110-wdt";
 681                         reg = <0x0 0x13070000 0x0 0x10000>;
 682                         clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
 683                                  <&syscrg JH7110_SYSCLK_WDT_CORE>;
 684                         clock-names = "apb", "core";
 685                         resets = <&syscrg JH7110_SYSRST_WDT_APB>,
 686                                  <&syscrg JH7110_SYSRST_WDT_CORE>;
 687                 };
 688
 689                 crypto: crypto@16000000 {
 690                         compatible = "starfive,jh7110-crypto";
 691                         reg = <0x0 0x16000000 0x0 0x4000>;
 692                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 693                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 694                         clock-names = "hclk", "ahb";
 695                         interrupts = <28>;
 696                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 697                         dmas = <&sdma 1 2>, <&sdma 0 2>;
 698                         dma-names = "tx", "rx";
 699                 };
 700
 701                 sdma: dma@16008000 {
 702                         compatible = "arm,pl080", "arm,primecell";
 703                         arm,primecell-periphid = <0x00041080>;
 704                         reg = <0x0 0x16008000 0x0 0x4000>;
 705                         interrupts = <29>;
 706                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 707                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 708                         clock-names = "hclk", "apb_pclk";
 709                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 710                         lli-bus-interface-ahb1;
 711                         mem-bus-interface-ahb1;
 712                         memcpy-burst-size = <256>;
 713                         memcpy-bus-width = <32>;
 714                         #dma-cells = <2>;
 715                 };
 716
 717                 rng: rng@1600c000 {
 718                         compatible = "starfive,jh7110-trng";
 719                         reg = <0x0 0x1600C000 0x0 0x4000>;
 720                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 721                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 722                         clock-names = "hclk", "ahb";
 723                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 724                         interrupts = <30>;
 725                 };
 726
 727                 mmc0: mmc@16010000 {
 728                         compatible = "starfive,jh7110-mmc";
 729                         reg = <0x0 0x16010000 0x0 0x10000>;
 730                         clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 731                                  <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 732                         clock-names = "biu","ciu";
 733                         resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 734                         reset-names = "reset";
 735                         interrupts = <74>;
 736                         fifo-depth = <32>;
 737                         fifo-watermark-aligned;
 738                         data-addr = <0>;
 739                         starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 740                         status = "disabled";
 741                 };
 742
 743                 mmc1: mmc@16020000 {
 744                         compatible = "starfive,jh7110-mmc";
 745                         reg = <0x0 0x16020000 0x0 0x10000>;
 746                         clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 747                                  <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 748                         clock-names = "biu","ciu";
 749                         resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 750                         reset-names = "reset";
 751                         interrupts = <75>;
 752                         fifo-depth = <32>;
 753                         fifo-watermark-aligned;
 754                         data-addr = <0>;
 755                         starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 756                         status = "disabled";
 757                 };
 758
 759                 gmac0: ethernet@16030000 {
 760                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 761                         reg = <0x0 0x16030000 0x0 0x10000>;
 762                         clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
 763                                  <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
 764                                  <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
 765                                  <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
 766                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
 767                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 768                                       "tx", "gtx";
 769                         resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
 770                                  <&aoncrg JH7110_AONRST_GMAC0_AHB>;
 771                         reset-names = "stmmaceth", "ahb";
 772                         interrupts = <7>, <6>, <5>;
 773                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 774                         snps,multicast-filter-bins = <64>;
 775                         snps,perfect-filter-entries = <8>;
 776                         rx-fifo-depth = <2048>;
 777                         tx-fifo-depth = <2048>;
 778                         snps,fixed-burst;
 779                         snps,no-pbl-x8;
 780                         snps,force_thresh_dma_mode;
 781                         snps,axi-config = <&stmmac_axi_setup>;
 782                         snps,tso;
 783                         snps,en-tx-lpi-clockgating;
 784                         snps,txpbl = <16>;
 785                         snps,rxpbl = <16>;
 786                         starfive,syscon = <&aon_syscon 0xc 0x12>;
 787                         status = "disabled";
 788                 };
 789
 790                 gmac1: ethernet@16040000 {
 791                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 792                         reg = <0x0 0x16040000 0x0 0x10000>;
 793                         clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
 794                                  <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
 795                                  <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
 796                                  <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
 797                                  <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
 798                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 799                                       "tx", "gtx";
 800                         resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
 801                                  <&syscrg JH7110_SYSRST_GMAC1_AHB>;
 802                         reset-names = "stmmaceth", "ahb";
 803                         interrupts = <78>, <77>, <76>;
 804                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 805                         snps,multicast-filter-bins = <64>;
 806                         snps,perfect-filter-entries = <8>;
 807                         rx-fifo-depth = <2048>;
 808                         tx-fifo-depth = <2048>;
 809                         snps,fixed-burst;
 810                         snps,no-pbl-x8;
 811                         snps,force_thresh_dma_mode;
 812                         snps,axi-config = <&stmmac_axi_setup>;
 813                         snps,tso;
 814                         snps,en-tx-lpi-clockgating;
 815                         snps,txpbl = <16>;
 816                         snps,rxpbl = <16>;
 817                         starfive,syscon = <&sys_syscon 0x90 0x2>;
 818                         status = "disabled";
 819                 };
 820
 821                 dma: dma-controller@16050000 {
 822                         compatible = "starfive,jh7110-axi-dma";
 823                         reg = <0x0 0x16050000 0x0 0x10000>;
 824                         clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
 825                                  <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
 826                         clock-names = "core-clk", "cfgr-clk";
 827                         resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
 828                                  <&stgcrg JH7110_STGRST_DMA1P_AHB>;
 829                         interrupts = <73>;
 830                         #dma-cells = <1>;
 831                         dma-channels = <4>;
 832                         snps,dma-masters = <1>;
 833                         snps,data-width = <3>;
 834                         snps,block-size = <65536 65536 65536 65536>;
 835                         snps,priority = <0 1 2 3>;
 836                         snps,axi-max-burst-len = <16>;
 837                 };
 838
 839                 aoncrg: clock-controller@17000000 {
 840                         compatible = "starfive,jh7110-aoncrg";
 841                         reg = <0x0 0x17000000 0x0 0x10000>;
 842                         clocks = <&osc>, <&gmac0_rmii_refin>,
 843                                  <&gmac0_rgmii_rxin>,
 844                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 845                                  <&syscrg JH7110_SYSCLK_APB_BUS>,
 846                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
 847                                  <&rtc_osc>;
 848                         clock-names = "osc", "gmac0_rmii_refin",
 849                                       "gmac0_rgmii_rxin", "stg_axiahb",
 850                                       "apb_bus", "gmac0_gtxclk",
 851                                       "rtc_osc";
 852                         #clock-cells = <1>;
 853                         #reset-cells = <1>;
 854                 };
 855
 856                 aon_syscon: syscon@17010000 {
 857                         compatible = "starfive,jh7110-aon-syscon", "syscon";
 858                         reg = <0x0 0x17010000 0x0 0x1000>;
 859                 };
 860
 861                 aongpio: pinctrl@17020000 {
 862                         compatible = "starfive,jh7110-aon-pinctrl";
 863                         reg = <0x0 0x17020000 0x0 0x10000>;
 864                         resets = <&aoncrg JH7110_AONRST_IOMUX>;
 865                         interrupts = <85>;
 866                         interrupt-controller;
 867                         #interrupt-cells = <2>;
 868                         gpio-controller;
 869                         #gpio-cells = <2>;
 870                 };
 871
 872                 pwrc: power-controller@17030000 {
 873                         compatible = "starfive,jh7110-pmu";
 874                         reg = <0x0 0x17030000 0x0 0x10000>;
 875                         interrupts = <111>;
 876                         #power-domain-cells = <1>;
 877                 };
 878
 879                 ispcrg: clock-controller@19810000 {
 880                         compatible = "starfive,jh7110-ispcrg";
 881                         reg = <0x0 0x19810000 0x0 0x10000>;
 882                         clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
 883                                  <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
 884                                  <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
 885                                  <&dvp_clk>;
 886                         clock-names = "isp_top_core", "isp_top_axi",
 887                                       "noc_bus_isp_axi", "dvp_clk";
 888                         resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
 889                                  <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
 890                                  <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
 891                         #clock-cells = <1>;
 892                         #reset-cells = <1>;
 893                         power-domains = <&pwrc JH7110_PD_ISP>;
 894                 };
 895
 896                 csi_phy: phy@19820000 {
 897                         compatible = "starfive,jh7110-dphy-rx";
 898                         reg = <0x0 0x19820000 0x0 0x10000>;
 899                         clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
 900                                  <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
 901                                  <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
 902                         clock-names = "cfg", "ref", "tx";
 903                         resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
 904                                  <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
 905                         starfive,aon-syscon = <&aon_syscon 0x00>;
 906                         #phy-cells = <0>;
 907                 };
 908
 909                 voutcrg: clock-controller@295c0000 {
 910                         compatible = "starfive,jh7110-voutcrg";
 911                         reg = <0x0 0x295c0000 0x0 0x10000>;
 912                         clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
 913                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
 914                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
 915                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
 916                                  <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
 917                                  <&hdmitx0_pixelclk>;
 918                         clock-names = "vout_src", "vout_top_ahb",
 919                                       "vout_top_axi", "vout_top_hdmitx0_mclk",
 920                                       "i2stx0_bclk", "hdmitx0_pixelclk";
 921                         resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
 922                         #clock-cells = <1>;
 923                         #reset-cells = <1>;
 924                         power-domains = <&pwrc JH7110_PD_VOUT>;
 925                 };
 926
 927                 pcie0: pcie@2B000000 {
 928                         compatible = "starfive,jh7110-pcie";
 929                         #address-cells = <3>;
 930                         #size-cells = <2>;
 931                         #interrupt-cells = <1>;
 932                         reg = <0x0 0x2B000000 0x0 0x1000000
 933                                0x9 0x40000000 0x0 0x10000000>;
 934                         reg-names = "reg", "config";
 935                         device_type = "pci";
 936                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
 937                         bus-range = <0x0 0xff>;
 938                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
 939                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 940                         interrupts = <56>;
 941                         interrupt-parent = <&plic>;
 942                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 943                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
 944                                         <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
 945                                         <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
 946                                         <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
 947                         msi-parent = <&pcie0>;
 948                         msi-controller;
 949                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
 950                                  <&stgcrg JH7110_STGCLK_PCIE0_TL>,
 951                                  <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
 952                                  <&stgcrg JH7110_STGCLK_PCIE0_APB>;
 953                         clock-names = "noc", "tl", "axi_mst0", "apb";
 954                         resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
 955                                  <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
 956                                  <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
 957                                  <&stgcrg JH7110_STGRST_PCIE0_BRG>,
 958                                  <&stgcrg JH7110_STGRST_PCIE0_CORE>,
 959                                  <&stgcrg JH7110_STGRST_PCIE0_APB>;
 960                         reset-names = "mst0", "slv0", "slv", "brg",
 961                                       "core", "apb";
 962                         status = "disabled";
 963
 964                         pcie_intc0: interrupt-controller {
 965                                 #address-cells = <0>;
 966                                 #interrupt-cells = <1>;
 967                                 interrupt-controller;
 968                         };
 969                 };
 970
 971                 pcie1: pcie@2C000000 {
 972                         compatible = "starfive,jh7110-pcie";
 973                         #address-cells = <3>;
 974                         #size-cells = <2>;
 975                         #interrupt-cells = <1>;
 976                         reg = <0x0 0x2C000000 0x0 0x1000000
 977                                0x9 0xc0000000 0x0 0x10000000>;
 978                         reg-names = "reg", "config";
 979                         device_type = "pci";
 980                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
 981                         bus-range = <0x0 0xff>;
 982                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
 983                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
 984                         interrupts = <57>;
 985                         interrupt-parent = <&plic>;
 986                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 987                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
 988                                         <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
 989                                         <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
 990                                         <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
 991                         msi-parent = <&pcie1>;
 992                         msi-controller;
 993                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
 994                                  <&stgcrg JH7110_STGCLK_PCIE1_TL>,
 995                                  <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
 996                                  <&stgcrg JH7110_STGCLK_PCIE1_APB>;
 997                         clock-names = "noc", "tl", "axi_mst0", "apb";
 998                         resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
 999                                  <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1000                                  <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1001                                  <&stgcrg JH7110_STGRST_PCIE1_BRG>,
1002                                  <&stgcrg JH7110_STGRST_PCIE1_CORE>,
1003                                  <&stgcrg JH7110_STGRST_PCIE1_APB>;
1004                         reset-names = "mst0", "slv0", "slv", "brg",
1005                                       "core", "apb";
1006                         status = "disabled";
1007
1008                         pcie_intc1: interrupt-controller {
1009                                 #address-cells = <0>;
1010                                 #interrupt-cells = <1>;
1011                                 interrupt-controller;
1012                         };
1013                 };
1014         };
1015 };