1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110-clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
13 #include <dt-bindings/power/jh7110-power.h>
16 compatible = "starfive,jh7110";
20 cluster0_opp: opp-table-0 {
21 compatible = "operating-points-v2";
24 opp-hz = /bits/ 64 <375000000>;
25 opp-microvolt = <880000>;
28 opp-hz = /bits/ 64 <500000000>;
29 opp-microvolt = <880000>;
32 opp-hz = /bits/ 64 <625000000>;
33 opp-microvolt = <880000>;
36 opp-hz = /bits/ 64 <750000000>;
37 opp-microvolt = <880000>;
40 opp-hz = /bits/ 64 <875000000>;
41 opp-microvolt = <880000>;
44 opp-hz = /bits/ 64 <1000000000>;
45 opp-microvolt = <900000>;
48 opp-hz = /bits/ 64 <1250000000>;
49 opp-microvolt = <950000>;
52 opp-hz = /bits/ 64 <1375000000>;
53 opp-microvolt = <1000000>;
56 opp-hz = /bits/ 64 <1500000000>;
57 opp-microvolt = <1100000>;
60 opp-hz = /bits/ 64 <1625000000>;
61 opp-microvolt = <1100000>;
64 opp-hz = /bits/ 64 <1750000000>;
65 opp-microvolt = <1200000>;
74 compatible = "sifive,u74-mc", "riscv";
76 d-cache-block-size = <64>;
78 d-cache-size = <8192>;
82 i-cache-block-size = <64>;
84 i-cache-size = <16384>;
87 mmu-type = "riscv,sv39";
88 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
89 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
90 next-level-cache = <&cachectrl>;
91 riscv,isa = "rv64imac";
95 cpu0intctrl: interrupt-controller {
96 #interrupt-cells = <1>;
97 compatible = "riscv,cpu-intc";
103 compatible = "sifive,u74-mc", "riscv";
105 d-cache-block-size = <64>;
107 d-cache-size = <32768>;
111 i-cache-block-size = <64>;
113 i-cache-size = <32768>;
116 mmu-type = "riscv,sv39";
117 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
118 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
119 next-level-cache = <&cachectrl>;
120 riscv,isa = "rv64imafdc";
123 operating-points-v2 = <&cluster0_opp>;
125 cpu1intctrl: interrupt-controller {
126 #interrupt-cells = <1>;
127 compatible = "riscv,cpu-intc";
128 interrupt-controller;
133 compatible = "sifive,u74-mc", "riscv";
135 d-cache-block-size = <64>;
137 d-cache-size = <32768>;
141 i-cache-block-size = <64>;
143 i-cache-size = <32768>;
146 mmu-type = "riscv,sv39";
147 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
148 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
149 next-level-cache = <&cachectrl>;
150 riscv,isa = "rv64imafdc";
153 operating-points-v2 = <&cluster0_opp>;
155 cpu2intctrl: interrupt-controller {
156 #interrupt-cells = <1>;
157 compatible = "riscv,cpu-intc";
158 interrupt-controller;
163 compatible = "sifive,u74-mc", "riscv";
165 d-cache-block-size = <64>;
167 d-cache-size = <32768>;
171 i-cache-block-size = <64>;
173 i-cache-size = <32768>;
176 mmu-type = "riscv,sv39";
177 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
178 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
179 next-level-cache = <&cachectrl>;
180 riscv,isa = "rv64imafdc";
183 operating-points-v2 = <&cluster0_opp>;
185 cpu3intctrl: interrupt-controller {
186 #interrupt-cells = <1>;
187 compatible = "riscv,cpu-intc";
188 interrupt-controller;
193 compatible = "sifive,u74-mc", "riscv";
195 d-cache-block-size = <64>;
197 d-cache-size = <32768>;
201 i-cache-block-size = <64>;
203 i-cache-size = <32768>;
206 mmu-type = "riscv,sv39";
207 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
208 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
209 next-level-cache = <&cachectrl>;
210 riscv,isa = "rv64imafdc";
213 operating-points-v2 = <&cluster0_opp>;
215 cpu4intctrl: interrupt-controller {
216 #interrupt-cells = <1>;
217 compatible = "riscv,cpu-intc";
218 interrupt-controller;
224 CPU_RET_0_0: cpu-retentive-0-0 {
225 compatible = "riscv,idle-state";
226 riscv,sbi-suspend-param = <0x10000000>;
227 entry-latency-us = <20>;
228 exit-latency-us = <40>;
229 min-residency-us = <80>;
232 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
233 compatible = "riscv,idle-state";
234 riscv,sbi-suspend-param = <0x90000000>;
235 entry-latency-us = <250>;
236 exit-latency-us = <500>;
237 min-residency-us = <950>;
240 CLUSTER_RET_0: cluster-retentive-0 {
241 compatible = "riscv,idle-state";
242 riscv,sbi-suspend-param = <0x11000000>;
244 entry-latency-us = <50>;
245 exit-latency-us = <100>;
246 min-residency-us = <250>;
247 wakeup-latency-us = <130>;
250 CLUSTER_NONRET_0: cluster-nonretentive-0 {
251 compatible = "riscv,idle-state";
252 riscv,sbi-suspend-param = <0x91000000>;
254 entry-latency-us = <600>;
255 exit-latency-us = <1100>;
256 min-residency-us = <2700>;
257 wakeup-latency-us = <1500>;
262 compatible = "simple-bus";
263 interrupt-parent = <&plic>;
264 #address-cells = <2>;
269 cachectrl: cache-controller@2010000 {
270 compatible = "sifive,fu740-c000-ccache", "cache";
271 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
272 reg-names = "control", "sideband";
273 interrupts = <1 3 4 2>;
274 cache-block-size = <64>;
277 cache-size = <2097152>;
281 aon_syscon: aon_syscon@17010000 {
282 compatible = "syscon";
283 reg = <0x0 0x17010000 0x0 0x1000>;
286 stg_syscon: stg_syscon@10240000 {
287 compatible = "syscon";
288 reg = <0x0 0x10240000 0x0 0x1000>;
291 sys_syscon: sys_syscon@13030000 {
292 compatible = "syscon";
293 reg = <0x0 0x13030000 0x0 0x1000>;
296 clint: clint@2000000 {
297 compatible = "riscv,clint0";
298 reg = <0x0 0x2000000 0x0 0x10000>;
299 reg-names = "control";
300 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
301 &cpu1intctrl 3 &cpu1intctrl 7
302 &cpu2intctrl 3 &cpu2intctrl 7
303 &cpu3intctrl 3 &cpu3intctrl 7
304 &cpu4intctrl 3 &cpu4intctrl 7>;
305 #interrupt-cells = <1>;
309 compatible = "riscv,plic0";
310 reg = <0x0 0xc000000 0x0 0x4000000>;
311 reg-names = "control";
312 interrupts-extended = <&cpu0intctrl 11
313 &cpu1intctrl 11 &cpu1intctrl 9
314 &cpu2intctrl 11 &cpu2intctrl 9
315 &cpu3intctrl 11 &cpu3intctrl 9
316 &cpu4intctrl 11 &cpu4intctrl 9>;
317 interrupt-controller;
318 #interrupt-cells = <1>;
319 riscv,max-priority = <7>;
323 clkgen: clock-controller {
324 compatible = "starfive,jh7110-clkgen";
325 reg = <0x0 0x13020000 0x0 0x10000>,
326 <0x0 0x10230000 0x0 0x10000>,
327 <0x0 0x17000000 0x0 0x10000>;
328 reg-names = "sys", "stg", "aon";
329 clocks = <&osc>, <&gmac1_rmii_refin>,
331 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
332 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
333 <&tdm_ext>, <&mclk_ext>,
334 <&jtag_tck_inner>, <&bist_apb>,
336 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
337 clock-names = "osc", "gmac1_rmii_refin",
339 "i2stx_bclk_ext", "i2stx_lrck_ext",
340 "i2srx_bclk_ext", "i2srx_lrck_ext",
341 "tdm_ext", "mclk_ext",
342 "jtag_tck_inner", "bist_apb",
344 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
346 starfive,sys-syscon = <&sys_syscon 0x18 0x1c
347 0x20 0x24 0x28 0x2c 0x30 0x34>;
351 clkvout: clock-controller@295C0000 {
352 compatible = "starfive,jh7110-clk-vout";
353 reg = <0x0 0x295C0000 0x0 0x10000>;
355 clocks = <&hdmitx0_pixelclk>,
356 <&mipitx_dphy_rxesc>,
357 <&mipitx_dphy_txbytehs>,
358 <&clkgen JH7110_VOUT_SRC>,
359 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
360 clock-names = "hdmitx0_pixelclk",
362 "mipitx_dphy_txbytehs",
365 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
366 reset-names = "vout_src";
368 power-domains = <&pwrc JH7110_PD_VOUT>;
372 clkisp: clock-controller@19810000 {
373 compatible = "starfive,jh7110-clk-isp";
374 reg = <0x0 0x19810000 0x0 0x10000>;
377 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
378 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
379 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
380 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
381 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
382 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
383 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
384 "u0_sft7110_noc_bus_clk_isp_axi";
385 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
386 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
387 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
388 reset-names = "rst_isp_top_n", "rst_isp_top_axi",
390 power-domains = <&pwrc JH7110_PD_ISP>;
395 compatible = "cdns,qspi-nor";
396 #address-cells = <1>;
398 reg = <0x0 0x13010000 0x0 0x10000
399 0x0 0x21000000 0x0 0x400000>;
400 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
401 clock-names = "clk_ref";
402 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
403 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
404 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
405 resets-names = "rst_apb", "rst_ahb", "rst_ref";
406 cdns,fifo-depth = <256>;
407 cdns,fifo-width = <4>;
408 spi-max-frequency = <250000000>;
410 nor_flash: nor-flash@0 {
411 compatible = "jedec,spi-nor";
413 spi-max-frequency = <100000000>;
422 compatible = "starfive,jh7110-otp";
423 reg = <0x0 0x17050000 0x0 0x10000>;
424 clock-frequency = <4000000>;
425 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
430 compatible = "starfive,jh7110-cdns3";
431 reg = <0x0 0x10210000 0x0 0x1000>,
432 <0x0 0x10200000 0x0 0x1000>;
433 clocks = <&clkgen JH7110_USB_125M>,
434 <&clkgen JH7110_USB0_CLK_APP_125>,
435 <&clkgen JH7110_USB0_CLK_LPM>,
436 <&clkgen JH7110_USB0_CLK_STB>,
437 <&clkgen JH7110_USB0_CLK_USB_APB>,
438 <&clkgen JH7110_USB0_CLK_AXI>,
439 <&clkgen JH7110_USB0_CLK_UTMI_APB>,
440 <&clkgen JH7110_PCIE0_CLK_APB>;
441 clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
442 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
443 <&rstgen RSTN_U0_CDN_USB_APB>,
444 <&rstgen RSTN_U0_CDN_USB_AXI>,
445 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
446 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
447 reset-names = "pwrup","apb","axi","utmi", "phy";
448 starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
449 starfive,sys-syscon = <&sys_syscon 0x18>;
451 #address-cells = <2>;
453 #interrupt-cells = <1>;
455 usbdrd_cdns3: usb@10100000 {
456 compatible = "cdns,usb3";
457 reg = <0x0 0x10100000 0x0 0x10000>,
458 <0x0 0x10110000 0x0 0x10000>,
459 <0x0 0x10120000 0x0 0x10000>;
460 reg-names = "otg", "xhci", "dev";
461 interrupts = <100>, <108>, <110>;
462 interrupt-names = "host", "peripheral", "otg";
463 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
464 maximum-speed = "super-speed";
468 timer: timer@13050000 {
469 compatible = "starfive,jh7110-timers";
470 reg = <0x0 0x13050000 0x0 0x10000>;
471 interrupts = <69>, <70>, <71> ,<72>;
472 interrupt-names = "timer0", "timer1",
474 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
475 <&clkgen JH7110_TIMER_CLK_TIMER1>,
476 <&clkgen JH7110_TIMER_CLK_TIMER2>,
477 <&clkgen JH7110_TIMER_CLK_TIMER3>,
478 <&clkgen JH7110_TIMER_CLK_APB>;
479 clock-names = "timer0", "timer1",
480 "timer2", "timer3", "apb_clk";
481 resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
482 <&rstgen RSTN_U0_TIMER_TIMER1>,
483 <&rstgen RSTN_U0_TIMER_TIMER2>,
484 <&rstgen RSTN_U0_TIMER_TIMER3>,
485 <&rstgen RSTN_U0_TIMER_APB>;
486 reset-names = "timer0", "timer1",
487 "timer2", "timer3", "apb_rst";
488 clock-frequency = <24000000>;
492 wdog: wdog@13070000 {
493 compatible = "starfive,dskit-wdt";
494 reg = <0x0 0x13070000 0x0 0x10000>;
496 interrupt-names = "wdog";
497 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
498 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
499 clock-names = "core_clk", "apb_clk";
500 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
501 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
502 reset-names = "rst_apb", "rst_core";
508 compatible = "starfive,rtc_hms";
509 reg = <0x0 0x17040000 0x0 0x10000>;
510 interrupts = <10>, <11>, <12>;
511 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
512 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
513 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
514 clock-names = "pclk", "cal_clk";
515 resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
516 <&rstgen RSTN_U0_RTC_HMS_APB>,
517 <&rstgen RSTN_U0_RTC_HMS_CAL>;
518 reset-names = "rst_osc", "rst_apb", "rst_cal";
519 rtc,cal-clock-freq = <1000000>;
523 pwrc: power-controller@17030000 {
524 compatible = "starfive,jh7110-pmu";
525 reg = <0x0 0x17030000 0x0 0x10000>;
527 #power-domain-cells = <1>;
531 uart0: serial@10000000 {
532 compatible = "snps,dw-apb-uart";
533 reg = <0x0 0x10000000 0x0 0x10000>;
536 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
537 <&clkgen JH7110_UART0_CLK_APB>;
538 clock-names = "baudclk", "apb_pclk";
539 resets = <&rstgen RSTN_U0_DW_UART_APB>,
540 <&rstgen RSTN_U0_DW_UART_CORE>;
545 uart1: serial@10010000 {
546 compatible = "snps,dw-apb-uart";
547 reg = <0x0 0x10010000 0x0 0x10000>;
550 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
551 <&clkgen JH7110_UART1_CLK_APB>;
552 clock-names = "baudclk", "apb_pclk";
553 resets = <&rstgen RSTN_U1_DW_UART_APB>,
554 <&rstgen RSTN_U1_DW_UART_CORE>;
559 uart2: serial@10020000 {
560 compatible = "snps,dw-apb-uart";
561 reg = <0x0 0x10020000 0x0 0x10000>;
564 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
565 <&clkgen JH7110_UART2_CLK_APB>;
566 clock-names = "baudclk", "apb_pclk";
567 resets = <&rstgen RSTN_U2_DW_UART_APB>,
568 <&rstgen RSTN_U2_DW_UART_CORE>;
573 uart3: serial@12000000 {
574 compatible = "snps,dw-apb-uart";
575 reg = <0x0 0x12000000 0x0 0x10000>;
578 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
579 <&clkgen JH7110_UART3_CLK_APB>;
580 clock-names = "baudclk", "apb_pclk";
581 resets = <&rstgen RSTN_U3_DW_UART_APB>,
582 <&rstgen RSTN_U3_DW_UART_CORE>;
587 uart4: serial@12010000 {
588 compatible = "snps,dw-apb-uart";
589 reg = <0x0 0x12010000 0x0 0x10000>;
592 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
593 <&clkgen JH7110_UART4_CLK_APB>;
594 clock-names = "baudclk", "apb_pclk";
595 resets = <&rstgen RSTN_U4_DW_UART_APB>,
596 <&rstgen RSTN_U4_DW_UART_CORE>;
601 uart5: serial@12020000 {
602 compatible = "snps,dw-apb-uart";
603 reg = <0x0 0x12020000 0x0 0x10000>;
606 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
607 <&clkgen JH7110_UART5_CLK_APB>;
608 clock-names = "baudclk", "apb_pclk";
609 resets = <&rstgen RSTN_U5_DW_UART_APB>,
610 <&rstgen RSTN_U5_DW_UART_CORE>;
615 dma: dma-controller@16050000 {
616 compatible = "starfive,axi-dma";
617 reg = <0x0 0x16050000 0x0 0x10000>;
618 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
619 <&clkgen JH7110_DMA1P_CLK_AHB>;
620 clock-names = "core-clk", "cfgr-clk";
621 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
622 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
623 reset-names = "rst_axi", "rst_ahb";
627 snps,dma-masters = <1>;
628 snps,data-width = <3>;
629 snps,num-hs-if = <56>;
630 snps,block-size = <65536 65536 65536 65536>;
631 snps,priority = <0 1 2 3>;
632 snps,axi-max-burst-len = <16>;
636 gpio: gpio@13040000 {
637 compatible = "starfive,jh7110-sys-pinctrl";
638 reg = <0x0 0x13040000 0x0 0x10000>;
639 reg-names = "control";
640 clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
641 resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
643 interrupt-controller;
649 gpioa: gpio@17020000 {
650 compatible = "starfive,jh7110-aon-pinctrl";
651 reg = <0x0 0x17020000 0x0 0x10000>;
652 reg-names = "control";
653 resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
655 interrupt-controller;
661 sfctemp: tmon@120e0000 {
662 compatible = "starfive,jh7110-temp";
663 reg = <0x0 0x120e0000 0x0 0x10000>;
665 clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
666 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
667 clock-names = "sense", "bus";
668 resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
669 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
670 reset-names = "sense", "bus";
671 #thermal-sensor-cells = <0>;
677 polling-delay-passive = <250>;
678 polling-delay = <15000>;
680 thermal-sensors = <&sfctemp>;
686 cpu_alert0: cpu_alert0 {
688 temperature = <75000>;
695 temperature = <90000>;
703 trng: trng@1600C000 {
704 compatible = "starfive,trng";
705 reg = <0x0 0x1600C000 0x0 0x4000>;
706 clocks = <&clkgen JH7110_SEC_HCLK>,
707 <&clkgen JH7110_SEC_MISCAHB_CLK>;
708 clock-names = "hclk", "miscahb_clk";
709 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
714 sec_dma: sec_dma@16008000 {
715 /*compatible = "arm,pl080", "arm,primecell";*/
716 compatible = "starfive,pl080";
717 reg = <0x0 0x16008000 0x0 0x4000>;
718 reg-names = "sec_dma";
720 clocks = <&clkgen JH7110_SEC_HCLK>,
721 <&clkgen JH7110_SEC_MISCAHB_CLK>;
722 clock-names = "sec_hclk","sec_ahb";
723 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
724 reset-names = "sec_hre";
725 lli-bus-interface-ahb1;
726 mem-bus-interface-ahb1;
727 memcpy-burst-size = <256>;
728 memcpy-bus-width = <32>;
733 crypto: crypto@16000000 {
734 compatible = "starfive,jh7110-sec";
735 reg = <0x0 0x16000000 0x0 0x4000>,
736 <0x0 0x16008000 0x0 0x4000>;
737 reg-names = "secreg","secdma";
738 interrupts = <28>, <29>;
739 interrupt-names = "secirq", "dmairq";
740 clocks = <&clkgen JH7110_SEC_HCLK>,
741 <&clkgen JH7110_SEC_MISCAHB_CLK>;
742 clock-names = "sec_hclk","sec_ahb";
743 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
744 reset-names = "sec_hre";
745 enable-side-channel-mitigation = "true";
747 dmas = <&sec_dma 1 2>,
749 dma-names = "sec_m","sec_p";
754 compatible = "snps,designware-i2c";
755 reg = <0x0 0x10030000 0x0 0x10000>;
756 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
757 <&clkgen JH7110_I2C0_CLK_APB>;
758 clock-names = "ref", "pclk";
759 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
761 #address-cells = <1>;
767 compatible = "snps,designware-i2c";
768 reg = <0x0 0x10040000 0x0 0x10000>;
769 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
770 <&clkgen JH7110_I2C1_CLK_APB>;
771 clock-names = "ref", "pclk";
772 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
774 #address-cells = <1>;
780 compatible = "snps,designware-i2c";
781 reg = <0x0 0x10050000 0x0 0x10000>;
782 clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
783 <&clkgen JH7110_I2C2_CLK_APB>;
784 clock-names = "ref", "pclk";
785 resets = <&rstgen RSTN_U2_DW_I2C_APB>;
787 #address-cells = <1>;
793 compatible = "snps,designware-i2c";
794 reg = <0x0 0x12030000 0x0 0x10000>;
795 clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
796 <&clkgen JH7110_I2C3_CLK_APB>;
797 clock-names = "ref", "pclk";
798 resets = <&rstgen RSTN_U3_DW_I2C_APB>;
800 #address-cells = <1>;
806 compatible = "snps,designware-i2c";
807 reg = <0x0 0x12040000 0x0 0x10000>;
808 clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
809 <&clkgen JH7110_I2C4_CLK_APB>;
810 clock-names = "ref", "pclk";
811 resets = <&rstgen RSTN_U4_DW_I2C_APB>;
813 #address-cells = <1>;
819 compatible = "snps,designware-i2c";
820 reg = <0x0 0x12050000 0x0 0x10000>;
821 clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
822 <&clkgen JH7110_I2C5_CLK_APB>;
823 clock-names = "ref", "pclk";
824 resets = <&rstgen RSTN_U5_DW_I2C_APB>;
826 #address-cells = <1>;
832 compatible = "snps,designware-i2c";
833 reg = <0x0 0x12060000 0x0 0x10000>;
834 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
835 <&clkgen JH7110_I2C6_CLK_APB>;
836 clock-names = "ref", "pclk";
837 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
839 #address-cells = <1>;
844 /* unremovable emmc as mmcblk0 */
845 sdio0: sdio0@16010000 {
846 compatible = "snps,dw-mshc";
847 reg = <0x0 0x16010000 0x0 0x10000>;
848 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
849 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
850 clock-names = "biu","ciu";
851 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
852 reset-names = "reset";
855 fifo-watermark-aligned;
860 sdio1: sdio1@16020000 {
861 compatible = "snps,dw-mshc";
862 reg = <0x0 0x16020000 0x0 0x10000>;
863 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
864 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
865 clock-names = "biu","ciu";
866 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
867 reset-names = "reset";
870 fifo-watermark-aligned;
875 vin_sysctl: vin_sysctl@19800000 {
876 compatible = "starfive,stf-vin";
877 reg = <0x0 0x19800000 0x0 0x10000>,
878 <0x0 0x19810000 0x0 0x10000>,
879 <0x0 0x19820000 0x0 0x10000>,
880 <0x0 0x19840000 0x0 0x10000>,
881 <0x0 0x19870000 0x0 0x30000>,
882 <0x0 0x11840000 0x0 0x10000>,
883 <0x0 0x17030000 0x0 0x10000>,
884 <0x0 0x13020000 0x0 0x10000>;
885 reg-names = "csi2rx", "vclk", "vrst", "sctrl",
886 "isp", "trst", "pmu", "syscrg";
887 clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
888 <&clkisp JH7110_U0_VIN_PCLK>,
889 <&clkisp JH7110_U0_VIN_SYS_CLK>,
890 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
891 <&clkisp JH7110_DVP_INV>,
892 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
893 <&clkisp JH7110_MIPI_RX0_PXL>,
894 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
895 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
896 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
897 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
898 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
899 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
900 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
901 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
902 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
903 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
904 clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
905 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
906 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
907 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
908 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
909 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
910 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
911 resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
912 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
913 <&rstgen RSTN_U0_VIN_N_PCLK>,
914 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
915 <&rstgen RSTN_U0_VIN_P_AXIRD>,
916 <&rstgen RSTN_U0_VIN_P_AXIWR>,
917 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
918 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
919 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
920 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
921 <&rstgen RSTN_U0_M31DPHY_HW>,
922 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
923 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
924 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
925 reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
926 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
927 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
928 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
929 "rst_isp_top_n", "rst_isp_top_axi";
930 starfive,aon-syscon = <&aon_syscon 0x00>;
931 power-domains = <&pwrc JH7110_PD_ISP>;
932 /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
933 interrupts = <92 87 88 89 90>;
938 compatible = "starfive,jpu";
939 reg = <0x0 0x13090000 0x0 0x300>;
941 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
942 <&clkgen JH7110_CODAJ12_CLK_CORE>,
943 <&clkgen JH7110_CODAJ12_CLK_APB>,
944 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
945 clock-names = "axi_clk", "core_clk",
946 "apb_clk", "noc_bus";
947 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
948 <&rstgen RSTN_U0_CODAJ12_CORE>,
949 <&rstgen RSTN_U0_CODAJ12_APB>;
950 reset-names = "rst_axi", "rst_core", "rst_apb";
951 power-domains = <&pwrc JH7110_PD_VDEC>;
955 vpu_dec: vpu_dec@130A0000 {
956 compatible = "starfive,vdec";
957 reg = <0x0 0x130A0000 0x0 0x10000>;
959 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
960 <&clkgen JH7110_WAVE511_CLK_BPU>,
961 <&clkgen JH7110_WAVE511_CLK_VCE>,
962 <&clkgen JH7110_WAVE511_CLK_APB>,
963 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
964 clock-names = "axi_clk", "bpu_clk", "vce_clk",
965 "apb_clk", "noc_bus";
966 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
967 <&rstgen RSTN_U0_WAVE511_BPU>,
968 <&rstgen RSTN_U0_WAVE511_VCE>,
969 <&rstgen RSTN_U0_WAVE511_APB>,
970 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
971 reset-names = "rst_axi", "rst_bpu", "rst_vce",
972 "rst_apb", "rst_sram";
973 starfive,vdec_noc_ctrl;
974 power-domains = <&pwrc JH7110_PD_VDEC>;
978 vpu_enc: vpu_enc@130B0000 {
979 compatible = "starfive,venc";
980 reg = <0x0 0x130B0000 0x0 0x10000>;
982 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
983 <&clkgen JH7110_WAVE420L_CLK_BPU>,
984 <&clkgen JH7110_WAVE420L_CLK_VCE>,
985 <&clkgen JH7110_WAVE420L_CLK_APB>,
986 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
987 clock-names = "axi_clk", "bpu_clk", "vce_clk",
988 "apb_clk", "noc_bus";
989 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
990 <&rstgen RSTN_U0_WAVE420L_BPU>,
991 <&rstgen RSTN_U0_WAVE420L_VCE>,
992 <&rstgen RSTN_U0_WAVE420L_APB>,
993 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
994 reset-names = "rst_axi", "rst_bpu", "rst_vce",
995 "rst_apb", "rst_sram";
996 starfive,venc_noc_ctrl;
997 power-domains = <&pwrc JH7110_PD_VENC>;
1001 rstgen: reset-controller {
1002 compatible = "starfive,jh7110-reset";
1003 reg = <0x0 0x13020000 0x0 0x10000>,
1004 <0x0 0x10230000 0x0 0x10000>,
1005 <0x0 0x17000000 0x0 0x10000>,
1006 <0x0 0x19810000 0x0 0x10000>,
1007 <0x0 0x295C0000 0x0 0x10000>;
1008 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
1013 stmmac_axi_setup: stmmac-axi-config {
1014 snps,wr_osr_lmt = <0xf>;
1015 snps,rd_osr_lmt = <0xf>;
1016 snps,blen = <256 128 64 32 0 0 0>;
1019 gmac0: ethernet@16030000 {
1020 compatible = "starfive,jh7110-eqos-5.20";
1021 reg = <0x0 0x16030000 0x0 0x10000>;
1022 clock-names = "gtx",
1028 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
1029 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
1030 <&clkgen JH7110_GMAC0_PTP>,
1031 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
1032 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
1033 <&clkgen JH7110_GMAC0_GTXC>;
1034 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
1035 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
1036 reset-names = "ahb", "stmmaceth";
1037 interrupts = <7>, <6>, <5> ;
1038 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1039 max-frame-size = <9000>;
1040 phy-mode = "rgmii-id";
1041 snps,multicast-filter-bins = <64>;
1042 snps,perfect-filter-entries = <128>;
1043 rx-fifo-depth = <2048>;
1044 tx-fifo-depth = <2048>;
1047 snps,force_thresh_dma_mode;
1048 snps,axi-config = <&stmmac_axi_setup>;
1050 snps,en-tx-lpi-clockgating;
1052 snps,write-requests = <4>;
1053 snps,read-requests = <4>;
1054 snps,burst-map = <0x7>;
1057 status = "disabled";
1060 gmac1: ethernet@16040000 {
1061 compatible = "starfive,jh7110-eqos-5.20";
1062 reg = <0x0 0x16040000 0x0 0x10000>;
1063 clock-names = "gtx",
1069 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1070 <&clkgen JH7110_GMAC5_CLK_TX>,
1071 <&clkgen JH7110_GMAC5_CLK_PTP>,
1072 <&clkgen JH7110_GMAC5_CLK_AHB>,
1073 <&clkgen JH7110_GMAC5_CLK_AXI>,
1074 <&clkgen JH7110_GMAC1_GTXC>;
1075 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1076 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1077 reset-names = "ahb", "stmmaceth";
1078 interrupts = <78>, <77>, <76> ;
1079 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1080 max-frame-size = <9000>;
1081 phy-mode = "rgmii-id";
1082 snps,multicast-filter-bins = <64>;
1083 snps,perfect-filter-entries = <128>;
1084 rx-fifo-depth = <2048>;
1085 tx-fifo-depth = <2048>;
1088 snps,force_thresh_dma_mode;
1089 snps,axi-config = <&stmmac_axi_setup>;
1091 snps,en-tx-lpi-clockgating;
1093 snps,write-requests = <4>;
1094 snps,read-requests = <4>;
1095 snps,burst-map = <0x7>;
1098 status = "disabled";
1102 compatible = "img-gpu";
1103 reg = <0x0 0x18000000 0x0 0x100000>,
1104 <0x0 0x130C000 0x0 0x10000>;
1105 clocks = <&clkgen JH7110_GPU_CLK_APB>,
1106 <&clkgen JH7110_GPU_RTC_TOGGLE>,
1107 <&clkgen JH7110_GPU_CORE_CLK>,
1108 <&clkgen JH7110_GPU_SYS_CLK>,
1109 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1110 clock-names = "clk_apb", "clk_rtc", "clk_core",
1111 "clk_sys", "clk_axi";
1112 resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1113 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1114 reset-names = "rst_apb", "rst_doma";
1115 power-domains = <&pwrc JH7110_PD_GPUA>;
1117 current-clock = <8000000>;
1118 status = "disabled";
1121 can0: can@130d0000 {
1122 compatible = "ipms,can";
1123 reg = <0x0 0x130d0000 0x0 0x1000>;
1125 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1126 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1127 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1128 clock-names = "apb_clk", "core_clk", "timer_clk";
1129 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1130 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1131 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1132 reset-names = "rst_apb", "rst_core", "rst_timer";
1133 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1134 status = "disabled";
1137 can1: can@130e0000 {
1138 compatible = "ipms,can";
1139 reg = <0x0 0x130e0000 0x0 0x1000>;
1141 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1142 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1143 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1144 clock-names = "apb_clk", "core_clk", "timer_clk";
1145 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1146 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1147 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1148 reset-names = "rst_apb", "rst_core", "rst_timer";
1149 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1150 status = "disabled";
1154 compatible = "starfive,sf-tdm";
1155 reg = <0x0 0x10090000 0x0 0x1000>;
1157 clocks = <&clkgen JH7110_AHB0>,
1158 <&clkgen JH7110_TDM_CLK_AHB>,
1159 <&clkgen JH7110_APB0>,
1160 <&clkgen JH7110_TDM_CLK_APB>,
1161 <&clkgen JH7110_TDM_INTERNAL>,
1163 <&clkgen JH7110_TDM_CLK_TDM>,
1164 <&clkgen JH7110_MCLK_INNER>;
1165 clock-names = "clk_ahb0", "clk_tdm_ahb",
1166 "clk_apb0", "clk_tdm_apb",
1167 "clk_tdm_internal", "clk_tdm_ext",
1168 "clk_tdm", "mclk_inner";
1169 resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1170 <&rstgen RSTN_U0_TDM16SLOT_APB>,
1171 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1172 reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1173 dmas = <&dma 20 1>, <&dma 21 1>;
1174 dma-names = "rx","tx";
1175 #sound-dai-cells = <0>;
1176 status = "disabled";
1179 spdif0: spdif0@100a0000 {
1180 compatible = "starfive,sf-spdif";
1181 reg = <0x0 0x100a0000 0x0 0x1000>;
1182 clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1183 <&clkgen JH7110_SPDIF_CLK_CORE>,
1184 <&clkgen JH7110_AUDIO_ROOT>,
1185 <&clkgen JH7110_MCLK_INNER>;
1186 clock-names = "spdif-apb", "spdif-core",
1187 "audroot", "mclk_inner";
1188 resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1189 reset-names = "rst_apb";
1191 interrupt-names = "tx";
1192 #sound-dai-cells = <0>;
1193 status = "disabled";
1196 pwmdac: pwmdac@100b0000 {
1197 compatible = "starfive,pwmdac";
1198 reg = <0x0 0x100b0000 0x0 0x1000>;
1199 clocks = <&clkgen JH7110_APB0>,
1200 <&clkgen JH7110_PWMDAC_CLK_APB>,
1201 <&clkgen JH7110_PWMDAC_CLK_CORE>;
1202 clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1203 resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1204 reset-names = "rst-apb";
1207 #sound-dai-cells = <0>;
1208 status = "disabled";
1211 i2stx: i2stx@100c0000 {
1212 compatible = "snps,designware-i2stx";
1213 reg = <0x0 0x100c0000 0x0 0x1000>;
1214 interrupt-names = "tx";
1215 #sound-dai-cells = <0>;
1218 status = "disabled";
1222 compatible = "starfive,sf-pdm";
1223 reg = <0x0 0x100d0000 0x0 0x1000>;
1225 clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1226 <&clkgen JH7110_APB0>,
1227 <&clkgen JH7110_PDM_CLK_APB>,
1228 <&clkgen JH7110_MCLK_INNER>,
1229 <&clkgen JH7110_MCLK>,
1230 <&clkgen JH7110_MCLK_OUT>;
1231 clock-names = "pdm_mclk", "clk_apb0",
1232 "pdm_apb", "mclk_inner",
1233 "clk_mclk", "mclk_out";
1234 resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1235 <&rstgen RSTN_U0_PDM_4MIC_APB>;
1236 reset-names = "pdm_dmic", "pdm_apb";
1237 #sound-dai-cells = <0>;
1240 i2srx_mst: i2srx_mst@100e0000 {
1241 compatible = "snps,i2srx-master";
1242 reg = <0x0 0x100e0000 0x0 0x1000>;
1243 clocks = <&clkgen JH7110_APB0>,
1244 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1245 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1246 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1247 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1248 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1249 clock-names = "apb0", "i2srx_apb",
1250 "i2srx_bclk_mst", "i2srx_lrck_mst",
1251 "i2srx_bclk", "i2srx_lrck";
1252 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1253 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1254 reset-names = "rst_apb_rx", "rst_bclk_rx";
1257 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1258 #sound-dai-cells = <0>;
1259 status = "disabled";
1262 i2srx_3ch: i2srx_3ch@100e0000 {
1263 compatible = "snps,designware-i2srx";
1264 reg = <0x0 0x100e0000 0x0 0x1000>;
1265 clocks = <&clkgen JH7110_APB0>,
1266 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1267 <&clkgen JH7110_AUDIO_ROOT>,
1268 <&clkgen JH7110_MCLK_INNER>,
1269 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1270 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1271 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1272 <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1273 <&clkgen JH7110_MCLK>,
1276 clock-names = "apb0", "3ch-apb",
1277 "audioroot", "mclk-inner",
1278 "bclk_mst", "3ch-lrck",
1279 "rx-bclk", "rx-lrck",
1282 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1283 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1286 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1287 #sound-dai-cells = <0>;
1288 status = "disabled";
1291 i2stx_4ch0: i2stx_4ch0@120b0000 {
1292 compatible = "snps,designware-i2stx-4ch0";
1293 reg = <0x0 0x120b0000 0x0 0x1000>;
1294 clocks = <&clkgen JH7110_MCLK_INNER>,
1295 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1296 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1297 <&clkgen JH7110_MCLK>,
1298 <&clkgen JH7110_I2STX0_4CHBCLK>,
1299 <&clkgen JH7110_I2STX0_4CHLRCK>;
1300 clock-names = "inner", "bclk-mst",
1303 resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1304 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1307 #sound-dai-cells = <0>;
1308 status = "disabled";
1311 i2stx_4ch1: i2stx_4ch1@120c0000 {
1312 compatible = "snps,designware-i2stx-4ch1";
1313 reg = <0x0 0x120c0000 0x0 0x1000>;
1314 clocks = <&clkgen JH7110_AUDIO_ROOT>,
1315 <&clkgen JH7110_MCLK_INNER>,
1316 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1317 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1318 <&clkgen JH7110_MCLK>,
1319 <&clkgen JH7110_I2STX1_4CHBCLK>,
1320 <&clkgen JH7110_I2STX1_4CHLRCK>,
1321 <&clkgen JH7110_MCLK_OUT>,
1322 <&clkgen JH7110_APB0>,
1323 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1327 clock-names = "audroot", "mclk_inner", "bclk_mst",
1328 "lrck_mst", "mclk", "4chbclk",
1329 "4chlrck", "mclk_out",
1331 "mclk_ext", "bclk_ext", "lrck_ext";
1333 resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1334 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1337 #sound-dai-cells = <0>;
1338 status = "disabled";
1342 compatible = "starfive,pwm";
1343 reg = <0x0 0x120d0000 0x0 0x10000>;
1344 reg-names = "control";
1345 clocks = <&clkgen JH7110_PWM_CLK_APB>;
1346 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1347 starfive,approx-freq = <2000000>;
1349 starfive,npwm = <8>;
1350 status = "disabled";
1353 spdif_transmitter: spdif_transmitter {
1354 compatible = "linux,spdif-dit";
1355 #sound-dai-cells = <0>;
1356 status = "disabled";
1359 spdif_receiver: spdif_receiver {
1360 compatible = "linux,spdif-dir";
1361 #sound-dai-cells = <0>;
1362 status = "disabled";
1365 pwmdac_codec: pwmdac-transmitter {
1366 compatible = "linux,pwmdac-dit";
1367 #sound-dai-cells = <0>;
1368 status = "disabled";
1371 dmic_codec: dmic_codec {
1372 compatible = "dmic-codec";
1373 #sound-dai-cells = <0>;
1374 status = "disabled";
1377 spi0: spi@10060000 {
1378 compatible = "arm,pl022", "arm,primecell";
1379 reg = <0x0 0x10060000 0x0 0x10000>;
1380 clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1381 clock-names = "apb_pclk";
1382 resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1383 reset-names = "rst_apb";
1385 /* shortage of dma channel that not be used */
1386 /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1387 /*dma-names = "rx","tx";*/
1388 arm,primecell-periphid = <0x00041022>;
1390 #address-cells = <1>;
1392 status = "disabled";
1395 spi1: spi@10070000 {
1396 compatible = "arm,pl022", "arm,primecell";
1397 reg = <0x0 0x10070000 0x0 0x10000>;
1398 clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1399 clock-names = "apb_pclk";
1400 resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1401 reset-names = "rst_apb";
1403 /* shortage of dma channel that not be used */
1404 /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1405 /*dma-names = "rx","tx";*/
1406 arm,primecell-periphid = <0x00041022>;
1408 #address-cells = <1>;
1410 status = "disabled";
1413 spi2: spi@10080000 {
1414 compatible = "arm,pl022", "arm,primecell";
1415 reg = <0x0 0x10080000 0x0 0x10000>;
1416 clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1417 clock-names = "apb_pclk";
1418 resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1419 reset-names = "rst_apb";
1421 /* shortage of dma channel that not be used */
1422 /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1423 /*dma-names = "rx","tx";*/
1424 arm,primecell-periphid = <0x00041022>;
1426 #address-cells = <1>;
1428 status = "disabled";
1431 spi3: spi@12070000 {
1432 compatible = "arm,pl022", "arm,primecell";
1433 reg = <0x0 0x12070000 0x0 0x10000>;
1434 clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1435 clock-names = "apb_pclk";
1436 resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1437 reset-names = "rst_apb";
1439 /* shortage of dma channel that not be used */
1440 /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1441 /*dma-names = "rx","tx";*/
1442 arm,primecell-periphid = <0x00041022>;
1444 #address-cells = <1>;
1446 status = "disabled";
1449 spi4: spi@12080000 {
1450 compatible = "arm,pl022", "arm,primecell";
1451 reg = <0x0 0x12080000 0x0 0x10000>;
1452 clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1453 clock-names = "apb_pclk";
1454 resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1455 reset-names = "rst_apb";
1457 /* shortage of dma channel that not be used */
1458 /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1459 /*dma-names = "rx","tx";*/
1460 arm,primecell-periphid = <0x00041022>;
1462 #address-cells = <1>;
1464 status = "disabled";
1467 spi5: spi@12090000 {
1468 compatible = "arm,pl022", "arm,primecell";
1469 reg = <0x0 0x12090000 0x0 0x10000>;
1470 clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1471 clock-names = "apb_pclk";
1472 resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1473 reset-names = "rst_apb";
1475 /* shortage of dma channel that not be used */
1476 /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1477 /*dma-names = "rx","tx";*/
1478 arm,primecell-periphid = <0x00041022>;
1480 #address-cells = <1>;
1482 status = "disabled";
1485 spi6: spi@120A0000 {
1486 compatible = "arm,pl022", "arm,primecell";
1487 reg = <0x0 0x120A0000 0x0 0x10000>;
1488 clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1489 clock-names = "apb_pclk";
1490 resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1491 reset-names = "rst_apb";
1493 /* shortage of dma channel that not be used */
1494 /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1495 /*dma-names = "rx","tx";*/
1496 arm,primecell-periphid = <0x00041022>;
1498 #address-cells = <1>;
1500 status = "disabled";
1503 pcie0: pcie@2B000000 {
1504 compatible = "plda,pci-xpressrich3-axi";
1505 #address-cells = <3>;
1507 #interrupt-cells = <1>;
1508 reg = <0x0 0x2B000000 0x0 0x1000000
1509 0x9 0x40000000 0x0 0x10000000>;
1510 reg-names = "reg", "config";
1511 device_type = "pci";
1512 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1513 bus-range = <0x0 0xff>;
1514 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>;
1515 msi-parent = <&plic>;
1517 interrupt-controller;
1518 interrupt-names = "msi";
1519 interrupt-parent = <&plic>;
1520 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1521 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1522 <0x0 0x0 0x0 0x2 &plic 0x2>,
1523 <0x0 0x0 0x0 0x3 &plic 0x3>,
1524 <0x0 0x0 0x0 0x4 &plic 0x4>;
1525 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1526 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1527 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1528 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1529 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1530 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1531 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1532 "rst_brg", "rst_core", "rst_apb";
1533 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1534 <&clkgen JH7110_PCIE0_CLK_TL>,
1535 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1536 <&clkgen JH7110_PCIE0_CLK_APB>;
1537 clock-names = "noc", "tl", "axi_mst0", "apb";
1538 status = "disabled";
1541 pcie1: pcie@2C000000 {
1542 compatible = "plda,pci-xpressrich3-axi";
1543 #address-cells = <3>;
1545 #interrupt-cells = <1>;
1546 reg = <0x0 0x2C000000 0x0 0x1000000
1547 0x9 0xc0000000 0x0 0x10000000>;
1548 reg-names = "reg", "config";
1549 device_type = "pci";
1550 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1551 bus-range = <0x0 0xff>;
1552 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>;
1553 msi-parent = <&plic>;
1555 interrupt-controller;
1556 interrupt-names = "msi";
1557 interrupt-parent = <&plic>;
1558 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1559 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1560 <0x0 0x0 0x0 0x2 &plic 0x2>,
1561 <0x0 0x0 0x0 0x3 &plic 0x3>,
1562 <0x0 0x0 0x0 0x4 &plic 0x4>;
1563 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1564 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1565 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1566 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1567 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1568 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1569 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1570 "rst_brg", "rst_core", "rst_apb";
1571 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1572 <&clkgen JH7110_PCIE1_CLK_TL>,
1573 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1574 <&clkgen JH7110_PCIE1_CLK_APB>;
1575 clock-names = "noc", "tl", "axi_mst0", "apb";
1576 status = "disabled";
1579 mailbox_contrl0: mailbox@0 {
1580 compatible = "starfive,mail_box";
1581 reg = <0x0 0x13060000 0x0 0x0001000>;
1582 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1583 clock-names = "clk_apb";
1584 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1585 reset-names = "mbx_rre";
1586 interrupts = <26 27>;
1588 status = "disabled";
1591 mailbox_client0: mailbox_client@0 {
1592 compatible = "starfive,mailbox-test";
1593 mbox-names = "rx", "tx";
1594 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1595 status = "disabled";
1598 display: display-subsystem {
1599 compatible = "verisilicon,display-subsystem";
1600 ports = <&dc_out_dpi0>;
1601 status = "disabled";
1604 dssctrl: dssctrl@295B0000 {
1605 compatible = "verisilicon,dss-ctrl", "syscon";
1606 reg = <0 0x295B0000 0 0x90>;
1609 tda988x_pin: tda988x_pin {
1610 compatible = "starfive,tda998x_rgb_pin";
1611 status = "disabled";
1614 hdmi_output: hdmi-output {
1615 compatible = "verisilicon,hdmi-encoder";
1616 //verisilicon,dss-syscon = <&dssctrl>;
1617 //verisilicon,mux-mask = <0x70 0x380>;
1618 //verisilicon,mux-val = <0x40 0x280>;
1619 status = "disabled";
1622 dc8200: dc8200@29400000 {
1623 compatible = "verisilicon,dc8200";
1624 verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1625 reg = <0x0 0x29400000 0x0 0x100>,
1626 <0x0 0x29400800 0x0 0x2000>,
1627 <0x0 0x17030000 0x0 0x1000>;
1629 status = "disabled";
1630 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1631 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1632 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1633 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1634 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1635 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1636 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1637 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1638 <&clkgen JH7110_VOUT_SRC>,
1639 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1640 <&clkgen JH7110_AHB1>,
1641 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1642 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1643 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1644 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1645 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1646 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1647 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1648 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1649 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1650 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1651 <&hdmitx0_pixelclk>,
1652 <&clkvout JH7110_DC8200_PIX0>,
1653 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1654 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1655 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1656 "noc_disp","noc_isp","noc_stg","vout_src",
1657 "top_vout_axi","ahb1","top_vout_ahb",
1658 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1659 "axi_clk","core_clk","vout_ahb",
1660 "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1661 "dc8200_pix0_out","dc8200_pix1_out";
1662 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1663 <&rstgen RSTN_U0_DC8200_AXI>,
1664 <&rstgen RSTN_U0_DC8200_AHB>,
1665 <&rstgen RSTN_U0_DC8200_CORE>,
1666 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1667 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1668 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1669 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1670 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1671 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1672 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1673 "rst_noc_disp","rst_noc_stg";
1674 power-domains = <&pwrc JH7110_PD_VOUT>;
1677 encoder: display-encoder {
1678 compatible = "verisilicon,dsi-encoder";
1679 status = "disabled";
1682 mipi_dphy: mipi-dphy@295e0000{
1683 compatible = "starfive,jh7100-mipi-dphy-tx";
1684 reg = <0x0 0x295e0000 0x0 0x10000>;
1685 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1686 clock-names = "dphy_txesc";
1687 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1688 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1689 reset-names = "dphy_sys", "dphy_txbytehs";
1691 status = "disabled";
1694 mipi_dsi: mipi@295d0000 {
1695 compatible = "cdns,dsi";
1696 reg = <0x0 0x295d0000 0x0 0x10000>;
1699 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1700 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1701 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1702 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1703 clock-names = "sys", "apb", "txesc", "dpi";
1704 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1705 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1706 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1707 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1708 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1709 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1710 reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1711 "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1712 phys = <&mipi_dphy>;
1714 status = "disabled";
1717 dsi_out_port: endpoint@0 {
1718 remote-endpoint = <&panel_dsi_port>;
1720 dsi_in_port: endpoint@1 {
1721 remote-endpoint = <&mipi_out>;
1725 mipi_panel: panel@0 {
1726 /*compatible = "";*/
1731 hdmi: hdmi@29590000 {
1732 compatible = "rockchip,rk3036-inno-hdmi";
1733 reg = <0x0 0x29590000 0x0 0x4000>;
1735 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1736 /*clocks = <&cru PCLK_HDMI>;*/
1737 /*clock-names = "pclk";*/
1738 /*pinctrl-names = "default";*/
1739 /*pinctrl-0 = <&hdmi_ctl>;*/
1740 status = "disabled";
1741 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1742 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1743 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1744 <&hdmitx0_pixelclk>;
1745 clock-names = "sysclk", "mclk","bclk","pclk";
1746 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1747 reset-names = "hdmi_tx";
1751 compatible = "simple-audio-card";
1752 simple-audio-card,name = "Starfive-Multi-Sound-Card";
1753 #address-cells = <1>;
1758 compatible = "starfive,e24";
1759 reg = <0x0 0xc0110000 0x0 0x00001000>,
1760 <0x0 0xc0111000 0x0 0x0001f000>;
1761 reg-names = "ecmd", "espace";
1762 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1763 <&clkgen JH7110_E2_CLK_CORE>,
1764 <&clkgen JH7110_E2_CLK_DBG>;
1765 clock-names = "clk_rtc", "clk_core", "clk_dbg";
1766 resets = <&rstgen RSTN_U0_E24_CORE>;
1767 reset-names = "e24_core";
1768 starfive,stg-syscon = <&stg_syscon>;
1769 interrupt-parent = <&plic>;
1770 firmware-name = "e24_elf";
1772 mbox-names = "tx", "rx";
1773 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1774 #address-cells = <1>;
1776 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1777 status = "disabled";
1782 compatible = "cdns,xrp";
1783 reg = <0x0 0x10230000 0x0 0x00010000
1784 0x0 0x10240000 0x0 0x00010000>;
1785 memory-region = <&xrp_reserved>;
1786 clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1787 clock-names = "core_clk";
1788 resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1789 <&rstgen RSTN_U0_HIFI4_AXI>;
1790 reset-names = "rst_core","rst_axi";
1791 starfive,stg-syscon = <&stg_syscon>;
1792 firmware-name = "hifi4_elf";
1793 #address-cells = <1>;
1795 ranges = <0x40000000 0x0 0x20000000 0x040000
1796 0xf0000000 0x0 0xf0000000 0x03000000>;
1797 status = "disabled";
1802 stf_cpufreq: starfive,stf-cpufreq {
1803 compatible = "starfive,stf-cpufreq";
1804 clocks = <&clkgen JH7110_PLL0_OUT>,
1805 <&clkgen JH7110_CPU_ROOT>,
1807 clock-names = "pll0", "cpu_clk", "osc";