arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <800000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <800000>;
  30                         };
  31                         opp-750000000 {
  32                                         opp-hz = /bits/ 64 <750000000>;
  33                                         opp-microvolt = <800000>;
  34                                         opp-suspend;
  35                         };
  36                         opp-1500000000 {
  37                                         opp-hz = /bits/ 64 <1500000000>;
  38                                         opp-microvolt = <1040000>;
  39                         };
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         compatible = "sifive,u74-mc", "riscv";
  48                         reg = <0>;
  49                         d-cache-block-size = <64>;
  50                         d-cache-sets = <64>;
  51                         d-cache-size = <8192>;
  52                         d-tlb-sets = <1>;
  53                         d-tlb-size = <40>;
  54                         device_type = "cpu";
  55                         i-cache-block-size = <64>;
  56                         i-cache-sets = <64>;
  57                         i-cache-size = <16384>;
  58                         i-tlb-sets = <1>;
  59                         i-tlb-size = <40>;
  60                         mmu-type = "riscv,sv39";
  61                         next-level-cache = <&cachectrl>;
  62                         riscv,isa = "rv64imac";
  63                         tlb-split;
  64                         status = "disabled";
  65
  66                         cpu0intctrl: interrupt-controller {
  67                                 #interrupt-cells = <1>;
  68                                 compatible = "riscv,cpu-intc";
  69                                 interrupt-controller;
  70                         };
  71                 };
  72
  73                 cpu1: cpu@1 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <1>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <32768>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <32768>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         next-level-cache = <&cachectrl>;
  89                         riscv,isa = "rv64imafdc";
  90                         tlb-split;
  91                         status = "okay";
  92                         operating-points-v2 = <&cluster0_opp>;
  93
  94                         cpu1intctrl: interrupt-controller {
  95                                 #interrupt-cells = <1>;
  96                                 compatible = "riscv,cpu-intc";
  97                                 interrupt-controller;
  98                         };
  99                 };
 100
 101                 cpu2: cpu@2 {
 102                         compatible = "sifive,u74-mc", "riscv";
 103                         reg = <2>;
 104                         d-cache-block-size = <64>;
 105                         d-cache-sets = <64>;
 106                         d-cache-size = <32768>;
 107                         d-tlb-sets = <1>;
 108                         d-tlb-size = <40>;
 109                         device_type = "cpu";
 110                         i-cache-block-size = <64>;
 111                         i-cache-sets = <64>;
 112                         i-cache-size = <32768>;
 113                         i-tlb-sets = <1>;
 114                         i-tlb-size = <40>;
 115                         mmu-type = "riscv,sv39";
 116                         next-level-cache = <&cachectrl>;
 117                         riscv,isa = "rv64imafdc";
 118                         tlb-split;
 119                         status = "okay";
 120                         operating-points-v2 = <&cluster0_opp>;
 121
 122                         cpu2intctrl: interrupt-controller {
 123                                 #interrupt-cells = <1>;
 124                                 compatible = "riscv,cpu-intc";
 125                                 interrupt-controller;
 126                         };
 127                 };
 128
 129                 cpu3: cpu@3 {
 130                         compatible = "sifive,u74-mc", "riscv";
 131                         reg = <3>;
 132                         d-cache-block-size = <64>;
 133                         d-cache-sets = <64>;
 134                         d-cache-size = <32768>;
 135                         d-tlb-sets = <1>;
 136                         d-tlb-size = <40>;
 137                         device_type = "cpu";
 138                         i-cache-block-size = <64>;
 139                         i-cache-sets = <64>;
 140                         i-cache-size = <32768>;
 141                         i-tlb-sets = <1>;
 142                         i-tlb-size = <40>;
 143                         mmu-type = "riscv,sv39";
 144                         next-level-cache = <&cachectrl>;
 145                         riscv,isa = "rv64imafdc";
 146                         tlb-split;
 147                         status = "okay";
 148                         operating-points-v2 = <&cluster0_opp>;
 149
 150                         cpu3intctrl: interrupt-controller {
 151                                 #interrupt-cells = <1>;
 152                                 compatible = "riscv,cpu-intc";
 153                                 interrupt-controller;
 154                         };
 155                 };
 156
 157                 cpu4: cpu@4 {
 158                         compatible = "sifive,u74-mc", "riscv";
 159                         reg = <4>;
 160                         d-cache-block-size = <64>;
 161                         d-cache-sets = <64>;
 162                         d-cache-size = <32768>;
 163                         d-tlb-sets = <1>;
 164                         d-tlb-size = <40>;
 165                         device_type = "cpu";
 166                         i-cache-block-size = <64>;
 167                         i-cache-sets = <64>;
 168                         i-cache-size = <32768>;
 169                         i-tlb-sets = <1>;
 170                         i-tlb-size = <40>;
 171                         mmu-type = "riscv,sv39";
 172                         next-level-cache = <&cachectrl>;
 173                         riscv,isa = "rv64imafdc";
 174                         tlb-split;
 175                         status = "okay";
 176                         operating-points-v2 = <&cluster0_opp>;
 177
 178                         cpu4intctrl: interrupt-controller {
 179                                 #interrupt-cells = <1>;
 180                                 compatible = "riscv,cpu-intc";
 181                                 interrupt-controller;
 182                         };
 183                 };
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 interrupt-parent = <&plic>;
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 #clock-cells = <1>;
 192                 ranges;
 193
 194                 cachectrl: cache-controller@2010000 {
 195                         compatible = "sifive,fu740-c000-ccache", "cache";
 196                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 197                         reg-names = "control", "sideband";
 198                         interrupts = <1 3 4 2>;
 199                         cache-block-size = <64>;
 200                         cache-level = <2>;
 201                         cache-sets = <2048>;
 202                         cache-size = <2097152>;
 203                         cache-unified;
 204                 };
 205
 206                 aon_syscon: aon_syscon@17010000 {
 207                         compatible = "syscon";
 208                         reg = <0x0 0x17010000 0x0 0x1000>;
 209                 };
 210
 211                 phyctrl0: multi-phyctrl@10210000 {
 212                         compatible = "starfive,phyctrl";
 213                         reg = <0x0 0x10210000 0x0 0x10000>;
 214                 };
 215
 216                 phyctrl1: pcie1-phyctrl@10220000 {
 217                         compatible = "starfive,phyctrl";
 218                         reg = <0x0 0x10220000 0x0 0x10000>;
 219                 };
 220
 221                 stg_syscon: stg_syscon@10240000 {
 222                         compatible = "syscon";
 223                         reg = <0x0 0x10240000 0x0 0x1000>;
 224                 };
 225
 226                 sys_syscon: sys_syscon@13030000 {
 227                         compatible = "syscon";
 228                         reg = <0x0 0x13030000 0x0 0x1000>;
 229                 };
 230
 231                 clint: clint@2000000 {
 232                         compatible = "riscv,clint0";
 233                         reg = <0x0 0x2000000 0x0 0x10000>;
 234                         reg-names = "control";
 235                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 236                                                 &cpu1intctrl 3 &cpu1intctrl 7
 237                                                 &cpu2intctrl 3 &cpu2intctrl 7
 238                                                 &cpu3intctrl 3 &cpu3intctrl 7
 239                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 240                         #interrupt-cells = <1>;
 241                 };
 242
 243                 plic: plic@c000000 {
 244                         compatible = "riscv,plic0";
 245                         reg = <0x0 0xc000000 0x0 0x4000000>;
 246                         reg-names = "control";
 247                         interrupts-extended = <&cpu0intctrl 11
 248                                                 &cpu1intctrl 11 &cpu1intctrl 9
 249                                                 &cpu2intctrl 11 &cpu2intctrl 9
 250                                                 &cpu3intctrl 11 &cpu3intctrl 9
 251                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 252                         interrupt-controller;
 253                         #interrupt-cells = <1>;
 254                         riscv,max-priority = <7>;
 255                         riscv,ndev = <136>;
 256                 };
 257
 258                 clkgen: clock-controller {
 259                         compatible = "starfive,jh7110-clkgen";
 260                         reg = <0x0 0x13020000 0x0 0x10000>,
 261                                 <0x0 0x10230000 0x0 0x10000>,
 262                                 <0x0 0x17000000 0x0 0x10000>;
 263                         reg-names = "sys", "stg", "aon";
 264                         clocks = <&osc>, <&gmac1_rmii_refin>,
 265                                  <&gmac1_rgmii_rxin>,
 266                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 267                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 268                                  <&tdm_ext>, <&mclk_ext>,
 269                                  <&jtag_tck_inner>, <&bist_apb>,
 270                                  <&clk_rtc>,
 271                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 272                         clock-names = "osc", "gmac1_rmii_refin",
 273                                 "gmac1_rgmii_rxin",
 274                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 275                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 276                                 "tdm_ext", "mclk_ext",
 277                                 "jtag_tck_inner", "bist_apb",
 278                                 "clk_rtc",
 279                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 280                         #clock-cells = <1>;
 281                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 282                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 283                         status = "okay";
 284                 };
 285
 286                 clkvout: clock-controller@295C0000 {
 287                         compatible = "starfive,jh7110-clk-vout";
 288                         reg = <0x0 0x295C0000 0x0 0x10000>;
 289                         reg-names = "vout";
 290                         clocks = <&hdmitx0_pixelclk>,
 291                                  <&mipitx_dphy_rxesc>,
 292                                  <&mipitx_dphy_txbytehs>,
 293                                  <&clkgen JH7110_VOUT_SRC>,
 294                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 295                         clock-names = "hdmitx0_pixelclk",
 296                                       "mipitx_dphy_rxesc",
 297                                       "mipitx_dphy_txbytehs",
 298                                       "vout_src",
 299                                       "vout_top_ahb";
 300                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 301                         reset-names = "vout_src";
 302                         #clock-cells = <1>;
 303                         power-domains = <&pwrc JH7110_PD_VOUT>;
 304                         status = "okay";
 305                 };
 306
 307                 clkisp: clock-controller@19810000 {
 308                         compatible = "starfive,jh7110-clk-isp";
 309                         reg = <0x0 0x19810000 0x0 0x10000>;
 310                         reg-names = "isp";
 311                         #clock-cells = <1>;
 312                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 313                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 314                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 315                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 316                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 317                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 318                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 319                                       "u0_sft7110_noc_bus_clk_isp_axi";
 320                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 321                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 322                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 323                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 324                                       "rst_isp_noc_bus_n";
 325                         power-domains = <&pwrc JH7110_PD_ISP>;
 326                         status = "okay";
 327                 };
 328
 329                 qspi: spi@13010000 {
 330                         compatible = "cdns,qspi-nor";
 331                         #address-cells = <1>;
 332                         #size-cells = <0>;
 333                         reg = <0x0 0x13010000 0x0 0x10000
 334                                 0x0 0x21000000 0x0 0x400000>;
 335                         interrupts = <25>;
 336                         clocks = <&clkgen JH7110_QSPI_CLK_REF>,
 337                                  <&clkgen JH7110_QSPI_CLK_APB>,
 338                                  <&clkgen JH7110_AHB1>,
 339                                  <&clkgen JH7110_QSPI_CLK_AHB>;
 340                         clock-names = "clk_ref",
 341                                       "clk_apb",
 342                                       "ahb1",
 343                                       "clk_ahb";
 344                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 345                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 346                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 347                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 348                         cdns,fifo-depth = <256>;
 349                         cdns,fifo-width = <4>;
 350                         cdns,trigger-address = <0x0>;
 351                         spi-max-frequency = <250000000>;
 352
 353                         nor_flash: nor-flash@0 {
 354                                 compatible = "jedec,spi-nor";
 355                                 reg=<0>;
 356                                 cdns,read-delay = <5>;
 357                                 spi-max-frequency = <100000000>;
 358                                 cdns,tshsl-ns = <1>;
 359                                 cdns,tsd2d-ns = <1>;
 360                                 cdns,tchsh-ns = <1>;
 361                                 cdns,tslch-ns = <1>;
 362
 363                                 partitions {
 364                                         compatible = "fixed-partitions";
 365                                         #address-cells = <1>;
 366                                         #size-cells = <1>;
 367
 368                                         spl@0 {
 369                                                 reg = <0x0 0x20000>;
 370                                         };
 371                                         uboot@100000 {
 372                                                 reg = <0x100000 0x300000>;
 373                                         };
 374                                         data@f00000 {
 375                                                 reg = <0xf00000 0x100000>;
 376                                         };
 377                                 };
 378                         };
 379                 };
 380
 381                 otp: otp@17050000 {
 382                         compatible = "starfive,jh7110-otp";
 383                         reg = <0x0 0x17050000 0x0 0x10000>;
 384                         clock-frequency = <4000000>;
 385                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 386                         clock-names = "apb";
 387                 };
 388
 389                 usbdrd30: usbdrd{
 390                         compatible = "starfive,jh7110-cdns3";
 391                         reg = <0x0 0x10210000 0x0 0x1000>,
 392                               <0x0 0x10200000 0x0 0x1000>;
 393                         clocks = <&clkgen JH7110_USB_125M>,
 394                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 395                                  <&clkgen JH7110_USB0_CLK_LPM>,
 396                                  <&clkgen JH7110_USB0_CLK_STB>,
 397                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 398                                  <&clkgen JH7110_USB0_CLK_AXI>,
 399                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 400                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 401                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 402                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 403                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 404                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 405                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 406                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 407                         reset-names = "pwrup","apb","axi","utmi", "phy";
 408                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 409                         starfive,sys-syscon = <&sys_syscon 0x18>;
 410                         status = "disabled";
 411                         #address-cells = <2>;
 412                         #size-cells = <2>;
 413                         #interrupt-cells = <1>;
 414                         ranges;
 415                         usbdrd_cdns3: usb@10100000 {
 416                                 compatible = "cdns,usb3";
 417                                 reg = <0x0 0x10100000 0x0 0x10000>,
 418                                       <0x0 0x10110000 0x0 0x10000>,
 419                                       <0x0 0x10120000 0x0 0x10000>;
 420                                 reg-names = "otg", "xhci", "dev";
 421                                 interrupts = <100>, <108>, <110>;
 422                                 interrupt-names = "host", "peripheral", "otg";
 423                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 424                                 maximum-speed = "super-speed";
 425                         };
 426                 };
 427
 428                 timer: timer@13050000 {
 429                         compatible = "starfive,jh7110-timers";
 430                         reg = <0x0 0x13050000 0x0 0x10000>;
 431                         interrupts = <69>, <70>, <71> ,<72>;
 432                         interrupt-names = "timer0", "timer1",
 433                                           "timer2", "timer3";
 434                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 435                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 436                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 437                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 438                                  <&clkgen JH7110_TIMER_CLK_APB>;
 439                         clock-names = "timer0", "timer1",
 440                                       "timer2", "timer3", "apb_clk";
 441                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 442                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 443                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 444                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 445                                  <&rstgen RSTN_U0_TIMER_APB>;
 446                         reset-names = "timer0", "timer1",
 447                                       "timer2", "timer3", "apb_rst";
 448                         clock-frequency = <24000000>;
 449                         status = "okay";
 450                 };
 451
 452                 wdog: wdog@13070000 {
 453                         compatible = "starfive,jh7110-wdt";
 454                         reg = <0x0 0x13070000 0x0 0x10000>;
 455                         interrupts = <68>;
 456                         interrupt-names = "wdog";
 457                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 458                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 459                         clock-names = "core_clk", "apb_clk";
 460                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 461                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 462                         reset-names = "rst_apb", "rst_core";
 463                         timeout-sec = <15>;
 464                         status = "okay";
 465                 };
 466
 467                 rtc: rtc@17040000 {
 468                         compatible = "starfive,jh7110-rtc";
 469                         reg = <0x0 0x17040000 0x0 0x10000>;
 470                         interrupts = <10>, <11>, <12>;
 471                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 472                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 473                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 474                         clock-names = "pclk", "cal_clk";
 475                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 476                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 477                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 478                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 479                         rtc,cal-clock-freq = <1000000>;
 480                         status = "okay";
 481                 };
 482
 483                 pwrc: power-controller@17030000 {
 484                         compatible = "starfive,jh7110-pmu";
 485                         reg = <0x0 0x17030000 0x0 0x10000>;
 486                         interrupts = <111>;
 487                         #power-domain-cells = <1>;
 488                         status = "okay";
 489                 };
 490
 491                 uart0: serial@10000000 {
 492                         compatible = "snps,dw-apb-uart";
 493                         reg = <0x0 0x10000000 0x0 0x10000>;
 494                         reg-io-width = <4>;
 495                         reg-shift = <2>;
 496                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 497                                  <&clkgen JH7110_UART0_CLK_APB>;
 498                         clock-names = "baudclk", "apb_pclk";
 499                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 500                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 501                         interrupts = <32>;
 502                         status = "disabled";
 503                 };
 504
 505                 uart1: serial@10010000 {
 506                         compatible = "snps,dw-apb-uart";
 507                         reg = <0x0 0x10010000 0x0 0x10000>;
 508                         reg-io-width = <4>;
 509                         reg-shift = <2>;
 510                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 511                                  <&clkgen JH7110_UART1_CLK_APB>;
 512                         clock-names = "baudclk", "apb_pclk";
 513                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 514                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 515                         interrupts = <33>;
 516                         status = "disabled";
 517                 };
 518
 519                 uart2: serial@10020000 {
 520                         compatible = "snps,dw-apb-uart";
 521                         reg = <0x0 0x10020000 0x0 0x10000>;
 522                         reg-io-width = <4>;
 523                         reg-shift = <2>;
 524                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 525                                  <&clkgen JH7110_UART2_CLK_APB>;
 526                         clock-names = "baudclk", "apb_pclk";
 527                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 528                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 529                         interrupts = <34>;
 530                         status = "disabled";
 531                 };
 532
 533                 uart3: serial@12000000 {
 534                         compatible = "snps,dw-apb-uart";
 535                         reg = <0x0 0x12000000 0x0 0x10000>;
 536                         reg-io-width = <4>;
 537                         reg-shift = <2>;
 538                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 539                                  <&clkgen JH7110_UART3_CLK_APB>;
 540                         clock-names = "baudclk", "apb_pclk";
 541                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 542                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 543                         interrupts = <45>;
 544                         status = "disabled";
 545                 };
 546
 547                 uart4: serial@12010000 {
 548                         compatible = "snps,dw-apb-uart";
 549                         reg = <0x0 0x12010000 0x0 0x10000>;
 550                         reg-io-width = <4>;
 551                         reg-shift = <2>;
 552                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 553                                  <&clkgen JH7110_UART4_CLK_APB>;
 554                         clock-names = "baudclk", "apb_pclk";
 555                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 556                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 557                         interrupts = <46>;
 558                         status = "disabled";
 559                 };
 560
 561                 uart5: serial@12020000 {
 562                         compatible = "snps,dw-apb-uart";
 563                         reg = <0x0 0x12020000 0x0 0x10000>;
 564                         reg-io-width = <4>;
 565                         reg-shift = <2>;
 566                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 567                                  <&clkgen JH7110_UART5_CLK_APB>;
 568                         clock-names = "baudclk", "apb_pclk";
 569                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 570                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 571                         interrupts = <47>;
 572                         status = "disabled";
 573                 };
 574
 575                 dma: dma-controller@16050000 {
 576                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 577                         reg = <0x0 0x16050000 0x0 0x10000>;
 578                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 579                                  <&clkgen JH7110_DMA1P_CLK_AHB>,
 580                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
 581                         clock-names = "core-clk", "cfgr-clk", "stg_clk";
 582                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 583                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>,
 584                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
 585                         reset-names = "rst_axi", "rst_ahb", "rst_stg";
 586                         interrupts = <73>;
 587                         #dma-cells = <2>;
 588                         dma-channels = <4>;
 589                         snps,dma-masters = <1>;
 590                         snps,data-width = <3>;
 591                         snps,num-hs-if = <56>;
 592                         snps,block-size = <65536 65536 65536 65536>;
 593                         snps,priority = <0 1 2 3>;
 594                         snps,axi-max-burst-len = <16>;
 595                         status = "disabled";
 596                 };
 597
 598                 gpio: gpio@13040000 {
 599                         compatible = "starfive,jh7110-sys-pinctrl";
 600                         reg = <0x0 0x13040000 0x0 0x10000>;
 601                         reg-names = "control";
 602                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 603                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 604                         interrupts = <86>;
 605                         interrupt-controller;
 606                         #gpio-cells = <2>;
 607                         ngpios = <64>;
 608                         status = "okay";
 609                 };
 610
 611                 gpioa: gpio@17020000 {
 612                         compatible = "starfive,jh7110-aon-pinctrl";
 613                         reg = <0x0 0x17020000 0x0 0x10000>;
 614                         reg-names = "control";
 615                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 616                         interrupts = <85>;
 617                         interrupt-controller;
 618                         #gpio-cells = <2>;
 619                         ngpios = <4>;
 620                         status = "okay";
 621                 };
 622
 623                 sfctemp: tmon@120e0000  {
 624                         compatible = "starfive,jh7110-temp";
 625                         reg = <0x0 0x120e0000 0x0 0x10000>;
 626                         interrupts = <81>;
 627                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 628                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 629                         clock-names = "sense", "bus";
 630                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 631                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 632                         reset-names = "sense", "bus";
 633                         #thermal-sensor-cells = <0>;
 634                         status = "disabled";
 635                 };
 636
 637                 thermal-zones {
 638                         cpu-thermal {
 639                                 polling-delay-passive = <250>;
 640                                 polling-delay = <15000>;
 641
 642                                 thermal-sensors = <&sfctemp>;
 643
 644                                 cooling-maps {
 645                                 };
 646
 647                                 trips {
 648                                         cpu_alert0: cpu_alert0 {
 649                                                 /* milliCelsius */
 650                                                 temperature = <75000>;
 651                                                 hysteresis = <2000>;
 652                                                 type = "passive";
 653                                         };
 654
 655                                         cpu_crit: cpu_crit {
 656                                                 /* milliCelsius */
 657                                                 temperature = <90000>;
 658                                                 hysteresis = <2000>;
 659                                                 type = "critical";
 660                                         };
 661                                 };
 662                         };
 663                 };
 664
 665                 trng: trng@1600C000 {
 666                         compatible = "starfive,jh7110-trng";
 667                         reg = <0x0 0x1600C000 0x0 0x4000>;
 668                         clocks = <&clkgen JH7110_SEC_HCLK>,
 669                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 670                         clock-names = "hclk", "ahb";
 671                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 672                         interrupts = <30>;
 673                         status = "disabled";
 674                 };
 675
 676                 sec_dma: sec_dma@16008000 {
 677                         compatible = "arm,pl080", "arm,primecell";
 678                         arm,primecell-periphid = <0x00041080>;
 679                         reg = <0x0 0x16008000 0x0 0x4000>;
 680                         reg-names = "sec_dma";
 681                         interrupts = <29>;
 682                         clocks = <&clkgen JH7110_SEC_HCLK>,
 683                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 684                         clock-names = "sec_hclk","apb_pclk";
 685                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 686                         reset-names = "sec_hre";
 687                         lli-bus-interface-ahb1;
 688                         mem-bus-interface-ahb1;
 689                         memcpy-burst-size = <256>;
 690                         memcpy-bus-width = <32>;
 691                         #dma-cells = <2>;
 692                         status = "disabled";
 693                 };
 694
 695                 crypto: crypto@16000000 {
 696                         compatible = "starfive,jh7110-sec";
 697                         reg = <0x0 0x16000000 0x0 0x4000>,
 698                               <0x0 0x16008000 0x0 0x4000>;
 699                         reg-names = "secreg","secdma";
 700                         interrupts = <28>, <29>;
 701                         interrupt-names = "secirq", "dmairq";
 702                         clocks = <&clkgen JH7110_SEC_HCLK>,
 703                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 704                         clock-names = "sec_hclk","sec_ahb";
 705                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 706                         reset-names = "sec_hre";
 707                         enable-side-channel-mitigation = "true";
 708                         enable-dma = "true";
 709                         dmas = <&sec_dma 1 2>,
 710                                <&sec_dma 0 2>;
 711                         dma-names = "sec_m","sec_p";
 712                         status = "disabled";
 713                 };
 714
 715                 i2c0: i2c@10030000 {
 716                         compatible = "snps,designware-i2c";
 717                         reg = <0x0 0x10030000 0x0 0x10000>;
 718                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 719                                  <&clkgen JH7110_I2C0_CLK_APB>;
 720                         clock-names = "ref", "pclk";
 721                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 722                         interrupts = <35>;
 723                         #address-cells = <1>;
 724                         #size-cells = <0>;
 725                         status = "disabled";
 726                 };
 727
 728                 i2c1: i2c@10040000 {
 729                         compatible = "snps,designware-i2c";
 730                         reg = <0x0 0x10040000 0x0 0x10000>;
 731                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 732                                  <&clkgen JH7110_I2C1_CLK_APB>;
 733                         clock-names = "ref", "pclk";
 734                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 735                         interrupts = <36>;
 736                         #address-cells = <1>;
 737                         #size-cells = <0>;
 738                         status = "disabled";
 739                 };
 740
 741                 i2c2: i2c@10050000 {
 742                         compatible = "snps,designware-i2c";
 743                         reg = <0x0 0x10050000 0x0 0x10000>;
 744                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 745                                  <&clkgen JH7110_I2C2_CLK_APB>;
 746                         clock-names = "ref", "pclk";
 747                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 748                         interrupts = <37>;
 749                         #address-cells = <1>;
 750                         #size-cells = <0>;
 751                         status = "disabled";
 752                 };
 753
 754                 i2c3: i2c@12030000 {
 755                         compatible = "snps,designware-i2c";
 756                         reg = <0x0 0x12030000 0x0 0x10000>;
 757                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 758                                  <&clkgen JH7110_I2C3_CLK_APB>;
 759                         clock-names = "ref", "pclk";
 760                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 761                         interrupts = <48>;
 762                         #address-cells = <1>;
 763                         #size-cells = <0>;
 764                         status = "disabled";
 765                 };
 766
 767                 i2c4: i2c@12040000 {
 768                         compatible = "snps,designware-i2c";
 769                         reg = <0x0 0x12040000 0x0 0x10000>;
 770                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 771                                  <&clkgen JH7110_I2C4_CLK_APB>;
 772                         clock-names = "ref", "pclk";
 773                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 774                         interrupts = <49>;
 775                         #address-cells = <1>;
 776                         #size-cells = <0>;
 777                         status = "disabled";
 778                 };
 779
 780                 i2c5: i2c@12050000 {
 781                         compatible = "snps,designware-i2c";
 782                         reg = <0x0 0x12050000 0x0 0x10000>;
 783                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 784                                  <&clkgen JH7110_I2C5_CLK_APB>;
 785                         clock-names = "ref", "pclk";
 786                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 787                         interrupts = <50>;
 788                         #address-cells = <1>;
 789                         #size-cells = <0>;
 790                         status = "disabled";
 791                 };
 792
 793                 i2c6: i2c@12060000 {
 794                         compatible = "snps,designware-i2c";
 795                         reg = <0x0 0x12060000 0x0 0x10000>;
 796                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 797                                  <&clkgen JH7110_I2C6_CLK_APB>;
 798                         clock-names = "ref", "pclk";
 799                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 800                         interrupts = <51>;
 801                         #address-cells = <1>;
 802                         #size-cells = <0>;
 803                         status = "disabled";
 804                 };
 805
 806                 /* unremovable emmc as mmcblk0 */
 807                 sdio0: sdio0@16010000 {
 808                         compatible = "starfive,jh7110-sdio";
 809                         reg = <0x0 0x16010000 0x0 0x10000>;
 810                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 811                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 812                         clock-names = "biu","ciu";
 813                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 814                         reset-names = "reset";
 815                         interrupts = <74>;
 816                         fifo-depth = <32>;
 817                         fifo-watermark-aligned;
 818                         data-addr = <0>;
 819                         starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
 820                         status = "disabled";
 821                 };
 822
 823                 sdio1: sdio1@16020000 {
 824                         compatible = "starfive,jh7110-sdio";
 825                         reg = <0x0 0x16020000 0x0 0x10000>;
 826                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 827                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 828                         clock-names = "biu","ciu";
 829                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 830                         reset-names = "reset";
 831                         interrupts = <75>;
 832                         fifo-depth = <32>;
 833                         fifo-watermark-aligned;
 834                         data-addr = <0>;
 835                         starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;
 836                         status = "disabled";
 837                 };
 838
 839                 vin_sysctl: vin_sysctl@19800000 {
 840                         compatible = "starfive,jh7110-vin";
 841                         reg = <0x0 0x19800000 0x0 0x10000>,
 842                                 <0x0 0x19810000 0x0 0x10000>,
 843                                 <0x0 0x19820000 0x0 0x10000>,
 844                                 <0x0 0x19840000 0x0 0x10000>,
 845                                 <0x0 0x19870000 0x0 0x30000>,
 846                                 <0x0 0x11840000 0x0 0x10000>,
 847                                 <0x0 0x17030000 0x0 0x10000>,
 848                                 <0x0 0x13020000 0x0 0x10000>;
 849                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 850                                 "isp", "trst", "pmu", "syscrg";
 851                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 852                                  <&clkisp JH7110_U0_VIN_PCLK>,
 853                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 854                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 855                                  <&clkisp JH7110_DVP_INV>,
 856                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 857                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 858                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 859                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 860                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 861                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 862                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 863                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 864                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 865                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 866                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
 867                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 868                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 869                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 870                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 871                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 872                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 873                                 "clk_ispcore_2x", "clk_isp_axi";
 874                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 875                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 876                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 877                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 878                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 879                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 880                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 881                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 882                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 883                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 884                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 885                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 886                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 887                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 888                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 889                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 890                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 891                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 892                                 "rst_isp_top_n", "rst_isp_top_axi";
 893                         starfive,aon-syscon = <&aon_syscon 0x00>;
 894                         power-domains = <&pwrc JH7110_PD_ISP>;
 895                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 896                         interrupts = <92 87 88 89 90>;
 897                         status = "disabled";
 898                 };
 899
 900                 jpu: jpu@11900000 {
 901                         compatible = "starfive,jpu";
 902                         reg = <0x0 0x13090000 0x0 0x300>;
 903                         interrupts = <14>;
 904                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 905                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 906                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 907                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 908                         clock-names = "axi_clk", "core_clk",
 909                                       "apb_clk", "noc_bus";
 910                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 911                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 912                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 913                         reset-names = "rst_axi", "rst_core", "rst_apb";
 914                         power-domains = <&pwrc JH7110_PD_VDEC>;
 915                         status = "disabled";
 916                 };
 917
 918                 vpu_dec: vpu_dec@130A0000 {
 919                         compatible = "starfive,vdec";
 920                         reg = <0x0 0x130A0000 0x0 0x10000>;
 921                         interrupts = <13>;
 922                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 923                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 924                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 925                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 926                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 927                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 928                                       "apb_clk", "noc_bus";
 929                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 930                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 931                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 932                                 <&rstgen RSTN_U0_WAVE511_APB>,
 933                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 934                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 935                                       "rst_apb", "rst_sram";
 936                         starfive,vdec_noc_ctrl;
 937                         power-domains = <&pwrc JH7110_PD_VDEC>;
 938                         status = "disabled";
 939                 };
 940
 941                 vpu_enc: vpu_enc@130B0000 {
 942                         compatible = "starfive,venc";
 943                         reg = <0x0 0x130B0000 0x0 0x10000>;
 944                         interrupts = <15>;
 945                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 946                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 947                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 948                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 949                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 950                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 951                                       "apb_clk", "noc_bus";
 952                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 953                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 954                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 955                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 956                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 957                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 958                                       "rst_apb", "rst_sram";
 959                         starfive,venc_noc_ctrl;
 960                         power-domains = <&pwrc JH7110_PD_VENC>;
 961                         status = "disabled";
 962                 };
 963
 964                 rstgen: reset-controller {
 965                         compatible = "starfive,jh7110-reset";
 966                         reg = <0x0 0x13020000 0x0 0x10000>,
 967                                 <0x0 0x10230000 0x0 0x10000>,
 968                                 <0x0 0x17000000 0x0 0x10000>,
 969                                 <0x0 0x19810000 0x0 0x10000>,
 970                                 <0x0 0x295C0000 0x0 0x10000>;
 971                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 972                         #reset-cells = <1>;
 973                         status = "okay";
 974                 };
 975
 976                 stmmac_axi_setup: stmmac-axi-config {
 977                         snps,wr_osr_lmt = <0xf>;
 978                         snps,rd_osr_lmt = <0xf>;
 979                         snps,blen = <256 128 64 32 0 0 0>;
 980                 };
 981
 982                 gmac0: ethernet@16030000 {
 983                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
 984                         reg = <0x0 0x16030000 0x0 0x10000>;
 985                         clock-names = "gtx",
 986                                 "tx",
 987                                 "ptp_ref",
 988                                 "stmmaceth",
 989                                 "pclk",
 990                                 "gtxc";
 991                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 992                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 993                                  <&clkgen JH7110_GMAC0_PTP>,
 994                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 995                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 996                                  <&clkgen JH7110_GMAC0_GTXC>;
 997                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 998                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 999                         reset-names = "ahb", "stmmaceth";
1000                         interrupts = <7>, <6>, <5> ;
1001                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1002                         max-frame-size = <9000>;
1003                         phy-mode = "rgmii-id";
1004                         snps,multicast-filter-bins = <64>;
1005                         snps,perfect-filter-entries = <128>;
1006                         rx-fifo-depth = <2048>;
1007                         tx-fifo-depth = <2048>;
1008                         snps,fixed-burst;
1009                         snps,no-pbl-x8;
1010                         snps,force_thresh_dma_mode;
1011                         snps,axi-config = <&stmmac_axi_setup>;
1012                         snps,tso;
1013                         snps,en-tx-lpi-clockgating;
1014                         snps,en-lpi;
1015                         snps,write-requests = <4>;
1016                         snps,read-requests = <4>;
1017                         snps,burst-map = <0x7>;
1018                         snps,txpbl = <16>;
1019                         snps,rxpbl = <16>;
1020                         status = "disabled";
1021                 };
1022
1023                 gmac1: ethernet@16040000 {
1024                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
1025                         reg = <0x0 0x16040000 0x0 0x10000>;
1026                         clock-names = "gtx",
1027                                 "tx",
1028                                 "ptp_ref",
1029                                 "stmmaceth",
1030                                 "pclk",
1031                                 "gtxc";
1032                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1033                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1034                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1035                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1036                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1037                                  <&clkgen JH7110_GMAC1_GTXC>;
1038                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1039                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1040                         reset-names = "ahb", "stmmaceth";
1041                         interrupts = <78>, <77>, <76> ;
1042                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1043                         max-frame-size = <9000>;
1044                         phy-mode = "rgmii-id";
1045                         snps,multicast-filter-bins = <64>;
1046                         snps,perfect-filter-entries = <128>;
1047                         rx-fifo-depth = <2048>;
1048                         tx-fifo-depth = <2048>;
1049                         snps,fixed-burst;
1050                         snps,no-pbl-x8;
1051                         snps,force_thresh_dma_mode;
1052                         snps,axi-config = <&stmmac_axi_setup>;
1053                         snps,tso;
1054                         snps,en-tx-lpi-clockgating;
1055                         snps,en-lpi;
1056                         snps,write-requests = <4>;
1057                         snps,read-requests = <4>;
1058                         snps,burst-map = <0x7>;
1059                         snps,txpbl = <16>;
1060                         snps,rxpbl = <16>;
1061                         status = "disabled";
1062                 };
1063
1064                 gpu: gpu@18000000 {
1065                         compatible = "img-gpu";
1066                         reg = <0x0 0x18000000 0x0 0x100000>,
1067                                 <0x0 0x130C000 0x0 0x10000>;
1068                         clocks = <&clkgen JH7110_GPU_CORE>,
1069                                  <&clkgen JH7110_GPU_CLK_APB>,
1070                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1071                                  <&clkgen JH7110_GPU_CORE_CLK>,
1072                                  <&clkgen JH7110_GPU_SYS_CLK>,
1073                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1074                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1075                                         "clk_core", "clk_sys", "clk_axi";
1076                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1077                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1078                         reset-names = "rst_apb", "rst_doma";
1079                         power-domains = <&pwrc JH7110_PD_GPUA>;
1080                         interrupts = <82>;
1081                         current-clock = <8000000>;
1082                         status = "disabled";
1083                 };
1084
1085                 can0: can@130d0000 {
1086                         compatible = "starfive,jh7110-can", "ipms,can";
1087                         reg = <0x0 0x130d0000 0x0 0x1000>;
1088                         interrupts = <112>;
1089                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1090                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1091                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1092                         clock-names = "apb_clk", "core_clk", "timer_clk";
1093                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1094                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1095                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1096                         reset-names = "rst_apb", "rst_core", "rst_timer";
1097                         frequency = <40000000>;
1098                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1099                         syscon,can_or_canfd = <0>;
1100                         status = "disabled";
1101                 };
1102
1103                 can1: can@130e0000 {
1104                         compatible = "starfive,jh7110-can", "ipms,can";
1105                         reg = <0x0 0x130e0000 0x0 0x1000>;
1106                         interrupts = <113>;
1107                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1108                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1109                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1110                         clock-names = "apb_clk", "core_clk", "timer_clk";
1111                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1112                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1113                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1114                         reset-names = "rst_apb", "rst_core", "rst_timer";
1115                         frequency = <40000000>;
1116                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1117                         syscon,can_or_canfd = <1>;
1118                         status = "disabled";
1119                 };
1120
1121                 tdm: tdm@10090000 {
1122                         compatible = "starfive,jh7110-tdm";
1123                         reg = <0x0 0x10090000 0x0 0x1000>;
1124                         reg-names = "tdm";
1125                         clocks = <&clkgen JH7110_TDM_CLK_AHB>,
1126                                  <&clkgen JH7110_TDM_CLK_APB>,
1127                                  <&clkgen JH7110_TDM_INTERNAL>,
1128                                  <&tdm_ext>,
1129                                  <&clkgen JH7110_TDM_CLK_TDM>,
1130                                  <&clkgen JH7110_MCLK_INNER>;
1131                         clock-names = "clk_tdm_ahb", "clk_tdm_apb",
1132                                       "clk_tdm_internal", "clk_tdm_ext",
1133                                       "clk_tdm", "mclk_inner";
1134                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1135                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1136                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1137                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1138                         dmas = <&dma 20 1>, <&dma 21 1>;
1139                         dma-names = "rx","tx";
1140                         #sound-dai-cells = <0>;
1141                         status = "disabled";
1142                 };
1143
1144                 spdif0: spdif0@100a0000 {
1145                         compatible = "starfive,jh7110-spdif";
1146                         reg = <0x0 0x100a0000 0x0 0x1000>;
1147                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1148                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1149                                  <&clkgen JH7110_AUDIO_ROOT>,
1150                                  <&clkgen JH7110_MCLK_INNER>,
1151                                  <&mclk_ext>, <&clkgen JH7110_MCLK>;
1152                         clock-names = "spdif-apb", "spdif-core",
1153                                       "audroot", "mclk_inner",
1154                                       "mclk_ext", "mclk";
1155                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1156                         reset-names = "rst_apb";
1157                         interrupts = <84>;
1158                         interrupt-names = "tx";
1159                         #sound-dai-cells = <0>;
1160                         status = "disabled";
1161                 };
1162
1163                 pwmdac: pwmdac@100b0000 {
1164                         compatible = "starfive,jh7110-pwmdac";
1165                         reg = <0x0 0x100b0000 0x0 0x1000>;
1166                         clocks = <&clkgen JH7110_APB0>,
1167                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1168                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1169                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1170                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1171                         reset-names = "rst-apb";
1172                         dmas = <&dma 22 1>;
1173                         dma-names = "tx";
1174                         #sound-dai-cells = <0>;
1175                         status = "disabled";
1176                 };
1177
1178                 i2stx: i2stx@100c0000 {
1179                         compatible = "snps,designware-i2stx";
1180                         reg = <0x0 0x100c0000 0x0 0x1000>;
1181                         interrupt-names = "tx";
1182                         #sound-dai-cells = <0>;
1183                         dmas = <&dma 28 1>;
1184                         dma-names = "rx";
1185                         status = "disabled";
1186                 };
1187
1188                 pdm: pdm@100d0000 {
1189                         compatible = "starfive,jh7110-pdm";
1190                         reg = <0x0 0x100d0000 0x0 0x1000>;
1191                         reg-names = "pdm";
1192                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1193                                  <&clkgen JH7110_PDM_CLK_APB>,
1194                                  <&clkgen JH7110_MCLK>,
1195                                  <&mclk_ext>;
1196                         clock-names = "pdm_mclk",
1197                                       "pdm_apb", "clk_mclk",
1198                                       "mclk_ext";
1199                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1200                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1201                         reset-names = "pdm_dmic", "pdm_apb";
1202                         #sound-dai-cells = <0>;
1203                 };
1204
1205                 i2srx_mst: i2srx_mst@100e0000 {
1206                         compatible = "starfive,jh7110-i2srx-master";
1207                         reg = <0x0 0x100e0000 0x0 0x1000>;
1208                         clocks = <&clkgen JH7110_APB0>,
1209                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1210                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1211                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1212                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1213                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1214                                  <&clkgen JH7110_MCLK>,
1215                                  <&mclk_ext>;
1216                         clock-names = "apb0", "i2srx_apb",
1217                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1218                                       "i2srx_bclk", "i2srx_lrck",
1219                                       "mclk", "mclk_ext";
1220                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1221                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1222                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1223                         dmas = <&dma 24 1>;
1224                         dma-names = "rx";
1225                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1226                         #sound-dai-cells = <0>;
1227                         status = "disabled";
1228                 };
1229
1230                 i2srx_3ch: i2srx_3ch@100e0000 {
1231                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1232                         reg = <0x0 0x100e0000 0x0 0x1000>;
1233                         clocks = <&clkgen JH7110_APB0>,
1234                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1235                                  <&clkgen JH7110_AUDIO_ROOT>,
1236                                  <&clkgen JH7110_MCLK_INNER>,
1237                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1238                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1239                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1240                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1241                                  <&clkgen JH7110_MCLK>,
1242                                  <&mclk_ext>,
1243                                  <&i2srx_bclk_ext>,
1244                                  <&i2srx_lrck_ext>;
1245                         clock-names = "apb0", "3ch-apb",
1246                                       "audioroot", "mclk-inner",
1247                                       "bclk_mst", "3ch-lrck",
1248                                       "rx-bclk", "rx-lrck",
1249                                       "mclk", "mclk_ext",
1250                                       "bclk-ext", "lrck-ext";
1251                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1252                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1253                         dmas = <&dma 24 1>;
1254                         dma-names = "rx";
1255                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1256                         #sound-dai-cells = <0>;
1257                         status = "disabled";
1258                 };
1259
1260                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1261                         compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1262                         reg = <0x0 0x120b0000 0x0 0x1000>;
1263                         clocks = <&clkgen JH7110_MCLK_INNER>,
1264                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1265                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1266                                  <&clkgen JH7110_MCLK>,
1267                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1268                                  <&clkgen JH7110_I2STX0_4CHLRCK>,
1269                                  <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1270                                  <&mclk_ext>;
1271                         clock-names = "inner", "bclk-mst",
1272                                         "lrck-mst", "mclk",
1273                                         "bclk0", "lrck0",
1274                                         "i2s_apb", "mclk_ext";
1275                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1276                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1277                         reset-names = "rst_apb", "rst_bclk";
1278                         dmas = <&dma 47 1>;
1279                         dma-names = "tx";
1280                         #sound-dai-cells = <0>;
1281                         status = "disabled";
1282                 };
1283
1284                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1285                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1286                         reg = <0x0 0x120c0000 0x0 0x1000>;
1287                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1288                                  <&clkgen JH7110_MCLK_INNER>,
1289                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1290                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1291                                  <&clkgen JH7110_MCLK>,
1292                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1293                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1294                                  <&clkgen JH7110_MCLK_OUT>,
1295                                  <&clkgen JH7110_APB0>,
1296                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1297                                  <&mclk_ext>,
1298                                  <&i2stx_bclk_ext>,
1299                                  <&i2stx_lrck_ext>;
1300                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1301                                       "lrck_mst", "mclk", "4chbclk",
1302                                       "4chlrck", "mclk_out",
1303                                       "apb0", "clk_apb",
1304                                       "mclk_ext", "bclk_ext", "lrck_ext";
1305                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1306                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1307                         dmas = <&dma 48 1>;
1308                         dma-names = "tx";
1309                         #sound-dai-cells = <0>;
1310                         status = "disabled";
1311                 };
1312
1313                 ptc: pwm@120d0000 {
1314                         compatible = "starfive,jh7110-pwm";
1315                         reg = <0x0 0x120d0000 0x0 0x10000>;
1316                         reg-names = "control";
1317                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1318                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1319                         starfive,approx-freq = <2000000>;
1320                         #pwm-cells=<3>;
1321                         starfive,npwm = <8>;
1322                         status = "disabled";
1323                 };
1324
1325                 spdif_transmitter: spdif_transmitter {
1326                         compatible = "linux,spdif-dit";
1327                         #sound-dai-cells = <0>;
1328                         status = "disabled";
1329                 };
1330
1331                 pwmdac_codec: pwmdac-transmitter {
1332                         compatible = "starfive,jh7110-pwmdac-dit";
1333                         #sound-dai-cells = <0>;
1334                         status = "disabled";
1335                 };
1336
1337                 dmic_codec: dmic_codec {
1338                         compatible = "dmic-codec";
1339                         #sound-dai-cells = <0>;
1340                         status = "disabled";
1341                 };
1342
1343                 spi0: spi@10060000 {
1344                         compatible = "arm,pl022", "arm,primecell";
1345                         reg = <0x0 0x10060000 0x0 0x10000>;
1346                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1347                         clock-names = "apb_pclk";
1348                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1349                         reset-names = "rst_apb";
1350                         interrupts = <38>;
1351                         /* shortage of dma channel that not be used */
1352                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1353                         /*dma-names = "rx","tx";*/
1354                         arm,primecell-periphid = <0x00041022>;
1355                         num-cs = <1>;
1356                         #address-cells = <1>;
1357                         #size-cells = <0>;
1358                         status = "disabled";
1359                 };
1360
1361                 spi1: spi@10070000 {
1362                         compatible = "arm,pl022", "arm,primecell";
1363                         reg = <0x0 0x10070000 0x0 0x10000>;
1364                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1365                         clock-names = "apb_pclk";
1366                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1367                         reset-names = "rst_apb";
1368                         interrupts = <39>;
1369                         /* shortage of dma channel that not be used */
1370                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1371                         /*dma-names = "rx","tx";*/
1372                         arm,primecell-periphid = <0x00041022>;
1373                         num-cs = <1>;
1374                         #address-cells = <1>;
1375                         #size-cells = <0>;
1376                         status = "disabled";
1377                 };
1378
1379                 spi2: spi@10080000 {
1380                         compatible = "arm,pl022", "arm,primecell";
1381                         reg = <0x0 0x10080000 0x0 0x10000>;
1382                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1383                         clock-names = "apb_pclk";
1384                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1385                         reset-names = "rst_apb";
1386                         interrupts = <40>;
1387                         /* shortage of dma channel that not be used */
1388                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1389                         /*dma-names = "rx","tx";*/
1390                         arm,primecell-periphid = <0x00041022>;
1391                         num-cs = <1>;
1392                         #address-cells = <1>;
1393                         #size-cells = <0>;
1394                         status = "disabled";
1395                 };
1396
1397                 spi3: spi@12070000 {
1398                         compatible = "arm,pl022", "arm,primecell";
1399                         reg = <0x0 0x12070000 0x0 0x10000>;
1400                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1401                         clock-names = "apb_pclk";
1402                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1403                         reset-names = "rst_apb";
1404                         interrupts = <52>;
1405                         /* shortage of dma channel that not be used */
1406                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1407                         /*dma-names = "rx","tx";*/
1408                         arm,primecell-periphid = <0x00041022>;
1409                         num-cs = <1>;
1410                         #address-cells = <1>;
1411                         #size-cells = <0>;
1412                         status = "disabled";
1413                 };
1414
1415                 spi4: spi@12080000 {
1416                         compatible = "arm,pl022", "arm,primecell";
1417                         reg = <0x0 0x12080000 0x0 0x10000>;
1418                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1419                         clock-names = "apb_pclk";
1420                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1421                         reset-names = "rst_apb";
1422                         interrupts = <53>;
1423                         /* shortage of dma channel that not be used */
1424                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1425                         /*dma-names = "rx","tx";*/
1426                         arm,primecell-periphid = <0x00041022>;
1427                         num-cs = <1>;
1428                         #address-cells = <1>;
1429                         #size-cells = <0>;
1430                         status = "disabled";
1431                 };
1432
1433                 spi5: spi@12090000 {
1434                         compatible = "arm,pl022", "arm,primecell";
1435                         reg = <0x0 0x12090000 0x0 0x10000>;
1436                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1437                         clock-names = "apb_pclk";
1438                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1439                         reset-names = "rst_apb";
1440                         interrupts = <54>;
1441                         /* shortage of dma channel that not be used */
1442                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1443                         /*dma-names = "rx","tx";*/
1444                         arm,primecell-periphid = <0x00041022>;
1445                         num-cs = <1>;
1446                         #address-cells = <1>;
1447                         #size-cells = <0>;
1448                         status = "disabled";
1449                 };
1450
1451                 spi6: spi@120A0000 {
1452                         compatible = "arm,pl022", "arm,primecell";
1453                         reg = <0x0 0x120A0000 0x0 0x10000>;
1454                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1455                         clock-names = "apb_pclk";
1456                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1457                         reset-names = "rst_apb";
1458                         interrupts = <55>;
1459                         /* shortage of dma channel that not be used */
1460                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1461                         /*dma-names = "rx","tx";*/
1462                         arm,primecell-periphid = <0x00041022>;
1463                         num-cs = <1>;
1464                         #address-cells = <1>;
1465                         #size-cells = <0>;
1466                         status = "disabled";
1467                 };
1468
1469                 pcie0: pcie@2B000000 {
1470                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1471                         #address-cells = <3>;
1472                         #size-cells = <2>;
1473                         #interrupt-cells = <1>;
1474                         reg = <0x0 0x2B000000 0x0 0x1000000
1475                                0x9 0x40000000 0x0 0x10000000>;
1476                         reg-names = "reg", "config";
1477                         device_type = "pci";
1478                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1479                         starfive,phyctrl = <&phyctrl0 0x28 0x80>;
1480                         bus-range = <0x0 0xff>;
1481                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1482                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1483                         msi-parent = <&plic>;
1484                         interrupts = <56>;
1485                         interrupt-controller;
1486                         interrupt-names = "msi";
1487                         interrupt-parent = <&plic>;
1488                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1489                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1490                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1491                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1492                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1493                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1494                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1495                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1496                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1497                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1498                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1499                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1500                                       "rst_brg", "rst_core", "rst_apb";
1501                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1502                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1503                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1504                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1505                         clock-names = "noc", "tl", "axi_mst0", "apb";
1506                         status = "disabled";
1507                 };
1508
1509                 pcie1: pcie@2C000000 {
1510                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1511                         #address-cells = <3>;
1512                         #size-cells = <2>;
1513                         #interrupt-cells = <1>;
1514                         reg = <0x0 0x2C000000 0x0 0x1000000
1515                                0x9 0xc0000000 0x0 0x10000000>;
1516                         reg-names = "reg", "config";
1517                         device_type = "pci";
1518                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1519                         starfive,phyctrl = <&phyctrl1 0x28 0x80>;
1520                         bus-range = <0x0 0xff>;
1521                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1522                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1523                         msi-parent = <&plic>;
1524                         interrupts = <57>;
1525                         interrupt-controller;
1526                         interrupt-names = "msi";
1527                         interrupt-parent = <&plic>;
1528                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1529                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1530                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1531                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1532                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1533                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1534                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1535                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1536                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1537                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1538                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1539                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1540                                       "rst_brg", "rst_core", "rst_apb";
1541                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1542                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1543                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1544                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1545                         clock-names = "noc", "tl", "axi_mst0", "apb";
1546                         status = "disabled";
1547                 };
1548
1549                 mailbox_contrl0: mailbox@0 {
1550                         compatible = "starfive,mail_box";
1551                         reg = <0x0 0x13060000 0x0 0x0001000>;
1552                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1553                         clock-names = "clk_apb";
1554                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1555                         reset-names = "mbx_rre";
1556                         interrupts = <26 27>;
1557                         #mbox-cells = <2>;
1558                         status = "disabled";
1559                 };
1560
1561                 mailbox_client0: mailbox_client@0 {
1562                         compatible = "starfive,mailbox-test";
1563                         mbox-names = "rx", "tx";
1564                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1565                         status = "disabled";
1566                 };
1567
1568                 display: display-subsystem {
1569                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1570                         ports = <&dc_out_dpi0>;
1571                         status = "disabled";
1572                 };
1573
1574                 dssctrl: dssctrl@295B0000 {
1575                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1576                         reg = <0 0x295B0000 0 0x90>;
1577                 };
1578
1579                 tda988x_pin: tda988x_pin {
1580                         compatible = "starfive,tda998x_rgb_pin";
1581                         status = "disabled";
1582                 };
1583
1584                 rgb_output: rgb-output {
1585                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1586                         //verisilicon,dss-syscon = <&dssctrl>;
1587                         //verisilicon,mux-mask = <0x70 0x380>;
1588                         //verisilicon,mux-val = <0x40 0x280>;
1589                         status = "disabled";
1590                 };
1591
1592                 dc8200: dc8200@29400000 {
1593                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1594                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1595                         reg = <0x0 0x29400000 0x0 0x100>,
1596                               <0x0 0x29400800 0x0 0x2000>,
1597                               <0x0 0x17030000 0x0 0x1000>;
1598                         interrupts = <95>;
1599                         status = "disabled";
1600                         clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1601                         <&clkgen JH7110_VOUT_SRC>,
1602                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1603                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1604                         <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1605                         <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1606                         <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1607                         <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1608                         <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1609                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1610                         <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1611                         <&hdmitx0_pixelclk>,
1612                         <&clkvout JH7110_DC8200_PIX0>,
1613                         <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1614                         <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1615                         clock-names = "noc_disp","vout_src",
1616                            "top_vout_axi","top_vout_ahb",
1617                            "pix_clk","vout_pix1",
1618                            "axi_clk","core_clk","vout_ahb",
1619                            "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1620                            "dc8200_pix0_out","dc8200_pix1_out";
1621                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1622                                  <&rstgen RSTN_U0_DC8200_AXI>,
1623                                  <&rstgen RSTN_U0_DC8200_AHB>,
1624                                  <&rstgen RSTN_U0_DC8200_CORE>,
1625                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
1626                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1627                                         "rst_noc_disp";
1628                 };
1629
1630                 dsi_output: dsi-output {
1631                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1632                         status = "disabled";
1633                 };
1634
1635                 mipi_dphy: mipi-dphy@295e0000{
1636                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1637                         reg = <0x0 0x295e0000 0x0 0x10000>;
1638                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1639                         clock-names = "dphy_txesc";
1640                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1641                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1642                         reset-names = "dphy_sys", "dphy_txbytehs";
1643                         #phy-cells = <0>;
1644                         status = "disabled";
1645                 };
1646
1647                  mipi_dsi: mipi@295d0000 {
1648                         compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1649                         reg = <0x0 0x295d0000 0x0 0x10000>;
1650                         interrupts = <98>;
1651                         reg-names = "dsi";
1652                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1653                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1654                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1655                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1656                         clock-names = "sys", "apb", "txesc", "dpi";
1657                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1658                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1659                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1660                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1661                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1662                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1663                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1664                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1665                         phys = <&mipi_dphy>;
1666                         phy-names = "dphy";
1667                         status = "disabled";
1668
1669                         port {
1670                                 dsi_out_port: endpoint@0 {
1671                                         remote-endpoint = <&panel_dsi_port>;
1672                                 };
1673                                 dsi_in_port: endpoint@1 {
1674                                         remote-endpoint = <&mipi_out>;
1675                                 };
1676                         };
1677
1678                         mipi_panel: panel@0 {
1679                                 /*compatible = "";*/
1680                                 status = "okay";
1681                         };
1682                 };
1683
1684                 hdmi: hdmi@29590000 {
1685                         compatible = "starfive,jh7110-hdmi","inno,hdmi";
1686                         reg = <0x0 0x29590000 0x0 0x4000>;
1687                         interrupts = <99>;
1688                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1689                         /*clocks = <&cru  PCLK_HDMI>;*/
1690                         /*clock-names = "pclk";*/
1691                         /*pinctrl-names = "default";*/
1692                         /*pinctrl-0 = <&hdmi_ctl>;*/
1693                         status = "disabled";
1694                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1695                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1696                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1697                                  <&hdmitx0_pixelclk>;
1698                         clock-names = "sysclk", "mclk","bclk","pclk";
1699                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1700                         reset-names = "hdmi_tx";
1701                         #sound-dai-cells = <0>;
1702                 };
1703
1704                 sound0: snd-card0 {
1705                         compatible = "simple-audio-card";
1706                         simple-audio-card,name = "Starfive-AC108-Sound-Card";
1707                         #address-cells = <1>;
1708                         #size-cells = <0>;
1709                 };
1710
1711                 sound1: snd-card1 {
1712                         compatible = "simple-audio-card";
1713                         simple-audio-card,name = "Starfive-HDMI-Sound-Card";
1714                         #address-cells = <1>;
1715                         #size-cells = <0>;
1716                 };
1717
1718                 sound2: snd-card2 {
1719                         compatible = "simple-audio-card";
1720                         simple-audio-card,name = "Starfive-PDM-Sound-Card";
1721                         #address-cells = <1>;
1722                         #size-cells = <0>;
1723                 };
1724
1725                 sound3: snd-card3 {
1726                         compatible = "simple-audio-card";
1727                         simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
1728                         #address-cells = <1>;
1729                         #size-cells = <0>;
1730                 };
1731
1732                 sound4: snd-card4 {
1733                         compatible = "simple-audio-card";
1734                         simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
1735                         #address-cells = <1>;
1736                         #size-cells = <0>;
1737                 };
1738
1739                 sound5: snd-card5 {
1740                         compatible = "simple-audio-card";
1741                         simple-audio-card,name = "Starfive-TDM-Sound-Card";
1742                         #address-cells = <1>;
1743                         #size-cells = <0>;
1744                 };
1745
1746                 sound6: snd-card6 {
1747                         compatible = "simple-audio-card";
1748                         simple-audio-card,name = "Starfive-WM8960-Sound-Card";
1749                         #address-cells = <1>;
1750                         #size-cells = <0>;
1751                 };
1752
1753                 co_process: e24@0 {
1754                         compatible = "starfive,e24";
1755                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1756                                 <0x0 0xc0111000 0x0 0x0001f000>;
1757                         reg-names = "ecmd", "espace";
1758                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1759                                  <&clkgen JH7110_E2_CLK_CORE>,
1760                                  <&clkgen JH7110_E2_CLK_DBG>;
1761                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1762                         resets = <&rstgen RSTN_U0_E24_CORE>;
1763                         reset-names = "e24_core";
1764                         starfive,stg-syscon = <&stg_syscon>;
1765                         interrupt-parent = <&plic>;
1766                         firmware-name = "e24_elf";
1767                         irq-mode = <1>;
1768                         mbox-names = "tx", "rx";
1769                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1770                         #address-cells = <1>;
1771                         #size-cells = <1>;
1772                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1773                         status = "disabled";
1774                         dsp@0 {};
1775                 };
1776
1777                 xrp: xrp@0 {
1778                         compatible = "cdns,xrp";
1779                         reg = <0x0  0x10230000 0x0 0x00010000
1780                                 0x0  0x10240000 0x0 0x00010000>;
1781                         memory-region = <&xrp_reserved>;
1782                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1783                         clock-names = "core_clk";
1784                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1785                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1786                         reset-names = "rst_core","rst_axi";
1787                         starfive,stg-syscon = <&stg_syscon>;
1788                         firmware-name = "hifi4_elf";
1789                         #address-cells = <1>;
1790                         #size-cells = <1>;
1791                         ranges = <0x40000000 0x0 0x20000000 0x040000
1792                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1793                         status = "disabled";
1794                         dsp@0 {
1795                         };
1796                 };
1797
1798                 starfive_cpufreq: starfive,jh7110-cpufreq {
1799                         compatible = "starfive,jh7110-cpufreq";
1800                         clocks = <&clkgen JH7110_CPU_CORE>;
1801                         clock-names = "cpu_clk";
1802                 };
1803         };
1804 };