arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
   9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
  10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
  11
  12 / {
  13         compatible = "starfive,jh7110";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 S7_0: cpu@0 {
  22                         compatible = "sifive,s7", "riscv";
  23                         reg = <0>;
  24                         d-cache-block-size = <64>;
  25                         d-cache-sets = <64>;
  26                         d-cache-size = <8192>;
  27                         d-tlb-sets = <1>;
  28                         d-tlb-size = <40>;
  29                         device_type = "cpu";
  30                         i-cache-block-size = <64>;
  31                         i-cache-sets = <64>;
  32                         i-cache-size = <16384>;
  33                         i-tlb-sets = <1>;
  34                         i-tlb-size = <40>;
  35                         mmu-type = "riscv,sv39";
  36                         next-level-cache = <&ccache>;
  37                         riscv,isa = "rv64imac_zba_zbb";
  38                         tlb-split;
  39                         status = "disabled";
  40
  41                         cpu0_intc: interrupt-controller {
  42                                 compatible = "riscv,cpu-intc";
  43                                 interrupt-controller;
  44                                 #interrupt-cells = <1>;
  45                         };
  46                 };
  47
  48                 U74_1: cpu@1 {
  49                         compatible = "sifive,u74-mc", "riscv";
  50                         reg = <1>;
  51                         d-cache-block-size = <64>;
  52                         d-cache-sets = <64>;
  53                         d-cache-size = <32768>;
  54                         d-tlb-sets = <1>;
  55                         d-tlb-size = <40>;
  56                         device_type = "cpu";
  57                         i-cache-block-size = <64>;
  58                         i-cache-sets = <64>;
  59                         i-cache-size = <32768>;
  60                         i-tlb-sets = <1>;
  61                         i-tlb-size = <40>;
  62                         mmu-type = "riscv,sv39";
  63                         next-level-cache = <&ccache>;
  64                         riscv,isa = "rv64imafdc_zba_zbb";
  65                         tlb-split;
  66
  67                         cpu1_intc: interrupt-controller {
  68                                 compatible = "riscv,cpu-intc";
  69                                 interrupt-controller;
  70                                 #interrupt-cells = <1>;
  71                         };
  72                 };
  73
  74                 U74_2: cpu@2 {
  75                         compatible = "sifive,u74-mc", "riscv";
  76                         reg = <2>;
  77                         d-cache-block-size = <64>;
  78                         d-cache-sets = <64>;
  79                         d-cache-size = <32768>;
  80                         d-tlb-sets = <1>;
  81                         d-tlb-size = <40>;
  82                         device_type = "cpu";
  83                         i-cache-block-size = <64>;
  84                         i-cache-sets = <64>;
  85                         i-cache-size = <32768>;
  86                         i-tlb-sets = <1>;
  87                         i-tlb-size = <40>;
  88                         mmu-type = "riscv,sv39";
  89                         next-level-cache = <&ccache>;
  90                         riscv,isa = "rv64imafdc_zba_zbb";
  91                         tlb-split;
  92
  93                         cpu2_intc: interrupt-controller {
  94                                 compatible = "riscv,cpu-intc";
  95                                 interrupt-controller;
  96                                 #interrupt-cells = <1>;
  97                         };
  98                 };
  99
 100                 U74_3: cpu@3 {
 101                         compatible = "sifive,u74-mc", "riscv";
 102                         reg = <3>;
 103                         d-cache-block-size = <64>;
 104                         d-cache-sets = <64>;
 105                         d-cache-size = <32768>;
 106                         d-tlb-sets = <1>;
 107                         d-tlb-size = <40>;
 108                         device_type = "cpu";
 109                         i-cache-block-size = <64>;
 110                         i-cache-sets = <64>;
 111                         i-cache-size = <32768>;
 112                         i-tlb-sets = <1>;
 113                         i-tlb-size = <40>;
 114                         mmu-type = "riscv,sv39";
 115                         next-level-cache = <&ccache>;
 116                         riscv,isa = "rv64imafdc_zba_zbb";
 117                         tlb-split;
 118
 119                         cpu3_intc: interrupt-controller {
 120                                 compatible = "riscv,cpu-intc";
 121                                 interrupt-controller;
 122                                 #interrupt-cells = <1>;
 123                         };
 124                 };
 125
 126                 U74_4: cpu@4 {
 127                         compatible = "sifive,u74-mc", "riscv";
 128                         reg = <4>;
 129                         d-cache-block-size = <64>;
 130                         d-cache-sets = <64>;
 131                         d-cache-size = <32768>;
 132                         d-tlb-sets = <1>;
 133                         d-tlb-size = <40>;
 134                         device_type = "cpu";
 135                         i-cache-block-size = <64>;
 136                         i-cache-sets = <64>;
 137                         i-cache-size = <32768>;
 138                         i-tlb-sets = <1>;
 139                         i-tlb-size = <40>;
 140                         mmu-type = "riscv,sv39";
 141                         next-level-cache = <&ccache>;
 142                         riscv,isa = "rv64imafdc_zba_zbb";
 143                         tlb-split;
 144
 145                         cpu4_intc: interrupt-controller {
 146                                 compatible = "riscv,cpu-intc";
 147                                 interrupt-controller;
 148                                 #interrupt-cells = <1>;
 149                         };
 150                 };
 151
 152                 cpu-map {
 153                         cluster0 {
 154                                 core0 {
 155                                         cpu = <&S7_0>;
 156                                 };
 157
 158                                 core1 {
 159                                         cpu = <&U74_1>;
 160                                 };
 161
 162                                 core2 {
 163                                         cpu = <&U74_2>;
 164                                 };
 165
 166                                 core3 {
 167                                         cpu = <&U74_3>;
 168                                 };
 169
 170                                 core4 {
 171                                         cpu = <&U74_4>;
 172                                 };
 173                         };
 174                 };
 175         };
 176
 177         dvp_clk: dvp-clock {
 178                 compatible = "fixed-clock";
 179                 clock-output-names = "dvp_clk";
 180                 #clock-cells = <0>;
 181         };
 182
 183         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 184                 compatible = "fixed-clock";
 185                 clock-output-names = "gmac0_rgmii_rxin";
 186                 #clock-cells = <0>;
 187         };
 188
 189         gmac0_rmii_refin: gmac0-rmii-refin-clock {
 190                 compatible = "fixed-clock";
 191                 clock-output-names = "gmac0_rmii_refin";
 192                 #clock-cells = <0>;
 193         };
 194
 195         gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 196                 compatible = "fixed-clock";
 197                 clock-output-names = "gmac1_rgmii_rxin";
 198                 #clock-cells = <0>;
 199         };
 200
 201         gmac1_rmii_refin: gmac1-rmii-refin-clock {
 202                 compatible = "fixed-clock";
 203                 clock-output-names = "gmac1_rmii_refin";
 204                 #clock-cells = <0>;
 205         };
 206
 207         hdmitx0_pixelclk: hdmitx0-pixel-clock {
 208                 compatible = "fixed-clock";
 209                 clock-output-names = "hdmitx0_pixelclk";
 210                 #clock-cells = <0>;
 211         };
 212
 213         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 214                 compatible = "fixed-clock";
 215                 clock-output-names = "i2srx_bclk_ext";
 216                 #clock-cells = <0>;
 217         };
 218
 219         i2srx_lrck_ext: i2srx-lrck-ext-clock {
 220                 compatible = "fixed-clock";
 221                 clock-output-names = "i2srx_lrck_ext";
 222                 #clock-cells = <0>;
 223         };
 224
 225         i2stx_bclk_ext: i2stx-bclk-ext-clock {
 226                 compatible = "fixed-clock";
 227                 clock-output-names = "i2stx_bclk_ext";
 228                 #clock-cells = <0>;
 229         };
 230
 231         i2stx_lrck_ext: i2stx-lrck-ext-clock {
 232                 compatible = "fixed-clock";
 233                 clock-output-names = "i2stx_lrck_ext";
 234                 #clock-cells = <0>;
 235         };
 236
 237         mclk_ext: mclk-ext-clock {
 238                 compatible = "fixed-clock";
 239                 clock-output-names = "mclk_ext";
 240                 #clock-cells = <0>;
 241         };
 242
 243         osc: oscillator {
 244                 compatible = "fixed-clock";
 245                 clock-output-names = "osc";
 246                 #clock-cells = <0>;
 247         };
 248
 249         rtc_osc: rtc-oscillator {
 250                 compatible = "fixed-clock";
 251                 clock-output-names = "rtc_osc";
 252                 #clock-cells = <0>;
 253         };
 254
 255         stmmac_axi_setup: stmmac-axi-config {
 256                 snps,lpi_en;
 257                 snps,wr_osr_lmt = <4>;
 258                 snps,rd_osr_lmt = <4>;
 259                 snps,blen = <256 128 64 32 0 0 0>;
 260         };
 261
 262         tdm_ext: tdm-ext-clock {
 263                 compatible = "fixed-clock";
 264                 clock-output-names = "tdm_ext";
 265                 #clock-cells = <0>;
 266         };
 267
 268         soc {
 269                 compatible = "simple-bus";
 270                 interrupt-parent = <&plic>;
 271                 #address-cells = <2>;
 272                 #size-cells = <2>;
 273                 ranges;
 274
 275                 clint: timer@2000000 {
 276                         compatible = "starfive,jh7110-clint", "sifive,clint0";
 277                         reg = <0x0 0x2000000 0x0 0x10000>;
 278                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 279                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 280                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 281                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 282                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 283                 };
 284
 285                 ccache: cache-controller@2010000 {
 286                         compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
 287                         reg = <0x0 0x2010000 0x0 0x4000>;
 288                         interrupts = <1>, <3>, <4>, <2>;
 289                         cache-block-size = <64>;
 290                         cache-level = <2>;
 291                         cache-sets = <2048>;
 292                         cache-size = <2097152>;
 293                         cache-unified;
 294                 };
 295
 296                 plic: interrupt-controller@c000000 {
 297                         compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 298                         reg = <0x0 0xc000000 0x0 0x4000000>;
 299                         interrupts-extended = <&cpu0_intc 11>,
 300                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 301                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 302                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 303                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 304                         interrupt-controller;
 305                         #interrupt-cells = <1>;
 306                         #address-cells = <0>;
 307                         riscv,ndev = <136>;
 308                 };
 309
 310                 uart0: serial@10000000 {
 311                         compatible = "snps,dw-apb-uart";
 312                         reg = <0x0 0x10000000 0x0 0x10000>;
 313                         clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
 314                                  <&syscrg JH7110_SYSCLK_UART0_APB>;
 315                         clock-names = "baudclk", "apb_pclk";
 316                         resets = <&syscrg JH7110_SYSRST_UART0_APB>;
 317                         interrupts = <32>;
 318                         reg-io-width = <4>;
 319                         reg-shift = <2>;
 320                         status = "disabled";
 321                 };
 322
 323                 uart1: serial@10010000 {
 324                         compatible = "snps,dw-apb-uart";
 325                         reg = <0x0 0x10010000 0x0 0x10000>;
 326                         clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
 327                                  <&syscrg JH7110_SYSCLK_UART1_APB>;
 328                         clock-names = "baudclk", "apb_pclk";
 329                         resets = <&syscrg JH7110_SYSRST_UART1_APB>;
 330                         interrupts = <33>;
 331                         reg-io-width = <4>;
 332                         reg-shift = <2>;
 333                         status = "disabled";
 334                 };
 335
 336                 uart2: serial@10020000 {
 337                         compatible = "snps,dw-apb-uart";
 338                         reg = <0x0 0x10020000 0x0 0x10000>;
 339                         clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
 340                                  <&syscrg JH7110_SYSCLK_UART2_APB>;
 341                         clock-names = "baudclk", "apb_pclk";
 342                         resets = <&syscrg JH7110_SYSRST_UART2_APB>;
 343                         interrupts = <34>;
 344                         reg-io-width = <4>;
 345                         reg-shift = <2>;
 346                         status = "disabled";
 347                 };
 348
 349                 i2c0: i2c@10030000 {
 350                         compatible = "snps,designware-i2c";
 351                         reg = <0x0 0x10030000 0x0 0x10000>;
 352                         clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
 353                         clock-names = "ref";
 354                         resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
 355                         interrupts = <35>;
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         status = "disabled";
 359                 };
 360
 361                 i2c1: i2c@10040000 {
 362                         compatible = "snps,designware-i2c";
 363                         reg = <0x0 0x10040000 0x0 0x10000>;
 364                         clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
 365                         clock-names = "ref";
 366                         resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
 367                         interrupts = <36>;
 368                         #address-cells = <1>;
 369                         #size-cells = <0>;
 370                         status = "disabled";
 371                 };
 372
 373                 i2c2: i2c@10050000 {
 374                         compatible = "snps,designware-i2c";
 375                         reg = <0x0 0x10050000 0x0 0x10000>;
 376                         clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
 377                         clock-names = "ref";
 378                         resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
 379                         interrupts = <37>;
 380                         #address-cells = <1>;
 381                         #size-cells = <0>;
 382                         status = "disabled";
 383                 };
 384
 385                 stgcrg: clock-controller@10230000 {
 386                         compatible = "starfive,jh7110-stgcrg";
 387                         reg = <0x0 0x10230000 0x0 0x10000>;
 388                         clocks = <&osc>,
 389                                  <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
 390                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 391                                  <&syscrg JH7110_SYSCLK_USB_125M>,
 392                                  <&syscrg JH7110_SYSCLK_CPU_BUS>,
 393                                  <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
 394                                  <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
 395                                  <&syscrg JH7110_SYSCLK_APB_BUS>;
 396                         clock-names = "osc", "hifi4_core",
 397                                       "stg_axiahb", "usb_125m",
 398                                       "cpu_bus", "hifi4_axi",
 399                                       "nocstg_bus", "apb_bus";
 400                         #clock-cells = <1>;
 401                         #reset-cells = <1>;
 402                 };
 403
 404                 stg_syscon: syscon@10240000 {
 405                         compatible = "starfive,jh7110-stg-syscon", "syscon";
 406                         reg = <0x0 0x10240000 0x0 0x1000>;
 407                 };
 408
 409                 uart3: serial@12000000 {
 410                         compatible = "snps,dw-apb-uart";
 411                         reg = <0x0 0x12000000 0x0 0x10000>;
 412                         clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
 413                                  <&syscrg JH7110_SYSCLK_UART3_APB>;
 414                         clock-names = "baudclk", "apb_pclk";
 415                         resets = <&syscrg JH7110_SYSRST_UART3_APB>;
 416                         interrupts = <45>;
 417                         reg-io-width = <4>;
 418                         reg-shift = <2>;
 419                         status = "disabled";
 420                 };
 421
 422                 uart4: serial@12010000 {
 423                         compatible = "snps,dw-apb-uart";
 424                         reg = <0x0 0x12010000 0x0 0x10000>;
 425                         clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
 426                                  <&syscrg JH7110_SYSCLK_UART4_APB>;
 427                         clock-names = "baudclk", "apb_pclk";
 428                         resets = <&syscrg JH7110_SYSRST_UART4_APB>;
 429                         interrupts = <46>;
 430                         reg-io-width = <4>;
 431                         reg-shift = <2>;
 432                         status = "disabled";
 433                 };
 434
 435                 uart5: serial@12020000 {
 436                         compatible = "snps,dw-apb-uart";
 437                         reg = <0x0 0x12020000 0x0 0x10000>;
 438                         clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
 439                                  <&syscrg JH7110_SYSCLK_UART5_APB>;
 440                         clock-names = "baudclk", "apb_pclk";
 441                         resets = <&syscrg JH7110_SYSRST_UART5_APB>;
 442                         interrupts = <47>;
 443                         reg-io-width = <4>;
 444                         reg-shift = <2>;
 445                         status = "disabled";
 446                 };
 447
 448                 i2c3: i2c@12030000 {
 449                         compatible = "snps,designware-i2c";
 450                         reg = <0x0 0x12030000 0x0 0x10000>;
 451                         clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
 452                         clock-names = "ref";
 453                         resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
 454                         interrupts = <48>;
 455                         #address-cells = <1>;
 456                         #size-cells = <0>;
 457                         status = "disabled";
 458                 };
 459
 460                 i2c4: i2c@12040000 {
 461                         compatible = "snps,designware-i2c";
 462                         reg = <0x0 0x12040000 0x0 0x10000>;
 463                         clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
 464                         clock-names = "ref";
 465                         resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
 466                         interrupts = <49>;
 467                         #address-cells = <1>;
 468                         #size-cells = <0>;
 469                         status = "disabled";
 470                 };
 471
 472                 i2c5: i2c@12050000 {
 473                         compatible = "snps,designware-i2c";
 474                         reg = <0x0 0x12050000 0x0 0x10000>;
 475                         clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
 476                         clock-names = "ref";
 477                         resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
 478                         interrupts = <50>;
 479                         #address-cells = <1>;
 480                         #size-cells = <0>;
 481                         status = "disabled";
 482                 };
 483
 484                 i2c6: i2c@12060000 {
 485                         compatible = "snps,designware-i2c";
 486                         reg = <0x0 0x12060000 0x0 0x10000>;
 487                         clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
 488                         clock-names = "ref";
 489                         resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
 490                         interrupts = <51>;
 491                         #address-cells = <1>;
 492                         #size-cells = <0>;
 493                         status = "disabled";
 494                 };
 495
 496                 ptc: pwm@120d0000 {
 497                         compatible = "starfive,jh7110-pwm";
 498                         reg = <0x0 0x120d0000 0x0 0x10000>;
 499                         clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
 500                         resets = <&syscrg JH7110_SYSRST_PWM_APB>;
 501                         #pwm-cells=<3>;
 502                         status = "disabled";
 503                 };
 504
 505                 sfctemp: temperature-sensor@120e0000 {
 506                         compatible = "starfive,jh7110-temp";
 507                         reg = <0x0 0x120e0000 0x0 0x10000>;
 508                         clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
 509                                  <&syscrg JH7110_SYSCLK_TEMP_APB>;
 510                         clock-names = "sense", "bus";
 511                         resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
 512                                  <&syscrg JH7110_SYSRST_TEMP_APB>;
 513                         reset-names = "sense", "bus";
 514                         #thermal-sensor-cells = <0>;
 515                 };
 516
 517                 qspi: spi@13010000 {
 518                         compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
 519                         #address-cells = <1>;
 520                         #size-cells = <0>;
 521                         reg = <0x0 0x13010000 0x0 0x10000
 522                                0x0 0x21000000 0x0 0x400000>;
 523                         interrupts = <25>;
 524                         clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
 525                         resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 526                                  <&syscrg JH7110_SYSRST_QSPI_AHB>,
 527                                  <&syscrg JH7110_SYSRST_QSPI_REF>;
 528                         reset-names = "qspi", "qspi-ocp", "rstc_ref";
 529                         cdns,fifo-depth = <256>;
 530                         cdns,fifo-width = <4>;
 531                         cdns,trigger-address = <0x0>;
 532
 533                         nor_flash: nor-flash@0 {
 534                                 compatible = "jedec,spi-nor";
 535                                 reg=<0>;
 536                                 cdns,read-delay = <5>;
 537                                 spi-max-frequency = <12000000>;
 538                                 cdns,tshsl-ns = <1>;
 539                                 cdns,tsd2d-ns = <1>;
 540                                 cdns,tchsh-ns = <1>;
 541                                 cdns,tslch-ns = <1>;
 542
 543                                 partitions {
 544                                         compatible = "fixed-partitions";
 545                                         #address-cells = <1>;
 546                                         #size-cells = <1>;
 547
 548                                         spl@0 {
 549                                                 reg = <0x0 0x20000>;
 550                                         };
 551                                         uboot@100000 {
 552                                                 reg = <0x100000 0x300000>;
 553                                         };
 554                                         data@f00000 {
 555                                                 reg = <0xf00000 0x100000>;
 556                                         };
 557                                 };
 558                         };
 559                 };
 560
 561                 syscrg: clock-controller@13020000 {
 562                         compatible = "starfive,jh7110-syscrg";
 563                         reg = <0x0 0x13020000 0x0 0x10000>;
 564                         clocks = <&osc>, <&gmac1_rmii_refin>,
 565                                  <&gmac1_rgmii_rxin>,
 566                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 567                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 568                                  <&tdm_ext>, <&mclk_ext>,
 569                                  <&pllclk JH7110_CLK_PLL0_OUT>,
 570                                  <&pllclk JH7110_CLK_PLL1_OUT>,
 571                                  <&pllclk JH7110_CLK_PLL2_OUT>;
 572                         clock-names = "osc", "gmac1_rmii_refin",
 573                                       "gmac1_rgmii_rxin",
 574                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
 575                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
 576                                       "tdm_ext", "mclk_ext",
 577                                       "pll0_out", "pll1_out", "pll2_out";
 578                         #clock-cells = <1>;
 579                         #reset-cells = <1>;
 580                 };
 581
 582                 sys_syscon: syscon@13030000 {
 583                         compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 584                         reg = <0x0 0x13030000 0x0 0x1000>;
 585
 586                         pllclk: pll-clock-controller {
 587                                 compatible = "starfive,jh7110-pll";
 588                                 clocks = <&osc>;
 589                                 #clock-cells = <1>;
 590                         };
 591                 };
 592
 593                 sysgpio: pinctrl@13040000 {
 594                         compatible = "starfive,jh7110-sys-pinctrl";
 595                         reg = <0x0 0x13040000 0x0 0x10000>;
 596                         clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
 597                         resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
 598                         interrupts = <86>;
 599                         interrupt-controller;
 600                         #interrupt-cells = <2>;
 601                         gpio-controller;
 602                         #gpio-cells = <2>;
 603                 };
 604
 605                 timer@13050000 {
 606                         compatible = "starfive,jh7110-timer";
 607                         reg = <0x0 0x13050000 0x0 0x10000>;
 608                         interrupts = <69>, <70>, <71> ,<72>;
 609                         clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
 610                                  <&syscrg JH7110_SYSCLK_TIMER0>,
 611                                  <&syscrg JH7110_SYSCLK_TIMER1>,
 612                                  <&syscrg JH7110_SYSCLK_TIMER2>,
 613                                  <&syscrg JH7110_SYSCLK_TIMER3>;
 614                         clock-names = "apb", "ch0", "ch1",
 615                                       "ch2", "ch3";
 616                         resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
 617                                  <&syscrg JH7110_SYSRST_TIMER0>,
 618                                  <&syscrg JH7110_SYSRST_TIMER1>,
 619                                  <&syscrg JH7110_SYSRST_TIMER2>,
 620                                  <&syscrg JH7110_SYSRST_TIMER3>;
 621                         reset-names = "apb", "ch0", "ch1",
 622                                       "ch2", "ch3";
 623                 };
 624
 625                 wdog: watchdog@13070000 {
 626                         compatible = "starfive,jh7110-wdt";
 627                         reg = <0x0 0x13070000 0x0 0x10000>;
 628                         clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
 629                                  <&syscrg JH7110_SYSCLK_WDT_CORE>;
 630                         clock-names = "apb", "core";
 631                         resets = <&syscrg JH7110_SYSRST_WDT_APB>,
 632                                  <&syscrg JH7110_SYSRST_WDT_CORE>;
 633                 };
 634
 635                 crypto: crypto@16000000 {
 636                         compatible = "starfive,jh7110-crypto";
 637                         reg = <0x0 0x16000000 0x0 0x4000>;
 638                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 639                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 640                         clock-names = "hclk", "ahb";
 641                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 642                         dmas = <&sdma 1 2>, <&sdma 0 2>;
 643                         dma-names = "tx", "rx";
 644                 };
 645
 646                 sdma: dma@16008000 {
 647                         compatible = "arm,pl080", "arm,primecell";
 648                         arm,primecell-periphid = <0x00041080>;
 649                         reg = <0x0 0x16008000 0x0 0x4000>;
 650                         interrupts = <29>;
 651                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 652                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 653                         clock-names = "hclk", "apb_pclk";
 654                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 655                         lli-bus-interface-ahb1;
 656                         mem-bus-interface-ahb1;
 657                         memcpy-burst-size = <256>;
 658                         memcpy-bus-width = <32>;
 659                         #dma-cells = <2>;
 660                 };
 661
 662                 rng: rng@1600c000 {
 663                         compatible = "starfive,jh7110-trng";
 664                         reg = <0x0 0x1600C000 0x0 0x4000>;
 665                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 666                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 667                         clock-names = "hclk", "ahb";
 668                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 669                         interrupts = <30>;
 670                 };
 671
 672                 mmc0: mmc@16010000 {
 673                         compatible = "starfive,jh7110-mmc";
 674                         reg = <0x0 0x16010000 0x0 0x10000>;
 675                         clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 676                                  <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 677                         clock-names = "biu","ciu";
 678                         resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 679                         reset-names = "reset";
 680                         interrupts = <74>;
 681                         fifo-depth = <32>;
 682                         fifo-watermark-aligned;
 683                         data-addr = <0>;
 684                         starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 685                         status = "disabled";
 686                 };
 687
 688                 mmc1: mmc@16020000 {
 689                         compatible = "starfive,jh7110-mmc";
 690                         reg = <0x0 0x16020000 0x0 0x10000>;
 691                         clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 692                                  <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 693                         clock-names = "biu","ciu";
 694                         resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 695                         reset-names = "reset";
 696                         interrupts = <75>;
 697                         fifo-depth = <32>;
 698                         fifo-watermark-aligned;
 699                         data-addr = <0>;
 700                         starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 701                         status = "disabled";
 702                 };
 703
 704                 gmac0: ethernet@16030000 {
 705                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 706                         reg = <0x0 0x16030000 0x0 0x10000>;
 707                         clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
 708                                  <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
 709                                  <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
 710                                  <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
 711                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
 712                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 713                                       "tx", "gtx";
 714                         resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
 715                                  <&aoncrg JH7110_AONRST_GMAC0_AHB>;
 716                         reset-names = "stmmaceth", "ahb";
 717                         interrupts = <7>, <6>, <5>;
 718                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 719                         snps,multicast-filter-bins = <64>;
 720                         snps,perfect-filter-entries = <8>;
 721                         rx-fifo-depth = <2048>;
 722                         tx-fifo-depth = <2048>;
 723                         snps,fixed-burst;
 724                         snps,no-pbl-x8;
 725                         snps,force_thresh_dma_mode;
 726                         snps,axi-config = <&stmmac_axi_setup>;
 727                         snps,tso;
 728                         snps,en-tx-lpi-clockgating;
 729                         snps,txpbl = <16>;
 730                         snps,rxpbl = <16>;
 731                         starfive,syscon = <&aon_syscon 0xc 0x12>;
 732                         status = "disabled";
 733                 };
 734
 735                 gmac1: ethernet@16040000 {
 736                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 737                         reg = <0x0 0x16040000 0x0 0x10000>;
 738                         clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
 739                                  <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
 740                                  <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
 741                                  <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
 742                                  <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
 743                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 744                                       "tx", "gtx";
 745                         resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
 746                                  <&syscrg JH7110_SYSRST_GMAC1_AHB>;
 747                         reset-names = "stmmaceth", "ahb";
 748                         interrupts = <78>, <77>, <76>;
 749                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 750                         snps,multicast-filter-bins = <64>;
 751                         snps,perfect-filter-entries = <8>;
 752                         rx-fifo-depth = <2048>;
 753                         tx-fifo-depth = <2048>;
 754                         snps,fixed-burst;
 755                         snps,no-pbl-x8;
 756                         snps,force_thresh_dma_mode;
 757                         snps,axi-config = <&stmmac_axi_setup>;
 758                         snps,tso;
 759                         snps,en-tx-lpi-clockgating;
 760                         snps,txpbl = <16>;
 761                         snps,rxpbl = <16>;
 762                         starfive,syscon = <&sys_syscon 0x90 0x2>;
 763                         status = "disabled";
 764                 };
 765
 766                 dma: dma-controller@16050000 {
 767                         compatible = "starfive,jh7110-axi-dma";
 768                         reg = <0x0 0x16050000 0x0 0x10000>;
 769                         clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
 770                                  <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
 771                         clock-names = "core-clk", "cfgr-clk";
 772                         resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
 773                                  <&stgcrg JH7110_STGRST_DMA1P_AHB>;
 774                         interrupts = <73>;
 775                         #dma-cells = <1>;
 776                         dma-channels = <4>;
 777                         snps,dma-masters = <1>;
 778                         snps,data-width = <3>;
 779                         snps,block-size = <65536 65536 65536 65536>;
 780                         snps,priority = <0 1 2 3>;
 781                         snps,axi-max-burst-len = <16>;
 782                 };
 783
 784                 aoncrg: clock-controller@17000000 {
 785                         compatible = "starfive,jh7110-aoncrg";
 786                         reg = <0x0 0x17000000 0x0 0x10000>;
 787                         clocks = <&osc>, <&gmac0_rmii_refin>,
 788                                  <&gmac0_rgmii_rxin>,
 789                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 790                                  <&syscrg JH7110_SYSCLK_APB_BUS>,
 791                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
 792                                  <&rtc_osc>;
 793                         clock-names = "osc", "gmac0_rmii_refin",
 794                                       "gmac0_rgmii_rxin", "stg_axiahb",
 795                                       "apb_bus", "gmac0_gtxclk",
 796                                       "rtc_osc";
 797                         #clock-cells = <1>;
 798                         #reset-cells = <1>;
 799                 };
 800
 801                 aon_syscon: syscon@17010000 {
 802                         compatible = "starfive,jh7110-aon-syscon", "syscon";
 803                         reg = <0x0 0x17010000 0x0 0x1000>;
 804                 };
 805
 806                 aongpio: pinctrl@17020000 {
 807                         compatible = "starfive,jh7110-aon-pinctrl";
 808                         reg = <0x0 0x17020000 0x0 0x10000>;
 809                         resets = <&aoncrg JH7110_AONRST_IOMUX>;
 810                         interrupts = <85>;
 811                         interrupt-controller;
 812                         #interrupt-cells = <2>;
 813                         gpio-controller;
 814                         #gpio-cells = <2>;
 815                 };
 816
 817                 pwrc: power-controller@17030000 {
 818                         compatible = "starfive,jh7110-pmu";
 819                         reg = <0x0 0x17030000 0x0 0x10000>;
 820                         interrupts = <111>;
 821                         #power-domain-cells = <1>;
 822                 };
 823
 824                 ispcrg: clock-controller@19810000 {
 825                         compatible = "starfive,jh7110-ispcrg";
 826                         reg = <0x0 0x19810000 0x0 0x10000>;
 827                         clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
 828                                  <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
 829                                  <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
 830                                  <&dvp_clk>;
 831                         clock-names = "isp_top_core", "isp_top_axi",
 832                                       "noc_bus_isp_axi", "dvp_clk";
 833                         resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
 834                                  <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
 835                                  <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
 836                         #clock-cells = <1>;
 837                         #reset-cells = <1>;
 838                         power-domains = <&pwrc JH7110_PD_ISP>;
 839                 };
 840
 841                 voutcrg: clock-controller@295c0000 {
 842                         compatible = "starfive,jh7110-voutcrg";
 843                         reg = <0x0 0x295c0000 0x0 0x10000>;
 844                         clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
 845                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
 846                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
 847                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
 848                                  <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
 849                                  <&hdmitx0_pixelclk>;
 850                         clock-names = "vout_src", "vout_top_ahb",
 851                                       "vout_top_axi", "vout_top_hdmitx0_mclk",
 852                                       "i2stx0_bclk", "hdmitx0_pixelclk";
 853                         resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
 854                         #clock-cells = <1>;
 855                         #reset-cells = <1>;
 856                         power-domains = <&pwrc JH7110_PD_VOUT>;
 857                 };
 858         };
 859 };