arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
   9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
  10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
  11 #include <dt-bindings/thermal/thermal.h>
  12
  13 / {
  14         compatible = "starfive,jh7110";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 S7_0: cpu@0 {
  23                         compatible = "sifive,s7", "riscv";
  24                         reg = <0>;
  25                         device_type = "cpu";
  26                         i-cache-block-size = <64>;
  27                         i-cache-sets = <64>;
  28                         i-cache-size = <16384>;
  29                         next-level-cache = <&ccache>;
  30                         riscv,isa = "rv64imac_zba_zbb";
  31                         status = "disabled";
  32
  33                         cpu0_intc: interrupt-controller {
  34                                 compatible = "riscv,cpu-intc";
  35                                 interrupt-controller;
  36                                 #interrupt-cells = <1>;
  37                         };
  38                 };
  39
  40                 U74_1: cpu@1 {
  41                         compatible = "sifive,u74-mc", "riscv";
  42                         reg = <1>;
  43                         d-cache-block-size = <64>;
  44                         d-cache-sets = <64>;
  45                         d-cache-size = <32768>;
  46                         d-tlb-sets = <1>;
  47                         d-tlb-size = <40>;
  48                         device_type = "cpu";
  49                         i-cache-block-size = <64>;
  50                         i-cache-sets = <64>;
  51                         i-cache-size = <32768>;
  52                         i-tlb-sets = <1>;
  53                         i-tlb-size = <40>;
  54                         mmu-type = "riscv,sv39";
  55                         next-level-cache = <&ccache>;
  56                         riscv,isa = "rv64imafdc_zba_zbb";
  57                         tlb-split;
  58                         operating-points-v2 = <&cpu_opp>;
  59                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
  60                         clock-names = "cpu";
  61                         #cooling-cells = <2>;
  62
  63                         cpu1_intc: interrupt-controller {
  64                                 compatible = "riscv,cpu-intc";
  65                                 interrupt-controller;
  66                                 #interrupt-cells = <1>;
  67                         };
  68                 };
  69
  70                 U74_2: cpu@2 {
  71                         compatible = "sifive,u74-mc", "riscv";
  72                         reg = <2>;
  73                         d-cache-block-size = <64>;
  74                         d-cache-sets = <64>;
  75                         d-cache-size = <32768>;
  76                         d-tlb-sets = <1>;
  77                         d-tlb-size = <40>;
  78                         device_type = "cpu";
  79                         i-cache-block-size = <64>;
  80                         i-cache-sets = <64>;
  81                         i-cache-size = <32768>;
  82                         i-tlb-sets = <1>;
  83                         i-tlb-size = <40>;
  84                         mmu-type = "riscv,sv39";
  85                         next-level-cache = <&ccache>;
  86                         riscv,isa = "rv64imafdc_zba_zbb";
  87                         tlb-split;
  88                         operating-points-v2 = <&cpu_opp>;
  89                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
  90                         clock-names = "cpu";
  91                         #cooling-cells = <2>;
  92
  93                         cpu2_intc: interrupt-controller {
  94                                 compatible = "riscv,cpu-intc";
  95                                 interrupt-controller;
  96                                 #interrupt-cells = <1>;
  97                         };
  98                 };
  99
 100                 U74_3: cpu@3 {
 101                         compatible = "sifive,u74-mc", "riscv";
 102                         reg = <3>;
 103                         d-cache-block-size = <64>;
 104                         d-cache-sets = <64>;
 105                         d-cache-size = <32768>;
 106                         d-tlb-sets = <1>;
 107                         d-tlb-size = <40>;
 108                         device_type = "cpu";
 109                         i-cache-block-size = <64>;
 110                         i-cache-sets = <64>;
 111                         i-cache-size = <32768>;
 112                         i-tlb-sets = <1>;
 113                         i-tlb-size = <40>;
 114                         mmu-type = "riscv,sv39";
 115                         next-level-cache = <&ccache>;
 116                         riscv,isa = "rv64imafdc_zba_zbb";
 117                         tlb-split;
 118                         operating-points-v2 = <&cpu_opp>;
 119                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 120                         clock-names = "cpu";
 121                         #cooling-cells = <2>;
 122
 123                         cpu3_intc: interrupt-controller {
 124                                 compatible = "riscv,cpu-intc";
 125                                 interrupt-controller;
 126                                 #interrupt-cells = <1>;
 127                         };
 128                 };
 129
 130                 U74_4: cpu@4 {
 131                         compatible = "sifive,u74-mc", "riscv";
 132                         reg = <4>;
 133                         d-cache-block-size = <64>;
 134                         d-cache-sets = <64>;
 135                         d-cache-size = <32768>;
 136                         d-tlb-sets = <1>;
 137                         d-tlb-size = <40>;
 138                         device_type = "cpu";
 139                         i-cache-block-size = <64>;
 140                         i-cache-sets = <64>;
 141                         i-cache-size = <32768>;
 142                         i-tlb-sets = <1>;
 143                         i-tlb-size = <40>;
 144                         mmu-type = "riscv,sv39";
 145                         next-level-cache = <&ccache>;
 146                         riscv,isa = "rv64imafdc_zba_zbb";
 147                         tlb-split;
 148                         operating-points-v2 = <&cpu_opp>;
 149                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 150                         clock-names = "cpu";
 151                         #cooling-cells = <2>;
 152
 153                         cpu4_intc: interrupt-controller {
 154                                 compatible = "riscv,cpu-intc";
 155                                 interrupt-controller;
 156                                 #interrupt-cells = <1>;
 157                         };
 158                 };
 159
 160                 cpu-map {
 161                         cluster0 {
 162                                 core0 {
 163                                         cpu = <&S7_0>;
 164                                 };
 165
 166                                 core1 {
 167                                         cpu = <&U74_1>;
 168                                 };
 169
 170                                 core2 {
 171                                         cpu = <&U74_2>;
 172                                 };
 173
 174                                 core3 {
 175                                         cpu = <&U74_3>;
 176                                 };
 177
 178                                 core4 {
 179                                         cpu = <&U74_4>;
 180                                 };
 181                         };
 182                 };
 183         };
 184
 185         cpu_opp: opp-table-0 {
 186                         compatible = "operating-points-v2";
 187                         opp-shared;
 188                         opp-375000000 {
 189                                         opp-hz = /bits/ 64 <375000000>;
 190                                         opp-microvolt = <800000>;
 191                         };
 192                         opp-500000000 {
 193                                         opp-hz = /bits/ 64 <500000000>;
 194                                         opp-microvolt = <800000>;
 195                         };
 196                         opp-750000000 {
 197                                         opp-hz = /bits/ 64 <750000000>;
 198                                         opp-microvolt = <800000>;
 199                         };
 200                         opp-1500000000 {
 201                                         opp-hz = /bits/ 64 <1500000000>;
 202                                         opp-microvolt = <1040000>;
 203                         };
 204         };
 205
 206         thermal-zones {
 207                 cpu-thermal {
 208                         polling-delay-passive = <250>;
 209                         polling-delay = <15000>;
 210
 211                         thermal-sensors = <&sfctemp>;
 212
 213                         cooling-maps {
 214                                 map0 {
 215                                         trip = <&cpu_alert0>;
 216                                         cooling-device =
 217                                                 <&U74_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 218                                                 <&U74_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 219                                                 <&U74_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 220                                                 <&U74_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 221                                 };
 222                         };
 223
 224                         trips {
 225                                 cpu_alert0: cpu_alert0 {
 226                                         /* milliCelsius */
 227                                         temperature = <85000>;
 228                                         hysteresis = <2000>;
 229                                         type = "passive";
 230                                 };
 231
 232                                 cpu_crit {
 233                                         /* milliCelsius */
 234                                         temperature = <100000>;
 235                                         hysteresis = <2000>;
 236                                         type = "critical";
 237                                 };
 238                         };
 239                 };
 240         };
 241
 242         dvp_clk: dvp-clock {
 243                 compatible = "fixed-clock";
 244                 clock-output-names = "dvp_clk";
 245                 #clock-cells = <0>;
 246         };
 247         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 248                 compatible = "fixed-clock";
 249                 clock-output-names = "gmac0_rgmii_rxin";
 250                 #clock-cells = <0>;
 251         };
 252
 253         gmac0_rmii_refin: gmac0-rmii-refin-clock {
 254                 compatible = "fixed-clock";
 255                 clock-output-names = "gmac0_rmii_refin";
 256                 #clock-cells = <0>;
 257         };
 258
 259         gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 260                 compatible = "fixed-clock";
 261                 clock-output-names = "gmac1_rgmii_rxin";
 262                 #clock-cells = <0>;
 263         };
 264
 265         gmac1_rmii_refin: gmac1-rmii-refin-clock {
 266                 compatible = "fixed-clock";
 267                 clock-output-names = "gmac1_rmii_refin";
 268                 #clock-cells = <0>;
 269         };
 270
 271         hdmitx0_pixelclk: hdmitx0-pixel-clock {
 272                 compatible = "fixed-clock";
 273                 clock-output-names = "hdmitx0_pixelclk";
 274                 #clock-cells = <0>;
 275         };
 276
 277         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 278                 compatible = "fixed-clock";
 279                 clock-output-names = "i2srx_bclk_ext";
 280                 #clock-cells = <0>;
 281         };
 282
 283         i2srx_lrck_ext: i2srx-lrck-ext-clock {
 284                 compatible = "fixed-clock";
 285                 clock-output-names = "i2srx_lrck_ext";
 286                 #clock-cells = <0>;
 287         };
 288
 289         i2stx_bclk_ext: i2stx-bclk-ext-clock {
 290                 compatible = "fixed-clock";
 291                 clock-output-names = "i2stx_bclk_ext";
 292                 #clock-cells = <0>;
 293         };
 294
 295         i2stx_lrck_ext: i2stx-lrck-ext-clock {
 296                 compatible = "fixed-clock";
 297                 clock-output-names = "i2stx_lrck_ext";
 298                 #clock-cells = <0>;
 299         };
 300
 301         mclk_ext: mclk-ext-clock {
 302                 compatible = "fixed-clock";
 303                 clock-output-names = "mclk_ext";
 304                 #clock-cells = <0>;
 305         };
 306
 307         osc: oscillator {
 308                 compatible = "fixed-clock";
 309                 clock-output-names = "osc";
 310                 #clock-cells = <0>;
 311         };
 312
 313         rtc_osc: rtc-oscillator {
 314                 compatible = "fixed-clock";
 315                 clock-output-names = "rtc_osc";
 316                 #clock-cells = <0>;
 317         };
 318
 319         stmmac_axi_setup: stmmac-axi-config {
 320                 snps,lpi_en;
 321                 snps,wr_osr_lmt = <15>;
 322                 snps,rd_osr_lmt = <15>;
 323                 snps,blen = <256 128 64 32 0 0 0>;
 324         };
 325
 326         tdm_ext: tdm-ext-clock {
 327                 compatible = "fixed-clock";
 328                 clock-output-names = "tdm_ext";
 329                 #clock-cells = <0>;
 330         };
 331
 332         display: display-subsystem {
 333                 compatible = "starfive,display-subsystem";
 334
 335                 clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>,
 336                         <&voutcrg JH7110_VOUTCLK_DC8200_CORE>,
 337                         <&voutcrg JH7110_VOUTCLK_DC8200_AXI>,
 338                         <&voutcrg JH7110_VOUTCLK_DC8200_AHB>;
 339                 clock-names = "noc_bus", "dc_core", "axi_core", "ahb";
 340                 resets = <&voutcrg JH7110_VOUTRST_DC8200_AXI>,
 341                          <&voutcrg JH7110_VOUTRST_DC8200_AHB>,
 342                          <&voutcrg JH7110_VOUTRST_DC8200_CORE>;
 343                 reset-names = "axi","ahb", "core";
 344         };
 345
 346         dsi_encoder: dsi_encoder {
 347                 compatible = "starfive,dsi-encoder";
 348                 starfive,syscon = <&vout_syscon 0x8 0x08>;
 349         };
 350         soc {
 351                 compatible = "simple-bus";
 352                 interrupt-parent = <&plic>;
 353                 #address-cells = <2>;
 354                 #size-cells = <2>;
 355                 ranges;
 356
 357                 clint: timer@2000000 {
 358                         compatible = "starfive,jh7110-clint", "sifive,clint0";
 359                         reg = <0x0 0x2000000 0x0 0x10000>;
 360                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 361                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 362                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 363                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 364                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 365                 };
 366
 367                 ccache: cache-controller@2010000 {
 368                         compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
 369                         reg = <0x0 0x2010000 0x0 0x4000>;
 370                         interrupts = <1>, <3>, <4>, <2>;
 371                         cache-block-size = <64>;
 372                         cache-level = <2>;
 373                         cache-sets = <2048>;
 374                         cache-size = <2097152>;
 375                         cache-unified;
 376                 };
 377
 378                 plic: interrupt-controller@c000000 {
 379                         compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 380                         reg = <0x0 0xc000000 0x0 0x4000000>;
 381                         interrupts-extended = <&cpu0_intc 11>,
 382                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 383                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 384                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 385                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 386                         interrupt-controller;
 387                         #interrupt-cells = <1>;
 388                         #address-cells = <0>;
 389                         riscv,ndev = <136>;
 390                 };
 391
 392                 uart0: serial@10000000 {
 393                         compatible = "snps,dw-apb-uart";
 394                         reg = <0x0 0x10000000 0x0 0x10000>;
 395                         clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
 396                                  <&syscrg JH7110_SYSCLK_UART0_APB>;
 397                         clock-names = "baudclk", "apb_pclk";
 398                         resets = <&syscrg JH7110_SYSRST_UART0_APB>;
 399                         interrupts = <32>;
 400                         reg-io-width = <4>;
 401                         reg-shift = <2>;
 402                         status = "disabled";
 403                 };
 404
 405                 uart1: serial@10010000 {
 406                         compatible = "snps,dw-apb-uart";
 407                         reg = <0x0 0x10010000 0x0 0x10000>;
 408                         clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
 409                                  <&syscrg JH7110_SYSCLK_UART1_APB>;
 410                         clock-names = "baudclk", "apb_pclk";
 411                         resets = <&syscrg JH7110_SYSRST_UART1_APB>;
 412                         interrupts = <33>;
 413                         reg-io-width = <4>;
 414                         reg-shift = <2>;
 415                         status = "disabled";
 416                 };
 417
 418                 uart2: serial@10020000 {
 419                         compatible = "snps,dw-apb-uart";
 420                         reg = <0x0 0x10020000 0x0 0x10000>;
 421                         clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
 422                                  <&syscrg JH7110_SYSCLK_UART2_APB>;
 423                         clock-names = "baudclk", "apb_pclk";
 424                         resets = <&syscrg JH7110_SYSRST_UART2_APB>;
 425                         interrupts = <34>;
 426                         reg-io-width = <4>;
 427                         reg-shift = <2>;
 428                         status = "disabled";
 429                 };
 430
 431                 i2c0: i2c@10030000 {
 432                         compatible = "snps,designware-i2c";
 433                         reg = <0x0 0x10030000 0x0 0x10000>;
 434                         clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
 435                         clock-names = "ref";
 436                         resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
 437                         interrupts = <35>;
 438                         #address-cells = <1>;
 439                         #size-cells = <0>;
 440                         status = "disabled";
 441                 };
 442
 443                 i2c1: i2c@10040000 {
 444                         compatible = "snps,designware-i2c";
 445                         reg = <0x0 0x10040000 0x0 0x10000>;
 446                         clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
 447                         clock-names = "ref";
 448                         resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
 449                         interrupts = <36>;
 450                         #address-cells = <1>;
 451                         #size-cells = <0>;
 452                         status = "disabled";
 453                 };
 454
 455                 i2c2: i2c@10050000 {
 456                         compatible = "snps,designware-i2c";
 457                         reg = <0x0 0x10050000 0x0 0x10000>;
 458                         clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
 459                         clock-names = "ref";
 460                         resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
 461                         interrupts = <37>;
 462                         #address-cells = <1>;
 463                         #size-cells = <0>;
 464                         status = "disabled";
 465                 };
 466
 467                 spi0: spi@10060000 {
 468                         compatible = "arm,pl022", "arm,primecell";
 469                         reg = <0x0 0x10060000 0x0 0x10000>;
 470                         clocks = <&syscrg JH7110_SYSCLK_SPI0_APB>,
 471                                  <&syscrg JH7110_SYSCLK_SPI0_APB>;
 472                         clock-names = "sspclk", "apb_pclk";
 473                         resets = <&syscrg JH7110_SYSRST_SPI0_APB>;
 474                         interrupts = <38>;
 475                         arm,primecell-periphid = <0x00041022>;
 476                         num-cs = <1>;
 477                         #address-cells = <1>;
 478                         #size-cells = <0>;
 479                         status = "disabled";
 480                 };
 481
 482                 spi1: spi@10070000 {
 483                         compatible = "arm,pl022", "arm,primecell";
 484                         reg = <0x0 0x10070000 0x0 0x10000>;
 485                         clocks = <&syscrg JH7110_SYSCLK_SPI1_APB>,
 486                                  <&syscrg JH7110_SYSCLK_SPI1_APB>;
 487                         clock-names = "sspclk", "apb_pclk";
 488                         resets = <&syscrg JH7110_SYSRST_SPI1_APB>;
 489                         interrupts = <39>;
 490                         arm,primecell-periphid = <0x00041022>;
 491                         num-cs = <1>;
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                         status = "disabled";
 495                 };
 496
 497                 spi2: spi@10080000 {
 498                         compatible = "arm,pl022", "arm,primecell";
 499                         reg = <0x0 0x10080000 0x0 0x10000>;
 500                         clocks = <&syscrg JH7110_SYSCLK_SPI2_APB>,
 501                                  <&syscrg JH7110_SYSCLK_SPI2_APB>;
 502                         clock-names = "sspclk", "apb_pclk";
 503                         resets = <&syscrg JH7110_SYSRST_SPI2_APB>;
 504                         interrupts = <40>;
 505                         arm,primecell-periphid = <0x00041022>;
 506                         num-cs = <1>;
 507                         #address-cells = <1>;
 508                         #size-cells = <0>;
 509                         status = "disabled";
 510                 };
 511
 512                 tdm: tdm@10090000 {
 513                         compatible = "starfive,jh7110-tdm";
 514                         reg = <0x0 0x10090000 0x0 0x1000>;
 515                         clocks = <&syscrg JH7110_SYSCLK_TDM_AHB>,
 516                                  <&syscrg JH7110_SYSCLK_TDM_APB>,
 517                                  <&syscrg JH7110_SYSCLK_TDM_INTERNAL>,
 518                                  <&syscrg JH7110_SYSCLK_TDM_TDM>,
 519                                  <&syscrg JH7110_SYSCLK_MCLK_INNER>,
 520                                  <&tdm_ext>;
 521                         clock-names = "tdm_ahb", "tdm_apb",
 522                                       "tdm_internal", "tdm",
 523                                       "mclk_inner", "tdm_ext";
 524                         resets = <&syscrg JH7110_SYSRST_TDM_AHB>,
 525                                  <&syscrg JH7110_SYSRST_TDM_APB>,
 526                                  <&syscrg JH7110_SYSRST_TDM_CORE>;
 527                         dmas = <&dma 20>, <&dma 21>;
 528                         dma-names = "rx","tx";
 529                         #sound-dai-cells = <0>;
 530                         status = "disabled";
 531                 };
 532
 533                 pwmdac: pwmdac@100b0000 {
 534                         compatible = "starfive,jh7110-pwmdac";
 535                         reg = <0x0 0x100b0000 0x0 0x1000>;
 536                         clocks = <&syscrg JH7110_SYSCLK_PWMDAC_APB>,
 537                                  <&syscrg JH7110_SYSCLK_PWMDAC_CORE>;
 538                         clock-names = "apb", "core";
 539                         resets = <&syscrg JH7110_SYSRST_PWMDAC_APB>;
 540                         dmas = <&dma 22>;
 541                         dma-names = "tx";
 542                         #sound-dai-cells = <0>;
 543                         status = "disabled";
 544                 };
 545
 546                 i2srx: i2s@100e0000 {
 547                         compatible = "starfive,jh7110-i2srx";
 548                         reg = <0x0 0x100e0000 0x0 0x1000>;
 549                         clocks = <&syscrg JH7110_SYSCLK_I2SRX_BCLK_MST>,
 550                                  <&syscrg JH7110_SYSCLK_I2SRX_APB>,
 551                                  <&syscrg JH7110_SYSCLK_MCLK>,
 552                                  <&syscrg JH7110_SYSCLK_MCLK_INNER>,
 553                                  <&mclk_ext>,
 554                                  <&syscrg JH7110_SYSCLK_I2SRX_BCLK>,
 555                                  <&syscrg JH7110_SYSCLK_I2SRX_LRCK>,
 556                                  <&i2srx_bclk_ext>,
 557                                  <&i2srx_lrck_ext>;
 558                         clock-names = "i2sclk", "apb", "mclk",
 559                                       "mclk_inner", "mclk_ext", "bclk",
 560                                       "lrck", "bclk_ext", "lrck_ext";
 561                         resets = <&syscrg JH7110_SYSRST_I2SRX_APB>,
 562                                  <&syscrg JH7110_SYSRST_I2SRX_BCLK>;
 563                         dmas = <0>, <&dma 24>;
 564                         dma-names = "tx", "rx";
 565                         starfive,syscon = <&sys_syscon 0x18 0x2>;
 566                         #sound-dai-cells = <0>;
 567                         status = "disabled";
 568                 };
 569
 570                 usb0: usb@10100000 {
 571                         compatible = "starfive,jh7110-usb";
 572                         ranges = <0x0 0x0 0x10100000 0x100000>;
 573                         #address-cells = <1>;
 574                         #size-cells = <1>;
 575                         starfive,stg-syscon = <&stg_syscon 0x4>;
 576                         starfive,sys-syscon = <&sys_syscon 0x18>;
 577                         clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
 578                                  <&stgcrg JH7110_STGCLK_USB0_STB>,
 579                                  <&stgcrg JH7110_STGCLK_USB0_APB>,
 580                                  <&stgcrg JH7110_STGCLK_USB0_AXI>,
 581                                  <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
 582                         clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
 583                         resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
 584                                  <&stgcrg JH7110_STGRST_USB0_APB>,
 585                                  <&stgcrg JH7110_STGRST_USB0_AXI>,
 586                                  <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
 587                         reset-names = "pwrup", "apb", "axi", "utmi_apb";
 588                         status = "disabled";
 589
 590                         usb_cdns3: usb@0 {
 591                                 compatible = "cdns,usb3";
 592                                 reg = <0x0 0x10000>,
 593                                       <0x10000 0x10000>,
 594                                       <0x20000 0x10000>;
 595                                 reg-names = "otg", "xhci", "dev";
 596                                 interrupts = <100>, <108>, <110>;
 597                                 interrupt-names = "host", "peripheral", "otg";
 598                                 phys = <&usbphy0>;
 599                                 phy-names = "cdns3,usb2-phy";
 600                         };
 601                 };
 602
 603                 usbphy0: phy@10200000 {
 604                         compatible = "starfive,jh7110-usb-phy";
 605                         reg = <0x0 0x10200000 0x0 0x10000>;
 606                         clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
 607                                  <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 608                         clock-names = "125m", "app_125m";
 609                         #phy-cells = <0>;
 610                 };
 611
 612                 pciephy0: phy@10210000 {
 613                         compatible = "starfive,jh7110-pcie-phy";
 614                         reg = <0x0 0x10210000 0x0 0x10000>;
 615                         #phy-cells = <0>;
 616                 };
 617
 618                 pciephy1: phy@10220000 {
 619                         compatible = "starfive,jh7110-pcie-phy";
 620                         reg = <0x0 0x10220000 0x0 0x10000>;
 621                         #phy-cells = <0>;
 622                 };
 623
 624                 stgcrg: clock-controller@10230000 {
 625                         compatible = "starfive,jh7110-stgcrg";
 626                         reg = <0x0 0x10230000 0x0 0x10000>;
 627                         clocks = <&osc>,
 628                                  <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
 629                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 630                                  <&syscrg JH7110_SYSCLK_USB_125M>,
 631                                  <&syscrg JH7110_SYSCLK_CPU_BUS>,
 632                                  <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
 633                                  <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
 634                                  <&syscrg JH7110_SYSCLK_APB_BUS>;
 635                         clock-names = "osc", "hifi4_core",
 636                                       "stg_axiahb", "usb_125m",
 637                                       "cpu_bus", "hifi4_axi",
 638                                       "nocstg_bus", "apb_bus";
 639                         #clock-cells = <1>;
 640                         #reset-cells = <1>;
 641                 };
 642
 643                 stg_syscon: syscon@10240000 {
 644                         compatible = "starfive,jh7110-stg-syscon", "syscon";
 645                         reg = <0x0 0x10240000 0x0 0x1000>;
 646                 };
 647
 648                 uart3: serial@12000000 {
 649                         compatible = "snps,dw-apb-uart";
 650                         reg = <0x0 0x12000000 0x0 0x10000>;
 651                         clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
 652                                  <&syscrg JH7110_SYSCLK_UART3_APB>;
 653                         clock-names = "baudclk", "apb_pclk";
 654                         resets = <&syscrg JH7110_SYSRST_UART3_APB>;
 655                         interrupts = <45>;
 656                         reg-io-width = <4>;
 657                         reg-shift = <2>;
 658                         status = "disabled";
 659                 };
 660
 661                 uart4: serial@12010000 {
 662                         compatible = "snps,dw-apb-uart";
 663                         reg = <0x0 0x12010000 0x0 0x10000>;
 664                         clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
 665                                  <&syscrg JH7110_SYSCLK_UART4_APB>;
 666                         clock-names = "baudclk", "apb_pclk";
 667                         resets = <&syscrg JH7110_SYSRST_UART4_APB>;
 668                         interrupts = <46>;
 669                         reg-io-width = <4>;
 670                         reg-shift = <2>;
 671                         status = "disabled";
 672                 };
 673
 674                 uart5: serial@12020000 {
 675                         compatible = "snps,dw-apb-uart";
 676                         reg = <0x0 0x12020000 0x0 0x10000>;
 677                         clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
 678                                  <&syscrg JH7110_SYSCLK_UART5_APB>;
 679                         clock-names = "baudclk", "apb_pclk";
 680                         resets = <&syscrg JH7110_SYSRST_UART5_APB>;
 681                         interrupts = <47>;
 682                         reg-io-width = <4>;
 683                         reg-shift = <2>;
 684                         status = "disabled";
 685                 };
 686
 687                 i2c3: i2c@12030000 {
 688                         compatible = "snps,designware-i2c";
 689                         reg = <0x0 0x12030000 0x0 0x10000>;
 690                         clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
 691                         clock-names = "ref";
 692                         resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
 693                         interrupts = <48>;
 694                         #address-cells = <1>;
 695                         #size-cells = <0>;
 696                         status = "disabled";
 697                 };
 698
 699                 i2c4: i2c@12040000 {
 700                         compatible = "snps,designware-i2c";
 701                         reg = <0x0 0x12040000 0x0 0x10000>;
 702                         clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
 703                         clock-names = "ref";
 704                         resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
 705                         interrupts = <49>;
 706                         #address-cells = <1>;
 707                         #size-cells = <0>;
 708                         status = "disabled";
 709                 };
 710
 711                 i2c5: i2c@12050000 {
 712                         compatible = "snps,designware-i2c";
 713                         reg = <0x0 0x12050000 0x0 0x10000>;
 714                         clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
 715                         clock-names = "ref";
 716                         resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
 717                         interrupts = <50>;
 718                         #address-cells = <1>;
 719                         #size-cells = <0>;
 720                         status = "disabled";
 721                 };
 722
 723                 i2c6: i2c@12060000 {
 724                         compatible = "snps,designware-i2c";
 725                         reg = <0x0 0x12060000 0x0 0x10000>;
 726                         clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
 727                         clock-names = "ref";
 728                         resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
 729                         interrupts = <51>;
 730                         #address-cells = <1>;
 731                         #size-cells = <0>;
 732                         status = "disabled";
 733                 };
 734
 735                 spi3: spi@12070000 {
 736                         compatible = "arm,pl022", "arm,primecell";
 737                         reg = <0x0 0x12070000 0x0 0x10000>;
 738                         clocks = <&syscrg JH7110_SYSCLK_SPI3_APB>,
 739                                  <&syscrg JH7110_SYSCLK_SPI3_APB>;
 740                         clock-names = "sspclk", "apb_pclk";
 741                         resets = <&syscrg JH7110_SYSRST_SPI3_APB>;
 742                         interrupts = <52>;
 743                         arm,primecell-periphid = <0x00041022>;
 744                         num-cs = <1>;
 745                         #address-cells = <1>;
 746                         #size-cells = <0>;
 747                         status = "disabled";
 748                 };
 749
 750                 spi4: spi@12080000 {
 751                         compatible = "arm,pl022", "arm,primecell";
 752                         reg = <0x0 0x12080000 0x0 0x10000>;
 753                         clocks = <&syscrg JH7110_SYSCLK_SPI4_APB>,
 754                                  <&syscrg JH7110_SYSCLK_SPI4_APB>;
 755                         clock-names = "sspclk", "apb_pclk";
 756                         resets = <&syscrg JH7110_SYSRST_SPI4_APB>;
 757                         interrupts = <53>;
 758                         arm,primecell-periphid = <0x00041022>;
 759                         num-cs = <1>;
 760                         #address-cells = <1>;
 761                         #size-cells = <0>;
 762                         status = "disabled";
 763                 };
 764
 765                 spi5: spi@12090000 {
 766                         compatible = "arm,pl022", "arm,primecell";
 767                         reg = <0x0 0x12090000 0x0 0x10000>;
 768                         clocks = <&syscrg JH7110_SYSCLK_SPI5_APB>,
 769                                  <&syscrg JH7110_SYSCLK_SPI5_APB>;
 770                         clock-names = "sspclk", "apb_pclk";
 771                         resets = <&syscrg JH7110_SYSRST_SPI5_APB>;
 772                         interrupts = <54>;
 773                         arm,primecell-periphid = <0x00041022>;
 774                         num-cs = <1>;
 775                         #address-cells = <1>;
 776                         #size-cells = <0>;
 777                         status = "disabled";
 778                 };
 779
 780                 spi6: spi@120a0000 {
 781                         compatible = "arm,pl022", "arm,primecell";
 782                         reg = <0x0 0x120A0000 0x0 0x10000>;
 783                         clocks = <&syscrg JH7110_SYSCLK_SPI6_APB>,
 784                                  <&syscrg JH7110_SYSCLK_SPI6_APB>;
 785                         clock-names = "sspclk", "apb_pclk";
 786                         resets = <&syscrg JH7110_SYSRST_SPI6_APB>;
 787                         interrupts = <55>;
 788                         arm,primecell-periphid = <0x00041022>;
 789                         num-cs = <1>;
 790                         #address-cells = <1>;
 791                         #size-cells = <0>;
 792                         status = "disabled";
 793                 };
 794
 795                 i2stx0: i2s@120b0000 {
 796                         compatible = "starfive,jh7110-i2stx0";
 797                         reg = <0x0 0x120b0000 0x0 0x1000>;
 798                         clocks = <&syscrg JH7110_SYSCLK_I2STX0_BCLK_MST>,
 799                                  <&syscrg JH7110_SYSCLK_I2STX0_APB>,
 800                                  <&syscrg JH7110_SYSCLK_MCLK>,
 801                                  <&syscrg JH7110_SYSCLK_MCLK_INNER>,
 802                                  <&mclk_ext>;
 803                         clock-names = "i2sclk", "apb", "mclk",
 804                                       "mclk_inner","mclk_ext";
 805                         resets = <&syscrg JH7110_SYSRST_I2STX0_APB>,
 806                                  <&syscrg JH7110_SYSRST_I2STX0_BCLK>;
 807                         dmas = <&dma 47>;
 808                         dma-names = "tx";
 809                         #sound-dai-cells = <0>;
 810                         status = "disabled";
 811                 };
 812
 813                 i2stx1: i2s@120c0000 {
 814                         compatible = "starfive,jh7110-i2stx1";
 815                         reg = <0x0 0x120c0000 0x0 0x1000>;
 816                         clocks = <&syscrg JH7110_SYSCLK_I2STX1_BCLK_MST>,
 817                                  <&syscrg JH7110_SYSCLK_I2STX1_APB>,
 818                                  <&syscrg JH7110_SYSCLK_MCLK>,
 819                                  <&syscrg JH7110_SYSCLK_MCLK_INNER>,
 820                                  <&mclk_ext>,
 821                                  <&syscrg JH7110_SYSCLK_I2STX1_BCLK>,
 822                                  <&syscrg JH7110_SYSCLK_I2STX1_LRCK>,
 823                                  <&i2stx_bclk_ext>,
 824                                  <&i2stx_lrck_ext>;
 825                         clock-names = "i2sclk", "apb", "mclk",
 826                                       "mclk_inner", "mclk_ext", "bclk",
 827                                       "lrck", "bclk_ext", "lrck_ext";
 828                         resets = <&syscrg JH7110_SYSRST_I2STX1_APB>,
 829                                  <&syscrg JH7110_SYSRST_I2STX1_BCLK>;
 830                         dmas = <&dma 48>;
 831                         dma-names = "tx";
 832                         #sound-dai-cells = <0>;
 833                         status = "disabled";
 834                 };
 835
 836                 sfctemp: temperature-sensor@120e0000 {
 837                         compatible = "starfive,jh7110-temp";
 838                         reg = <0x0 0x120e0000 0x0 0x10000>;
 839                         clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
 840                                  <&syscrg JH7110_SYSCLK_TEMP_APB>;
 841                         clock-names = "sense", "bus";
 842                         resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
 843                                  <&syscrg JH7110_SYSRST_TEMP_APB>;
 844                         reset-names = "sense", "bus";
 845                         #thermal-sensor-cells = <0>;
 846                 };
 847
 848                 qspi: spi@13010000 {
 849                         compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
 850                         reg = <0x0 0x13010000 0x0 0x10000>,
 851                               <0x0 0x21000000 0x0 0x400000>;
 852                         interrupts = <25>;
 853                         clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>,
 854                                  <&syscrg JH7110_SYSCLK_QSPI_AHB>,
 855                                  <&syscrg JH7110_SYSCLK_QSPI_APB>;
 856                         clock-names = "ref", "ahb", "apb";
 857                         resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 858                                  <&syscrg JH7110_SYSRST_QSPI_AHB>,
 859                                  <&syscrg JH7110_SYSRST_QSPI_REF>;
 860                         reset-names = "qspi", "qspi-ocp", "rstc_ref";
 861                         cdns,fifo-depth = <256>;
 862                         cdns,fifo-width = <4>;
 863                         cdns,trigger-address = <0x0>;
 864                         status = "disabled";
 865                 };
 866
 867                 syscrg: clock-controller@13020000 {
 868                         compatible = "starfive,jh7110-syscrg";
 869                         reg = <0x0 0x13020000 0x0 0x10000>;
 870                         clocks = <&osc>, <&gmac1_rmii_refin>,
 871                                  <&gmac1_rgmii_rxin>,
 872                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 873                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 874                                  <&tdm_ext>, <&mclk_ext>,
 875                                  <&pllclk JH7110_PLLCLK_PLL0_OUT>,
 876                                  <&pllclk JH7110_PLLCLK_PLL1_OUT>,
 877                                  <&pllclk JH7110_PLLCLK_PLL2_OUT>;
 878                         clock-names = "osc", "gmac1_rmii_refin",
 879                                       "gmac1_rgmii_rxin",
 880                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
 881                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
 882                                       "tdm_ext", "mclk_ext",
 883                                       "pll0_out", "pll1_out", "pll2_out";
 884                         #clock-cells = <1>;
 885                         #reset-cells = <1>;
 886                 };
 887
 888                 sys_syscon: syscon@13030000 {
 889                         compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 890                         reg = <0x0 0x13030000 0x0 0x1000>;
 891
 892                         pllclk: clock-controller {
 893                                 compatible = "starfive,jh7110-pll";
 894                                 clocks = <&osc>;
 895                                 #clock-cells = <1>;
 896                         };
 897                 };
 898
 899                 sysgpio: pinctrl@13040000 {
 900                         compatible = "starfive,jh7110-sys-pinctrl";
 901                         reg = <0x0 0x13040000 0x0 0x10000>;
 902                         clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
 903                         resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
 904                         interrupts = <86>;
 905                         interrupt-controller;
 906                         #interrupt-cells = <2>;
 907                         gpio-controller;
 908                         #gpio-cells = <2>;
 909                 };
 910
 911                 watchdog@13070000 {
 912                         compatible = "starfive,jh7110-wdt";
 913                         reg = <0x0 0x13070000 0x0 0x10000>;
 914                         clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
 915                                  <&syscrg JH7110_SYSCLK_WDT_CORE>;
 916                         clock-names = "apb", "core";
 917                         resets = <&syscrg JH7110_SYSRST_WDT_APB>,
 918                                  <&syscrg JH7110_SYSRST_WDT_CORE>;
 919                 };
 920
 921                 crypto: crypto@16000000 {
 922                         compatible = "starfive,jh7110-crypto";
 923                         reg = <0x0 0x16000000 0x0 0x4000>;
 924                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 925                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 926                         clock-names = "hclk", "ahb";
 927                         interrupts = <28>;
 928                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 929                         dmas = <&sdma 1 2>, <&sdma 0 2>;
 930                         dma-names = "tx", "rx";
 931                 };
 932
 933                 sdma: dma-controller@16008000 {
 934                         compatible = "arm,pl080", "arm,primecell";
 935                         arm,primecell-periphid = <0x00041080>;
 936                         reg = <0x0 0x16008000 0x0 0x4000>;
 937                         interrupts = <29>;
 938                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>;
 939                         clock-names = "apb_pclk";
 940                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 941                         lli-bus-interface-ahb1;
 942                         mem-bus-interface-ahb1;
 943                         memcpy-burst-size = <256>;
 944                         memcpy-bus-width = <32>;
 945                         #dma-cells = <2>;
 946                 };
 947
 948                 rng: rng@1600c000 {
 949                         compatible = "starfive,jh7110-trng";
 950                         reg = <0x0 0x1600C000 0x0 0x4000>;
 951                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 952                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 953                         clock-names = "hclk", "ahb";
 954                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 955                         interrupts = <30>;
 956                 };
 957
 958                 mmc0: mmc@16010000 {
 959                         compatible = "starfive,jh7110-mmc";
 960                         reg = <0x0 0x16010000 0x0 0x10000>;
 961                         clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 962                                  <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 963                         clock-names = "biu","ciu";
 964                         resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 965                         reset-names = "reset";
 966                         interrupts = <74>;
 967                         fifo-depth = <32>;
 968                         fifo-watermark-aligned;
 969                         data-addr = <0>;
 970                         starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 971                         status = "disabled";
 972                 };
 973
 974                 mmc1: mmc@16020000 {
 975                         compatible = "starfive,jh7110-mmc";
 976                         reg = <0x0 0x16020000 0x0 0x10000>;
 977                         clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 978                                  <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 979                         clock-names = "biu","ciu";
 980                         resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 981                         reset-names = "reset";
 982                         interrupts = <75>;
 983                         fifo-depth = <32>;
 984                         fifo-watermark-aligned;
 985                         data-addr = <0>;
 986                         starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 987                         status = "disabled";
 988                 };
 989
 990                 gmac0: ethernet@16030000 {
 991                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 992                         reg = <0x0 0x16030000 0x0 0x10000>;
 993                         clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
 994                                  <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
 995                                  <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
 996                                  <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
 997                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
 998                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 999                                       "tx", "gtx";
1000                         resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
1001                                  <&aoncrg JH7110_AONRST_GMAC0_AHB>;
1002                         reset-names = "stmmaceth", "ahb";
1003                         interrupts = <7>, <6>, <5>;
1004                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1005                         rx-fifo-depth = <2048>;
1006                         tx-fifo-depth = <2048>;
1007                         snps,multicast-filter-bins = <64>;
1008                         snps,perfect-filter-entries = <256>;
1009                         snps,fixed-burst;
1010                         snps,no-pbl-x8;
1011                         snps,force_thresh_dma_mode;
1012                         snps,axi-config = <&stmmac_axi_setup>;
1013                         snps,tso;
1014                         snps,en-tx-lpi-clockgating;
1015                         snps,txpbl = <16>;
1016                         snps,rxpbl = <16>;
1017                         starfive,syscon = <&aon_syscon 0xc 0x12>;
1018                         status = "disabled";
1019                 };
1020
1021                 gmac1: ethernet@16040000 {
1022                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
1023                         reg = <0x0 0x16040000 0x0 0x10000>;
1024                         clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
1025                                  <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
1026                                  <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
1027                                  <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
1028                                  <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
1029                         clock-names = "stmmaceth", "pclk", "ptp_ref",
1030                                       "tx", "gtx";
1031                         resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
1032                                  <&syscrg JH7110_SYSRST_GMAC1_AHB>;
1033                         reset-names = "stmmaceth", "ahb";
1034                         interrupts = <78>, <77>, <76>;
1035                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1036                         rx-fifo-depth = <2048>;
1037                         tx-fifo-depth = <2048>;
1038                         snps,multicast-filter-bins = <64>;
1039                         snps,perfect-filter-entries = <256>;
1040                         snps,fixed-burst;
1041                         snps,no-pbl-x8;
1042                         snps,force_thresh_dma_mode;
1043                         snps,axi-config = <&stmmac_axi_setup>;
1044                         snps,tso;
1045                         snps,en-tx-lpi-clockgating;
1046                         snps,txpbl = <16>;
1047                         snps,rxpbl = <16>;
1048                         starfive,syscon = <&sys_syscon 0x90 0x2>;
1049                         status = "disabled";
1050                 };
1051
1052                 gpu: gpu@18000000 {
1053                         compatible = "img-gpu";
1054                         reg = <0x0 0x18000000 0x0 0x100000>,
1055                                 <0x0 0x130C000 0x0 0x10000>;
1056                         clocks = <&syscrg JH7110_SYSCLK_GPU_CORE>,
1057                                  <&syscrg JH7110_SYSCLK_GPU_APB>,
1058                                  <&syscrg JH7110_SYSCLK_GPU_RTC_TOGGLE>,
1059                                  <&syscrg JH7110_SYSCLK_GPU_CORE_CLK>,
1060                                  <&syscrg JH7110_SYSCLK_GPU_SYS_CLK>,
1061                                  <&syscrg JH7110_SYSCLK_NOC_BUS_GPU_AXI>;
1062                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1063                                         "clk_core", "clk_sys", "clk_axi";
1064                         resets = <&syscrg JH7110_SYSRST_GPU_APB>,
1065                                  <&syscrg JH7110_SYSRST_GPU_DOMA>;
1066                         reset-names = "rst_apb", "rst_doma";
1067                         power-domains = <&pwrc JH7110_PD_GPUA>;
1068                         interrupts = <82>;
1069                         current-clock = <8000000>;
1070                         status = "disabled";
1071                 };
1072
1073                 jpu: jpu@13090000 {
1074                         compatible = "starfive,jpu";
1075                         reg = <0x0 0x13090000 0x0 0x300>;
1076                         interrupts = <14>;
1077                         clocks = <&syscrg JH7110_SYSCLK_CODAJ12_AXI>,
1078                                  <&syscrg JH7110_SYSCLK_CODAJ12_CORE>,
1079                                  <&syscrg JH7110_SYSCLK_CODAJ12_APB>,
1080                                  <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>;
1081                         clock-names = "axi_clk", "core_clk",
1082                                       "apb_clk", "noc_bus";
1083                         resets = <&syscrg JH7110_SYSRST_CODAJ12_AXI>,
1084                                  <&syscrg JH7110_SYSRST_CODAJ12_CORE>,
1085                                  <&syscrg JH7110_SYSRST_CODAJ12_APB>;
1086                         reset-names = "rst_axi", "rst_core", "rst_apb";
1087                         power-domains = <&pwrc JH7110_PD_VDEC>;
1088                         status = "disabled";
1089                 };
1090
1091                 vpu_dec: vpu_dec@130A0000 {
1092                         compatible = "starfive,vdec";
1093                         reg = <0x0 0x130A0000 0x0 0x10000>;
1094                         interrupts = <13>;
1095                         clocks = <&syscrg JH7110_SYSCLK_WAVE511_AXI>,
1096                                  <&syscrg JH7110_SYSCLK_WAVE511_BPU>,
1097                                  <&syscrg JH7110_SYSCLK_WAVE511_VCE>,
1098                                  <&syscrg JH7110_SYSCLK_WAVE511_APB>,
1099                                  <&syscrg JH7110_SYSCLK_NOC_BUS_VDEC_AXI>;
1100                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
1101                                       "apb_clk", "noc_bus";
1102                         resets = <&syscrg JH7110_SYSRST_WAVE511_AXI>,
1103                                  <&syscrg JH7110_SYSRST_WAVE511_BPU>,
1104                                  <&syscrg JH7110_SYSRST_WAVE511_VCE>,
1105                                  <&syscrg JH7110_SYSRST_WAVE511_APB>,
1106                                  <&syscrg JH7110_SYSRST_AXIMEM0_AXI>;
1107                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
1108                                       "rst_apb", "rst_sram";
1109                         starfive,vdec_noc_ctrl;
1110                         power-domains = <&pwrc JH7110_PD_VDEC>;
1111                         status = "disabled";
1112                 };
1113
1114                 vpu_enc: vpu_enc@130B0000 {
1115                         compatible = "starfive,venc";
1116                         reg = <0x0 0x130B0000 0x0 0x10000>;
1117                         interrupts = <15>;
1118                         clocks = <&syscrg JH7110_SYSCLK_VENC_AXI>,
1119                                  <&syscrg JH7110_SYSCLK_WAVE420L_BPU>,
1120                                  <&syscrg JH7110_SYSCLK_WAVE420L_VCE>,
1121                                  <&syscrg JH7110_SYSCLK_WAVE420L_APB>,
1122                                  <&syscrg JH7110_SYSCLK_NOC_BUS_VENC_AXI>;
1123                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
1124                                       "apb_clk", "noc_bus";
1125                         resets = <&syscrg JH7110_SYSRST_WAVE420L_AXI>,
1126                                  <&syscrg JH7110_SYSRST_WAVE420L_BPU>,
1127                                  <&syscrg JH7110_SYSRST_WAVE420L_VCE>,
1128                                  <&syscrg JH7110_SYSRST_WAVE420L_APB>,
1129                                  <&syscrg JH7110_SYSRST_AXIMEM1_AXI>;
1130                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
1131                                       "rst_apb", "rst_sram";
1132                         starfive,venc_noc_ctrl;
1133                         power-domains = <&pwrc JH7110_PD_VENC>;
1134                         status = "disabled";
1135                 };
1136
1137                 dma: dma-controller@16050000 {
1138                         compatible = "starfive,jh7110-axi-dma";
1139                         reg = <0x0 0x16050000 0x0 0x10000>;
1140                         clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
1141                                  <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
1142                         clock-names = "core-clk", "cfgr-clk";
1143                         resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
1144                                  <&stgcrg JH7110_STGRST_DMA1P_AHB>;
1145                         interrupts = <73>;
1146                         #dma-cells = <1>;
1147                         dma-channels = <4>;
1148                         snps,dma-masters = <1>;
1149                         snps,data-width = <3>;
1150                         snps,block-size = <65536 65536 65536 65536>;
1151                         snps,priority = <0 1 2 3>;
1152                         snps,axi-max-burst-len = <16>;
1153                 };
1154
1155                 aoncrg: clock-controller@17000000 {
1156                         compatible = "starfive,jh7110-aoncrg";
1157                         reg = <0x0 0x17000000 0x0 0x10000>;
1158                         clocks = <&osc>, <&gmac0_rmii_refin>,
1159                                  <&gmac0_rgmii_rxin>,
1160                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
1161                                  <&syscrg JH7110_SYSCLK_APB_BUS>,
1162                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
1163                                  <&rtc_osc>;
1164                         clock-names = "osc", "gmac0_rmii_refin",
1165                                       "gmac0_rgmii_rxin", "stg_axiahb",
1166                                       "apb_bus", "gmac0_gtxclk",
1167                                       "rtc_osc";
1168                         #clock-cells = <1>;
1169                         #reset-cells = <1>;
1170                 };
1171
1172                 aon_syscon: syscon@17010000 {
1173                         compatible = "starfive,jh7110-aon-syscon", "syscon";
1174                         reg = <0x0 0x17010000 0x0 0x1000>;
1175                         #power-domain-cells = <1>;
1176                 };
1177
1178                 aongpio: pinctrl@17020000 {
1179                         compatible = "starfive,jh7110-aon-pinctrl";
1180                         reg = <0x0 0x17020000 0x0 0x10000>;
1181                         resets = <&aoncrg JH7110_AONRST_IOMUX>;
1182                         interrupts = <85>;
1183                         interrupt-controller;
1184                         #interrupt-cells = <2>;
1185                         gpio-controller;
1186                         #gpio-cells = <2>;
1187                 };
1188
1189                 rtc: rtc@17040000 {
1190                         compatible = "starfive,jh7110-rtc";
1191                         reg = <0x0 0x17040000 0x0 0x10000>;
1192                         interrupts = <10>, <11>, <12>;
1193                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
1194                         clocks = <&aoncrg JH7110_AONCLK_RTC_APB>,
1195                                  <&aoncrg JH7110_AONCLK_RTC_CAL>;
1196                         clock-names = "pclk", "cal_clk";
1197                         resets = <&aoncrg JH7110_AONRST_RTC_32K>,
1198                                  <&aoncrg JH7110_AONRST_RTC_APB>,
1199                                  <&aoncrg JH7110_AONRST_RTC_CAL>;
1200                         reset-names = "rst_osc", "rst_apb", "rst_cal";
1201                         rtc,cal-clock-freq = <1000000>;
1202                         status = "okay";
1203                 };
1204
1205                 pwrc: power-controller@17030000 {
1206                         compatible = "starfive,jh7110-pmu";
1207                         reg = <0x0 0x17030000 0x0 0x10000>;
1208                         interrupts = <111>;
1209                         #power-domain-cells = <1>;
1210                 };
1211
1212                 ispcrg: clock-controller@19810000 {
1213                         compatible = "starfive,jh7110-ispcrg";
1214                         reg = <0x0 0x19810000 0x0 0x10000>;
1215                         clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
1216                                  <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
1217                                  <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
1218                                  <&dvp_clk>;
1219                         clock-names = "isp_top_core", "isp_top_axi",
1220                                       "noc_bus_isp_axi", "dvp_clk";
1221                         resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
1222                                  <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
1223                                  <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
1224                         #clock-cells = <1>;
1225                         #reset-cells = <1>;
1226                         power-domains = <&pwrc JH7110_PD_ISP>;
1227                 };
1228
1229                 dc8200: lcd-controller@29400000 {
1230                         compatible = "starfive,jh7110-dc8200";
1231                         reg = <0x0 0x29400000 0x0 0x100>,
1232                               <0x0 0x29400800 0x0 0x2000>;
1233                         interrupts = <95>;
1234                         clocks = <&voutcrg JH7110_VOUTCLK_DC8200_PIX0>,
1235                                 <&voutcrg JH7110_VOUTCLK_DC8200_PIX1>,
1236                                 <&hdmitx0_pixelclk>,
1237                                 <&voutcrg JH7110_VOUTCLK_DC8200_PIX>;
1238                         clock-names = "channel0", "channel1",
1239                                       "hdmi_tx", "dc_parent";
1240                 };
1241
1242                 hdmi: hdmi@29590000 {
1243                         compatible = "starfive,jh7110-inno-hdmi";
1244                         reg = <0x0 0x29590000 0x0 0x4000>;
1245                         interrupts = <99>;
1246
1247                         clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
1248                                  <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
1249                                  <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>;
1250                         clock-names = "sysclk", "mclk", "bclk";
1251                         resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
1252                         #sound-dai-cells = <0>;
1253                 };
1254
1255                 pcie0: pcie@2B000000 {
1256                         compatible = "starfive,jh7110-pcie";
1257                         #address-cells = <3>;
1258                         #size-cells = <2>;
1259                         #interrupt-cells = <1>;
1260                         reg = <0x0 0x2B000000 0x0 0x1000000
1261                                0x9 0x40000000 0x0 0x10000000>;
1262                         reg-names = "reg", "config";
1263                         device_type = "pci";
1264                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1265                         bus-range = <0x0 0xff>;
1266                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1267                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1268                         interrupts = <56>;
1269                         interrupt-parent = <&plic>;
1270                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1271                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
1272                                         <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
1273                                         <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
1274                                         <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
1275                         msi-parent = <&pcie0>;
1276                         msi-controller;
1277                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1278                                  <&stgcrg JH7110_STGCLK_PCIE0_TL>,
1279                                  <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
1280                                  <&stgcrg JH7110_STGCLK_PCIE0_APB>;
1281                         clock-names = "noc", "tl", "axi_mst0", "apb";
1282                         resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
1283                                  <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
1284                                  <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
1285                                  <&stgcrg JH7110_STGRST_PCIE0_BRG>,
1286                                  <&stgcrg JH7110_STGRST_PCIE0_CORE>,
1287                                  <&stgcrg JH7110_STGRST_PCIE0_APB>;
1288                         reset-names = "mst0", "slv0", "slv", "brg",
1289                                       "core", "apb";
1290                         status = "disabled";
1291
1292                         pcie_intc0: interrupt-controller {
1293                                 #address-cells = <0>;
1294                                 #interrupt-cells = <1>;
1295                                 interrupt-controller;
1296                         };
1297                 };
1298
1299                 pcie1: pcie@2C000000 {
1300                         compatible = "starfive,jh7110-pcie";
1301                         #address-cells = <3>;
1302                         #size-cells = <2>;
1303                         #interrupt-cells = <1>;
1304                         reg = <0x0 0x2C000000 0x0 0x1000000
1305                                0x9 0xc0000000 0x0 0x10000000>;
1306                         reg-names = "reg", "config";
1307                         device_type = "pci";
1308                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1309                         bus-range = <0x0 0xff>;
1310                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1311                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1312                         interrupts = <57>;
1313                         interrupt-parent = <&plic>;
1314                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1315                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
1316                                         <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
1317                                         <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
1318                                         <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
1319                         msi-parent = <&pcie1>;
1320                         msi-controller;
1321                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1322                                  <&stgcrg JH7110_STGCLK_PCIE1_TL>,
1323                                  <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
1324                                  <&stgcrg JH7110_STGCLK_PCIE1_APB>;
1325                         clock-names = "noc", "tl", "axi_mst0", "apb";
1326                         resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
1327                                  <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1328                                  <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1329                                  <&stgcrg JH7110_STGRST_PCIE1_BRG>,
1330                                  <&stgcrg JH7110_STGRST_PCIE1_CORE>,
1331                                  <&stgcrg JH7110_STGRST_PCIE1_APB>;
1332                         reset-names = "mst0", "slv0", "slv", "brg",
1333                                       "core", "apb";
1334                         status = "disabled";
1335
1336                         pcie_intc1: interrupt-controller {
1337                                 #address-cells = <0>;
1338                                 #interrupt-cells = <1>;
1339                                 interrupt-controller;
1340                         };
1341                 };
1342
1343
1344                 vout_syscon: syscon@295b0000 {
1345                         compatible = "starfive,jh7110-vout-syscon", "syscon";
1346                         reg = <0 0x295b0000 0 0x90>;
1347                 };
1348
1349                 voutcrg: clock-controller@295c0000 {
1350                         compatible = "starfive,jh7110-voutcrg";
1351                         reg = <0x0 0x295c0000 0x0 0x10000>;
1352                         clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
1353                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
1354                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
1355                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
1356                                  <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
1357                                  <&hdmitx0_pixelclk>;
1358                         clock-names = "vout_src", "vout_top_ahb",
1359                                       "vout_top_axi", "vout_top_hdmitx0_mclk",
1360                                       "i2stx0_bclk", "hdmitx0_pixelclk";
1361                         resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
1362                         #clock-cells = <1>;
1363                         #reset-cells = <1>;
1364                         power-domains = <&pwrc JH7110_PD_VOUT>;
1365                 };
1366         };
1367 };