arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
   9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
  10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
  11
  12 / {
  13         compatible = "starfive,jh7110";
  14         #address-cells = <2>;
  15         #size-cells = <2>;
  16
  17         cpus {
  18                 #address-cells = <1>;
  19                 #size-cells = <0>;
  20
  21                 S7_0: cpu@0 {
  22                         compatible = "sifive,s7", "riscv";
  23                         reg = <0>;
  24                         d-cache-block-size = <64>;
  25                         d-cache-sets = <64>;
  26                         d-cache-size = <8192>;
  27                         d-tlb-sets = <1>;
  28                         d-tlb-size = <40>;
  29                         device_type = "cpu";
  30                         i-cache-block-size = <64>;
  31                         i-cache-sets = <64>;
  32                         i-cache-size = <16384>;
  33                         i-tlb-sets = <1>;
  34                         i-tlb-size = <40>;
  35                         mmu-type = "riscv,sv39";
  36                         next-level-cache = <&ccache>;
  37                         riscv,isa = "rv64imac_zba_zbb";
  38                         tlb-split;
  39                         status = "disabled";
  40
  41                         cpu0_intc: interrupt-controller {
  42                                 compatible = "riscv,cpu-intc";
  43                                 interrupt-controller;
  44                                 #interrupt-cells = <1>;
  45                         };
  46                 };
  47
  48                 U74_1: cpu@1 {
  49                         compatible = "sifive,u74-mc", "riscv";
  50                         reg = <1>;
  51                         d-cache-block-size = <64>;
  52                         d-cache-sets = <64>;
  53                         d-cache-size = <32768>;
  54                         d-tlb-sets = <1>;
  55                         d-tlb-size = <40>;
  56                         device_type = "cpu";
  57                         i-cache-block-size = <64>;
  58                         i-cache-sets = <64>;
  59                         i-cache-size = <32768>;
  60                         i-tlb-sets = <1>;
  61                         i-tlb-size = <40>;
  62                         mmu-type = "riscv,sv39";
  63                         next-level-cache = <&ccache>;
  64                         riscv,isa = "rv64imafdc_zba_zbb";
  65                         tlb-split;
  66                         operating-points-v2 = <&cpu_opp>;
  67                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
  68                         clock-names = "cpu";
  69
  70                         cpu1_intc: interrupt-controller {
  71                                 compatible = "riscv,cpu-intc";
  72                                 interrupt-controller;
  73                                 #interrupt-cells = <1>;
  74                         };
  75                 };
  76
  77                 U74_2: cpu@2 {
  78                         compatible = "sifive,u74-mc", "riscv";
  79                         reg = <2>;
  80                         d-cache-block-size = <64>;
  81                         d-cache-sets = <64>;
  82                         d-cache-size = <32768>;
  83                         d-tlb-sets = <1>;
  84                         d-tlb-size = <40>;
  85                         device_type = "cpu";
  86                         i-cache-block-size = <64>;
  87                         i-cache-sets = <64>;
  88                         i-cache-size = <32768>;
  89                         i-tlb-sets = <1>;
  90                         i-tlb-size = <40>;
  91                         mmu-type = "riscv,sv39";
  92                         next-level-cache = <&ccache>;
  93                         riscv,isa = "rv64imafdc_zba_zbb";
  94                         tlb-split;
  95                         operating-points-v2 = <&cpu_opp>;
  96                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
  97                         clock-names = "cpu";
  98
  99                         cpu2_intc: interrupt-controller {
 100                                 compatible = "riscv,cpu-intc";
 101                                 interrupt-controller;
 102                                 #interrupt-cells = <1>;
 103                         };
 104                 };
 105
 106                 U74_3: cpu@3 {
 107                         compatible = "sifive,u74-mc", "riscv";
 108                         reg = <3>;
 109                         d-cache-block-size = <64>;
 110                         d-cache-sets = <64>;
 111                         d-cache-size = <32768>;
 112                         d-tlb-sets = <1>;
 113                         d-tlb-size = <40>;
 114                         device_type = "cpu";
 115                         i-cache-block-size = <64>;
 116                         i-cache-sets = <64>;
 117                         i-cache-size = <32768>;
 118                         i-tlb-sets = <1>;
 119                         i-tlb-size = <40>;
 120                         mmu-type = "riscv,sv39";
 121                         next-level-cache = <&ccache>;
 122                         riscv,isa = "rv64imafdc_zba_zbb";
 123                         tlb-split;
 124                         operating-points-v2 = <&cpu_opp>;
 125                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 126                         clock-names = "cpu";
 127
 128                         cpu3_intc: interrupt-controller {
 129                                 compatible = "riscv,cpu-intc";
 130                                 interrupt-controller;
 131                                 #interrupt-cells = <1>;
 132                         };
 133                 };
 134
 135                 U74_4: cpu@4 {
 136                         compatible = "sifive,u74-mc", "riscv";
 137                         reg = <4>;
 138                         d-cache-block-size = <64>;
 139                         d-cache-sets = <64>;
 140                         d-cache-size = <32768>;
 141                         d-tlb-sets = <1>;
 142                         d-tlb-size = <40>;
 143                         device_type = "cpu";
 144                         i-cache-block-size = <64>;
 145                         i-cache-sets = <64>;
 146                         i-cache-size = <32768>;
 147                         i-tlb-sets = <1>;
 148                         i-tlb-size = <40>;
 149                         mmu-type = "riscv,sv39";
 150                         next-level-cache = <&ccache>;
 151                         riscv,isa = "rv64imafdc_zba_zbb";
 152                         tlb-split;
 153                         operating-points-v2 = <&cpu_opp>;
 154                         clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
 155                         clock-names = "cpu";
 156
 157                         cpu4_intc: interrupt-controller {
 158                                 compatible = "riscv,cpu-intc";
 159                                 interrupt-controller;
 160                                 #interrupt-cells = <1>;
 161                         };
 162                 };
 163
 164                 cpu-map {
 165                         cluster0 {
 166                                 core0 {
 167                                         cpu = <&S7_0>;
 168                                 };
 169
 170                                 core1 {
 171                                         cpu = <&U74_1>;
 172                                 };
 173
 174                                 core2 {
 175                                         cpu = <&U74_2>;
 176                                 };
 177
 178                                 core3 {
 179                                         cpu = <&U74_3>;
 180                                 };
 181
 182                                 core4 {
 183                                         cpu = <&U74_4>;
 184                                 };
 185                         };
 186                 };
 187         };
 188
 189         cpu_opp: opp-table-0 {
 190                         compatible = "operating-points-v2";
 191                         opp-shared;
 192                         opp-375000000 {
 193                                         opp-hz = /bits/ 64 <375000000>;
 194                                         opp-microvolt = <800000>;
 195                         };
 196                         opp-500000000 {
 197                                         opp-hz = /bits/ 64 <500000000>;
 198                                         opp-microvolt = <800000>;
 199                         };
 200                         opp-750000000 {
 201                                         opp-hz = /bits/ 64 <750000000>;
 202                                         opp-microvolt = <800000>;
 203                         };
 204                         opp-1500000000 {
 205                                         opp-hz = /bits/ 64 <1500000000>;
 206                                         opp-microvolt = <1040000>;
 207                         };
 208         };
 209
 210         dvp_clk: dvp-clock {
 211                 compatible = "fixed-clock";
 212                 clock-output-names = "dvp_clk";
 213                 #clock-cells = <0>;
 214         };
 215
 216         gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
 217                 compatible = "fixed-clock";
 218                 clock-output-names = "gmac0_rgmii_rxin";
 219                 #clock-cells = <0>;
 220         };
 221
 222         gmac0_rmii_refin: gmac0-rmii-refin-clock {
 223                 compatible = "fixed-clock";
 224                 clock-output-names = "gmac0_rmii_refin";
 225                 #clock-cells = <0>;
 226         };
 227
 228         gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
 229                 compatible = "fixed-clock";
 230                 clock-output-names = "gmac1_rgmii_rxin";
 231                 #clock-cells = <0>;
 232         };
 233
 234         gmac1_rmii_refin: gmac1-rmii-refin-clock {
 235                 compatible = "fixed-clock";
 236                 clock-output-names = "gmac1_rmii_refin";
 237                 #clock-cells = <0>;
 238         };
 239
 240         hdmitx0_pixelclk: hdmitx0-pixel-clock {
 241                 compatible = "fixed-clock";
 242                 clock-output-names = "hdmitx0_pixelclk";
 243                 #clock-cells = <0>;
 244         };
 245
 246         i2srx_bclk_ext: i2srx-bclk-ext-clock {
 247                 compatible = "fixed-clock";
 248                 clock-output-names = "i2srx_bclk_ext";
 249                 #clock-cells = <0>;
 250         };
 251
 252         i2srx_lrck_ext: i2srx-lrck-ext-clock {
 253                 compatible = "fixed-clock";
 254                 clock-output-names = "i2srx_lrck_ext";
 255                 #clock-cells = <0>;
 256         };
 257
 258         i2stx_bclk_ext: i2stx-bclk-ext-clock {
 259                 compatible = "fixed-clock";
 260                 clock-output-names = "i2stx_bclk_ext";
 261                 #clock-cells = <0>;
 262         };
 263
 264         i2stx_lrck_ext: i2stx-lrck-ext-clock {
 265                 compatible = "fixed-clock";
 266                 clock-output-names = "i2stx_lrck_ext";
 267                 #clock-cells = <0>;
 268         };
 269
 270         mclk_ext: mclk-ext-clock {
 271                 compatible = "fixed-clock";
 272                 clock-output-names = "mclk_ext";
 273                 #clock-cells = <0>;
 274         };
 275
 276         osc: oscillator {
 277                 compatible = "fixed-clock";
 278                 clock-output-names = "osc";
 279                 #clock-cells = <0>;
 280         };
 281
 282         rtc_osc: rtc-oscillator {
 283                 compatible = "fixed-clock";
 284                 clock-output-names = "rtc_osc";
 285                 #clock-cells = <0>;
 286         };
 287
 288         stmmac_axi_setup: stmmac-axi-config {
 289                 snps,lpi_en;
 290                 snps,wr_osr_lmt = <4>;
 291                 snps,rd_osr_lmt = <4>;
 292                 snps,blen = <256 128 64 32 0 0 0>;
 293         };
 294
 295         tdm_ext: tdm-ext-clock {
 296                 compatible = "fixed-clock";
 297                 clock-output-names = "tdm_ext";
 298                 #clock-cells = <0>;
 299         };
 300
 301         soc {
 302                 compatible = "simple-bus";
 303                 interrupt-parent = <&plic>;
 304                 #address-cells = <2>;
 305                 #size-cells = <2>;
 306                 ranges;
 307
 308                 clint: timer@2000000 {
 309                         compatible = "starfive,jh7110-clint", "sifive,clint0";
 310                         reg = <0x0 0x2000000 0x0 0x10000>;
 311                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 312                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 313                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 314                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 315                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 316                 };
 317
 318                 ccache: cache-controller@2010000 {
 319                         compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
 320                         reg = <0x0 0x2010000 0x0 0x4000>;
 321                         interrupts = <1>, <3>, <4>, <2>;
 322                         cache-block-size = <64>;
 323                         cache-level = <2>;
 324                         cache-sets = <2048>;
 325                         cache-size = <2097152>;
 326                         cache-unified;
 327                 };
 328
 329                 plic: interrupt-controller@c000000 {
 330                         compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
 331                         reg = <0x0 0xc000000 0x0 0x4000000>;
 332                         interrupts-extended = <&cpu0_intc 11>,
 333                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 334                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 335                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 336                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 337                         interrupt-controller;
 338                         #interrupt-cells = <1>;
 339                         #address-cells = <0>;
 340                         riscv,ndev = <136>;
 341                 };
 342
 343                 uart0: serial@10000000 {
 344                         compatible = "snps,dw-apb-uart";
 345                         reg = <0x0 0x10000000 0x0 0x10000>;
 346                         clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
 347                                  <&syscrg JH7110_SYSCLK_UART0_APB>;
 348                         clock-names = "baudclk", "apb_pclk";
 349                         resets = <&syscrg JH7110_SYSRST_UART0_APB>;
 350                         interrupts = <32>;
 351                         reg-io-width = <4>;
 352                         reg-shift = <2>;
 353                         status = "disabled";
 354                 };
 355
 356                 uart1: serial@10010000 {
 357                         compatible = "snps,dw-apb-uart";
 358                         reg = <0x0 0x10010000 0x0 0x10000>;
 359                         clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
 360                                  <&syscrg JH7110_SYSCLK_UART1_APB>;
 361                         clock-names = "baudclk", "apb_pclk";
 362                         resets = <&syscrg JH7110_SYSRST_UART1_APB>;
 363                         interrupts = <33>;
 364                         reg-io-width = <4>;
 365                         reg-shift = <2>;
 366                         status = "disabled";
 367                 };
 368
 369                 uart2: serial@10020000 {
 370                         compatible = "snps,dw-apb-uart";
 371                         reg = <0x0 0x10020000 0x0 0x10000>;
 372                         clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
 373                                  <&syscrg JH7110_SYSCLK_UART2_APB>;
 374                         clock-names = "baudclk", "apb_pclk";
 375                         resets = <&syscrg JH7110_SYSRST_UART2_APB>;
 376                         interrupts = <34>;
 377                         reg-io-width = <4>;
 378                         reg-shift = <2>;
 379                         status = "disabled";
 380                 };
 381
 382                 i2c0: i2c@10030000 {
 383                         compatible = "snps,designware-i2c";
 384                         reg = <0x0 0x10030000 0x0 0x10000>;
 385                         clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
 386                         clock-names = "ref";
 387                         resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
 388                         interrupts = <35>;
 389                         #address-cells = <1>;
 390                         #size-cells = <0>;
 391                         status = "disabled";
 392                 };
 393
 394                 i2c1: i2c@10040000 {
 395                         compatible = "snps,designware-i2c";
 396                         reg = <0x0 0x10040000 0x0 0x10000>;
 397                         clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
 398                         clock-names = "ref";
 399                         resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
 400                         interrupts = <36>;
 401                         #address-cells = <1>;
 402                         #size-cells = <0>;
 403                         status = "disabled";
 404                 };
 405
 406                 i2c2: i2c@10050000 {
 407                         compatible = "snps,designware-i2c";
 408                         reg = <0x0 0x10050000 0x0 0x10000>;
 409                         clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
 410                         clock-names = "ref";
 411                         resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
 412                         interrupts = <37>;
 413                         #address-cells = <1>;
 414                         #size-cells = <0>;
 415                         status = "disabled";
 416                 };
 417
 418                 usb0: usb@10100000 {
 419                         compatible = "starfive,jh7110-usb";
 420                         clocks = <&stgcrg JH7110_STGCLK_USB0_LPM>,
 421                                  <&stgcrg JH7110_STGCLK_USB0_STB>,
 422                                  <&stgcrg JH7110_STGCLK_USB0_APB>,
 423                                  <&stgcrg JH7110_STGCLK_USB0_AXI>,
 424                                  <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
 425                         clock-names = "lpm", "stb", "apb", "axi", "utmi_apb";
 426                         resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
 427                                  <&stgcrg JH7110_STGRST_USB0_APB>,
 428                                  <&stgcrg JH7110_STGRST_USB0_AXI>,
 429                                  <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
 430                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 431                         starfive,sys-syscon = <&sys_syscon 0x18>;
 432                         status = "disabled";
 433                         #address-cells = <1>;
 434                         #size-cells = <1>;
 435                         ranges = <0x0 0x0 0x10100000 0x100000>;
 436
 437                         usbdrd_cdns3: usb@0 {
 438                                 compatible = "cdns,usb3";
 439                                 reg = <0x0 0x10000>,
 440                                       <0x10000 0x10000>,
 441                                       <0x20000 0x10000>;
 442                                 reg-names = "otg", "xhci", "dev";
 443                                 interrupts = <100>, <108>, <110>;
 444                                 interrupt-names = "host", "peripheral", "otg";
 445                                 phys = <&usbphy0>;
 446                                 phy-names = "cdns3,usb2-phy";
 447                                 maximum-speed = "super-speed";
 448                         };
 449                 };
 450
 451                 usbphy0: phy@10200000 {
 452                         compatible = "starfive,jh7110-usb-phy";
 453                         reg = <0x0 0x10200000 0x0 0x10000>;
 454                         clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
 455                                  <&stgcrg JH7110_STGCLK_USB0_APP_125>;
 456                         clock-names = "125m", "app_125";
 457                         #phy-cells = <0>;
 458                 };
 459
 460                 pciephy0: phy@10210000 {
 461                         compatible = "starfive,jh7110-pcie-phy";
 462                         reg = <0x0 0x10210000 0x0 0x10000>;
 463                         #phy-cells = <0>;
 464                 };
 465
 466                 pciephy1: phy@10220000 {
 467                         compatible = "starfive,jh7110-pcie-phy";
 468                         reg = <0x0 0x10220000 0x0 0x10000>;
 469                         #phy-cells = <0>;
 470                 };
 471
 472                 stgcrg: clock-controller@10230000 {
 473                         compatible = "starfive,jh7110-stgcrg";
 474                         reg = <0x0 0x10230000 0x0 0x10000>;
 475                         clocks = <&osc>,
 476                                  <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
 477                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 478                                  <&syscrg JH7110_SYSCLK_USB_125M>,
 479                                  <&syscrg JH7110_SYSCLK_CPU_BUS>,
 480                                  <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
 481                                  <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
 482                                  <&syscrg JH7110_SYSCLK_APB_BUS>;
 483                         clock-names = "osc", "hifi4_core",
 484                                       "stg_axiahb", "usb_125m",
 485                                       "cpu_bus", "hifi4_axi",
 486                                       "nocstg_bus", "apb_bus";
 487                         #clock-cells = <1>;
 488                         #reset-cells = <1>;
 489                 };
 490
 491                 stg_syscon: syscon@10240000 {
 492                         compatible = "starfive,jh7110-stg-syscon", "syscon";
 493                         reg = <0x0 0x10240000 0x0 0x1000>;
 494                 };
 495
 496                 uart3: serial@12000000 {
 497                         compatible = "snps,dw-apb-uart";
 498                         reg = <0x0 0x12000000 0x0 0x10000>;
 499                         clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
 500                                  <&syscrg JH7110_SYSCLK_UART3_APB>;
 501                         clock-names = "baudclk", "apb_pclk";
 502                         resets = <&syscrg JH7110_SYSRST_UART3_APB>;
 503                         interrupts = <45>;
 504                         reg-io-width = <4>;
 505                         reg-shift = <2>;
 506                         status = "disabled";
 507                 };
 508
 509                 uart4: serial@12010000 {
 510                         compatible = "snps,dw-apb-uart";
 511                         reg = <0x0 0x12010000 0x0 0x10000>;
 512                         clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
 513                                  <&syscrg JH7110_SYSCLK_UART4_APB>;
 514                         clock-names = "baudclk", "apb_pclk";
 515                         resets = <&syscrg JH7110_SYSRST_UART4_APB>;
 516                         interrupts = <46>;
 517                         reg-io-width = <4>;
 518                         reg-shift = <2>;
 519                         status = "disabled";
 520                 };
 521
 522                 uart5: serial@12020000 {
 523                         compatible = "snps,dw-apb-uart";
 524                         reg = <0x0 0x12020000 0x0 0x10000>;
 525                         clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
 526                                  <&syscrg JH7110_SYSCLK_UART5_APB>;
 527                         clock-names = "baudclk", "apb_pclk";
 528                         resets = <&syscrg JH7110_SYSRST_UART5_APB>;
 529                         interrupts = <47>;
 530                         reg-io-width = <4>;
 531                         reg-shift = <2>;
 532                         status = "disabled";
 533                 };
 534
 535                 i2c3: i2c@12030000 {
 536                         compatible = "snps,designware-i2c";
 537                         reg = <0x0 0x12030000 0x0 0x10000>;
 538                         clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
 539                         clock-names = "ref";
 540                         resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
 541                         interrupts = <48>;
 542                         #address-cells = <1>;
 543                         #size-cells = <0>;
 544                         status = "disabled";
 545                 };
 546
 547                 i2c4: i2c@12040000 {
 548                         compatible = "snps,designware-i2c";
 549                         reg = <0x0 0x12040000 0x0 0x10000>;
 550                         clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
 551                         clock-names = "ref";
 552                         resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
 553                         interrupts = <49>;
 554                         #address-cells = <1>;
 555                         #size-cells = <0>;
 556                         status = "disabled";
 557                 };
 558
 559                 i2c5: i2c@12050000 {
 560                         compatible = "snps,designware-i2c";
 561                         reg = <0x0 0x12050000 0x0 0x10000>;
 562                         clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
 563                         clock-names = "ref";
 564                         resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
 565                         interrupts = <50>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         status = "disabled";
 569                 };
 570
 571                 i2c6: i2c@12060000 {
 572                         compatible = "snps,designware-i2c";
 573                         reg = <0x0 0x12060000 0x0 0x10000>;
 574                         clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
 575                         clock-names = "ref";
 576                         resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
 577                         interrupts = <51>;
 578                         #address-cells = <1>;
 579                         #size-cells = <0>;
 580                         status = "disabled";
 581                 };
 582
 583                 ptc: pwm@120d0000 {
 584                         compatible = "starfive,jh7110-pwm";
 585                         reg = <0x0 0x120d0000 0x0 0x10000>;
 586                         clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
 587                         resets = <&syscrg JH7110_SYSRST_PWM_APB>;
 588                         #pwm-cells=<3>;
 589                         status = "disabled";
 590                 };
 591
 592                 sfctemp: temperature-sensor@120e0000 {
 593                         compatible = "starfive,jh7110-temp";
 594                         reg = <0x0 0x120e0000 0x0 0x10000>;
 595                         clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
 596                                  <&syscrg JH7110_SYSCLK_TEMP_APB>;
 597                         clock-names = "sense", "bus";
 598                         resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
 599                                  <&syscrg JH7110_SYSRST_TEMP_APB>;
 600                         reset-names = "sense", "bus";
 601                         #thermal-sensor-cells = <0>;
 602                 };
 603
 604                 qspi: spi@13010000 {
 605                         compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
 606                         #address-cells = <1>;
 607                         #size-cells = <0>;
 608                         reg = <0x0 0x13010000 0x0 0x10000
 609                                0x0 0x21000000 0x0 0x400000>;
 610                         interrupts = <25>;
 611                         clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
 612                         resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
 613                                  <&syscrg JH7110_SYSRST_QSPI_AHB>,
 614                                  <&syscrg JH7110_SYSRST_QSPI_REF>;
 615                         reset-names = "qspi", "qspi-ocp", "rstc_ref";
 616                         cdns,fifo-depth = <256>;
 617                         cdns,fifo-width = <4>;
 618                         cdns,trigger-address = <0x0>;
 619
 620                         nor_flash: nor-flash@0 {
 621                                 compatible = "jedec,spi-nor";
 622                                 reg=<0>;
 623                                 cdns,read-delay = <5>;
 624                                 spi-max-frequency = <12000000>;
 625                                 cdns,tshsl-ns = <1>;
 626                                 cdns,tsd2d-ns = <1>;
 627                                 cdns,tchsh-ns = <1>;
 628                                 cdns,tslch-ns = <1>;
 629
 630                                 partitions {
 631                                         compatible = "fixed-partitions";
 632                                         #address-cells = <1>;
 633                                         #size-cells = <1>;
 634
 635                                         spl@0 {
 636                                                 reg = <0x0 0x20000>;
 637                                         };
 638                                         uboot@100000 {
 639                                                 reg = <0x100000 0x300000>;
 640                                         };
 641                                         data@f00000 {
 642                                                 reg = <0xf00000 0x100000>;
 643                                         };
 644                                 };
 645                         };
 646                 };
 647
 648                 syscrg: clock-controller@13020000 {
 649                         compatible = "starfive,jh7110-syscrg";
 650                         reg = <0x0 0x13020000 0x0 0x10000>;
 651                         clocks = <&osc>, <&gmac1_rmii_refin>,
 652                                  <&gmac1_rgmii_rxin>,
 653                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 654                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 655                                  <&tdm_ext>, <&mclk_ext>,
 656                                  <&pllclk JH7110_CLK_PLL0_OUT>,
 657                                  <&pllclk JH7110_CLK_PLL1_OUT>,
 658                                  <&pllclk JH7110_CLK_PLL2_OUT>;
 659                         clock-names = "osc", "gmac1_rmii_refin",
 660                                       "gmac1_rgmii_rxin",
 661                                       "i2stx_bclk_ext", "i2stx_lrck_ext",
 662                                       "i2srx_bclk_ext", "i2srx_lrck_ext",
 663                                       "tdm_ext", "mclk_ext",
 664                                       "pll0_out", "pll1_out", "pll2_out";
 665                         #clock-cells = <1>;
 666                         #reset-cells = <1>;
 667                 };
 668
 669                 sys_syscon: syscon@13030000 {
 670                         compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 671                         reg = <0x0 0x13030000 0x0 0x1000>;
 672
 673                         pllclk: pll-clock-controller {
 674                                 compatible = "starfive,jh7110-pll";
 675                                 clocks = <&osc>;
 676                                 #clock-cells = <1>;
 677                         };
 678                 };
 679
 680                 sysgpio: pinctrl@13040000 {
 681                         compatible = "starfive,jh7110-sys-pinctrl";
 682                         reg = <0x0 0x13040000 0x0 0x10000>;
 683                         clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
 684                         resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
 685                         interrupts = <86>;
 686                         interrupt-controller;
 687                         #interrupt-cells = <2>;
 688                         gpio-controller;
 689                         #gpio-cells = <2>;
 690                 };
 691
 692                 timer@13050000 {
 693                         compatible = "starfive,jh7110-timer";
 694                         reg = <0x0 0x13050000 0x0 0x10000>;
 695                         interrupts = <69>, <70>, <71> ,<72>;
 696                         clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
 697                                  <&syscrg JH7110_SYSCLK_TIMER0>,
 698                                  <&syscrg JH7110_SYSCLK_TIMER1>,
 699                                  <&syscrg JH7110_SYSCLK_TIMER2>,
 700                                  <&syscrg JH7110_SYSCLK_TIMER3>;
 701                         clock-names = "apb", "ch0", "ch1",
 702                                       "ch2", "ch3";
 703                         resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
 704                                  <&syscrg JH7110_SYSRST_TIMER0>,
 705                                  <&syscrg JH7110_SYSRST_TIMER1>,
 706                                  <&syscrg JH7110_SYSRST_TIMER2>,
 707                                  <&syscrg JH7110_SYSRST_TIMER3>;
 708                         reset-names = "apb", "ch0", "ch1",
 709                                       "ch2", "ch3";
 710                 };
 711
 712                 wdog: watchdog@13070000 {
 713                         compatible = "starfive,jh7110-wdt";
 714                         reg = <0x0 0x13070000 0x0 0x10000>;
 715                         clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
 716                                  <&syscrg JH7110_SYSCLK_WDT_CORE>;
 717                         clock-names = "apb", "core";
 718                         resets = <&syscrg JH7110_SYSRST_WDT_APB>,
 719                                  <&syscrg JH7110_SYSRST_WDT_CORE>;
 720                 };
 721
 722                 crypto: crypto@16000000 {
 723                         compatible = "starfive,jh7110-crypto";
 724                         reg = <0x0 0x16000000 0x0 0x4000>;
 725                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 726                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 727                         clock-names = "hclk", "ahb";
 728                         interrupts = <28>;
 729                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 730                         dmas = <&sdma 1 2>, <&sdma 0 2>;
 731                         dma-names = "tx", "rx";
 732                 };
 733
 734                 sdma: dma@16008000 {
 735                         compatible = "arm,pl080", "arm,primecell";
 736                         arm,primecell-periphid = <0x00041080>;
 737                         reg = <0x0 0x16008000 0x0 0x4000>;
 738                         interrupts = <29>;
 739                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 740                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 741                         clock-names = "hclk", "apb_pclk";
 742                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 743                         lli-bus-interface-ahb1;
 744                         mem-bus-interface-ahb1;
 745                         memcpy-burst-size = <256>;
 746                         memcpy-bus-width = <32>;
 747                         #dma-cells = <2>;
 748                 };
 749
 750                 rng: rng@1600c000 {
 751                         compatible = "starfive,jh7110-trng";
 752                         reg = <0x0 0x1600C000 0x0 0x4000>;
 753                         clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
 754                                  <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
 755                         clock-names = "hclk", "ahb";
 756                         resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
 757                         interrupts = <30>;
 758                 };
 759
 760                 mmc0: mmc@16010000 {
 761                         compatible = "starfive,jh7110-mmc";
 762                         reg = <0x0 0x16010000 0x0 0x10000>;
 763                         clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
 764                                  <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
 765                         clock-names = "biu","ciu";
 766                         resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
 767                         reset-names = "reset";
 768                         interrupts = <74>;
 769                         fifo-depth = <32>;
 770                         fifo-watermark-aligned;
 771                         data-addr = <0>;
 772                         starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
 773                         status = "disabled";
 774                 };
 775
 776                 mmc1: mmc@16020000 {
 777                         compatible = "starfive,jh7110-mmc";
 778                         reg = <0x0 0x16020000 0x0 0x10000>;
 779                         clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
 780                                  <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
 781                         clock-names = "biu","ciu";
 782                         resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
 783                         reset-names = "reset";
 784                         interrupts = <75>;
 785                         fifo-depth = <32>;
 786                         fifo-watermark-aligned;
 787                         data-addr = <0>;
 788                         starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
 789                         status = "disabled";
 790                 };
 791
 792                 gmac0: ethernet@16030000 {
 793                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 794                         reg = <0x0 0x16030000 0x0 0x10000>;
 795                         clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
 796                                  <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
 797                                  <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
 798                                  <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
 799                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
 800                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 801                                       "tx", "gtx";
 802                         resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
 803                                  <&aoncrg JH7110_AONRST_GMAC0_AHB>;
 804                         reset-names = "stmmaceth", "ahb";
 805                         interrupts = <7>, <6>, <5>;
 806                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 807                         snps,multicast-filter-bins = <64>;
 808                         snps,perfect-filter-entries = <8>;
 809                         rx-fifo-depth = <2048>;
 810                         tx-fifo-depth = <2048>;
 811                         snps,fixed-burst;
 812                         snps,no-pbl-x8;
 813                         snps,force_thresh_dma_mode;
 814                         snps,axi-config = <&stmmac_axi_setup>;
 815                         snps,tso;
 816                         snps,en-tx-lpi-clockgating;
 817                         snps,txpbl = <16>;
 818                         snps,rxpbl = <16>;
 819                         starfive,syscon = <&aon_syscon 0xc 0x12>;
 820                         status = "disabled";
 821                 };
 822
 823                 gmac1: ethernet@16040000 {
 824                         compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
 825                         reg = <0x0 0x16040000 0x0 0x10000>;
 826                         clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
 827                                  <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
 828                                  <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
 829                                  <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
 830                                  <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
 831                         clock-names = "stmmaceth", "pclk", "ptp_ref",
 832                                       "tx", "gtx";
 833                         resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
 834                                  <&syscrg JH7110_SYSRST_GMAC1_AHB>;
 835                         reset-names = "stmmaceth", "ahb";
 836                         interrupts = <78>, <77>, <76>;
 837                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 838                         snps,multicast-filter-bins = <64>;
 839                         snps,perfect-filter-entries = <8>;
 840                         rx-fifo-depth = <2048>;
 841                         tx-fifo-depth = <2048>;
 842                         snps,fixed-burst;
 843                         snps,no-pbl-x8;
 844                         snps,force_thresh_dma_mode;
 845                         snps,axi-config = <&stmmac_axi_setup>;
 846                         snps,tso;
 847                         snps,en-tx-lpi-clockgating;
 848                         snps,txpbl = <16>;
 849                         snps,rxpbl = <16>;
 850                         starfive,syscon = <&sys_syscon 0x90 0x2>;
 851                         status = "disabled";
 852                 };
 853
 854                 dma: dma-controller@16050000 {
 855                         compatible = "starfive,jh7110-axi-dma";
 856                         reg = <0x0 0x16050000 0x0 0x10000>;
 857                         clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
 858                                  <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
 859                         clock-names = "core-clk", "cfgr-clk";
 860                         resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
 861                                  <&stgcrg JH7110_STGRST_DMA1P_AHB>;
 862                         interrupts = <73>;
 863                         #dma-cells = <1>;
 864                         dma-channels = <4>;
 865                         snps,dma-masters = <1>;
 866                         snps,data-width = <3>;
 867                         snps,block-size = <65536 65536 65536 65536>;
 868                         snps,priority = <0 1 2 3>;
 869                         snps,axi-max-burst-len = <16>;
 870                 };
 871
 872                 aoncrg: clock-controller@17000000 {
 873                         compatible = "starfive,jh7110-aoncrg";
 874                         reg = <0x0 0x17000000 0x0 0x10000>;
 875                         clocks = <&osc>, <&gmac0_rmii_refin>,
 876                                  <&gmac0_rgmii_rxin>,
 877                                  <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
 878                                  <&syscrg JH7110_SYSCLK_APB_BUS>,
 879                                  <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
 880                                  <&rtc_osc>;
 881                         clock-names = "osc", "gmac0_rmii_refin",
 882                                       "gmac0_rgmii_rxin", "stg_axiahb",
 883                                       "apb_bus", "gmac0_gtxclk",
 884                                       "rtc_osc";
 885                         #clock-cells = <1>;
 886                         #reset-cells = <1>;
 887                 };
 888
 889                 aon_syscon: syscon@17010000 {
 890                         compatible = "starfive,jh7110-aon-syscon", "syscon";
 891                         reg = <0x0 0x17010000 0x0 0x1000>;
 892                 };
 893
 894                 aongpio: pinctrl@17020000 {
 895                         compatible = "starfive,jh7110-aon-pinctrl";
 896                         reg = <0x0 0x17020000 0x0 0x10000>;
 897                         resets = <&aoncrg JH7110_AONRST_IOMUX>;
 898                         interrupts = <85>;
 899                         interrupt-controller;
 900                         #interrupt-cells = <2>;
 901                         gpio-controller;
 902                         #gpio-cells = <2>;
 903                 };
 904
 905                 pwrc: power-controller@17030000 {
 906                         compatible = "starfive,jh7110-pmu";
 907                         reg = <0x0 0x17030000 0x0 0x10000>;
 908                         interrupts = <111>;
 909                         #power-domain-cells = <1>;
 910                 };
 911
 912                 ispcrg: clock-controller@19810000 {
 913                         compatible = "starfive,jh7110-ispcrg";
 914                         reg = <0x0 0x19810000 0x0 0x10000>;
 915                         clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
 916                                  <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
 917                                  <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
 918                                  <&dvp_clk>;
 919                         clock-names = "isp_top_core", "isp_top_axi",
 920                                       "noc_bus_isp_axi", "dvp_clk";
 921                         resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
 922                                  <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
 923                                  <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
 924                         #clock-cells = <1>;
 925                         #reset-cells = <1>;
 926                         power-domains = <&pwrc JH7110_PD_ISP>;
 927                 };
 928
 929                 csi_phy: phy@19820000 {
 930                         compatible = "starfive,jh7110-dphy-rx";
 931                         reg = <0x0 0x19820000 0x0 0x10000>;
 932                         clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
 933                                  <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
 934                                  <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
 935                         clock-names = "cfg", "ref", "tx";
 936                         resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
 937                                  <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
 938                         starfive,aon-syscon = <&aon_syscon 0x00>;
 939                         #phy-cells = <0>;
 940                 };
 941
 942                 voutcrg: clock-controller@295c0000 {
 943                         compatible = "starfive,jh7110-voutcrg";
 944                         reg = <0x0 0x295c0000 0x0 0x10000>;
 945                         clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
 946                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
 947                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
 948                                  <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
 949                                  <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
 950                                  <&hdmitx0_pixelclk>;
 951                         clock-names = "vout_src", "vout_top_ahb",
 952                                       "vout_top_axi", "vout_top_hdmitx0_mclk",
 953                                       "i2stx0_bclk", "hdmitx0_pixelclk";
 954                         resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
 955                         #clock-cells = <1>;
 956                         #reset-cells = <1>;
 957                         power-domains = <&pwrc JH7110_PD_VOUT>;
 958                 };
 959
 960                 pcie0: pcie@2B000000 {
 961                         compatible = "starfive,jh7110-pcie";
 962                         #address-cells = <3>;
 963                         #size-cells = <2>;
 964                         #interrupt-cells = <1>;
 965                         reg = <0x0 0x2B000000 0x0 0x1000000
 966                                0x9 0x40000000 0x0 0x10000000>;
 967                         reg-names = "reg", "config";
 968                         device_type = "pci";
 969                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
 970                         bus-range = <0x0 0xff>;
 971                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
 972                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
 973                         interrupts = <56>;
 974                         interrupt-parent = <&plic>;
 975                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 976                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>,
 977                                         <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>,
 978                                         <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>,
 979                                         <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>;
 980                         msi-parent = <&pcie0>;
 981                         msi-controller;
 982                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
 983                                  <&stgcrg JH7110_STGCLK_PCIE0_TL>,
 984                                  <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>,
 985                                  <&stgcrg JH7110_STGCLK_PCIE0_APB>;
 986                         clock-names = "noc", "tl", "axi_mst0", "apb";
 987                         resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>,
 988                                  <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>,
 989                                  <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>,
 990                                  <&stgcrg JH7110_STGRST_PCIE0_BRG>,
 991                                  <&stgcrg JH7110_STGRST_PCIE0_CORE>,
 992                                  <&stgcrg JH7110_STGRST_PCIE0_APB>;
 993                         reset-names = "mst0", "slv0", "slv", "brg",
 994                                       "core", "apb";
 995                         status = "disabled";
 996
 997                         pcie_intc0: interrupt-controller {
 998                                 #address-cells = <0>;
 999                                 #interrupt-cells = <1>;
1000                                 interrupt-controller;
1001                         };
1002                 };
1003
1004                 pcie1: pcie@2C000000 {
1005                         compatible = "starfive,jh7110-pcie";
1006                         #address-cells = <3>;
1007                         #size-cells = <2>;
1008                         #interrupt-cells = <1>;
1009                         reg = <0x0 0x2C000000 0x0 0x1000000
1010                                0x9 0xc0000000 0x0 0x10000000>;
1011                         reg-names = "reg", "config";
1012                         device_type = "pci";
1013                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1014                         bus-range = <0x0 0xff>;
1015                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1016                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1017                         interrupts = <57>;
1018                         interrupt-parent = <&plic>;
1019                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1020                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>,
1021                                         <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>,
1022                                         <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>,
1023                                         <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>;
1024                         msi-parent = <&pcie1>;
1025                         msi-controller;
1026                         clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>,
1027                                  <&stgcrg JH7110_STGCLK_PCIE1_TL>,
1028                                  <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>,
1029                                  <&stgcrg JH7110_STGCLK_PCIE1_APB>;
1030                         clock-names = "noc", "tl", "axi_mst0", "apb";
1031                         resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>,
1032                                  <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>,
1033                                  <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>,
1034                                  <&stgcrg JH7110_STGRST_PCIE1_BRG>,
1035                                  <&stgcrg JH7110_STGRST_PCIE1_CORE>,
1036                                  <&stgcrg JH7110_STGRST_PCIE1_APB>;
1037                         reset-names = "mst0", "slv0", "slv", "brg",
1038                                       "core", "apb";
1039                         status = "disabled";
1040
1041                         pcie_intc1: interrupt-controller {
1042                                 #address-cells = <0>;
1043                                 #interrupt-cells = <1>;
1044                                 interrupt-controller;
1045                         };
1046                 };
1047         };
1048 };