arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "sifive,u74-mc", "riscv";
  26                         reg = <0>;
  27                         d-cache-block-size = <64>;
  28                         d-cache-sets = <64>;
  29                         d-cache-size = <8192>;
  30                         d-tlb-sets = <1>;
  31                         d-tlb-size = <40>;
  32                         device_type = "cpu";
  33                         i-cache-block-size = <64>;
  34                         i-cache-sets = <64>;
  35                         i-cache-size = <16384>;
  36                         i-tlb-sets = <1>;
  37                         i-tlb-size = <40>;
  38                         mmu-type = "riscv,sv39";
  39                         next-level-cache = <&cachectrl>;
  40                         riscv,isa = "rv64imac";
  41                         tlb-split;
  42                         status = "disabled";
  43
  44                         cpu0intctrl: interrupt-controller {
  45                                 #interrupt-cells = <1>;
  46                                 compatible = "riscv,cpu-intc";
  47                                 interrupt-controller;
  48                         };
  49                 };
  50
  51                 cpu1: cpu@1 {
  52                         compatible = "sifive,u74-mc", "riscv";
  53                         reg = <1>;
  54                         d-cache-block-size = <64>;
  55                         d-cache-sets = <64>;
  56                         d-cache-size = <32768>;
  57                         d-tlb-sets = <1>;
  58                         d-tlb-size = <40>;
  59                         device_type = "cpu";
  60                         i-cache-block-size = <64>;
  61                         i-cache-sets = <64>;
  62                         i-cache-size = <32768>;
  63                         i-tlb-sets = <1>;
  64                         i-tlb-size = <40>;
  65                         mmu-type = "riscv,sv39";
  66                         next-level-cache = <&cachectrl>;
  67                         riscv,isa = "rv64imafdc";
  68                         tlb-split;
  69                         status = "okay";
  70
  71                         cpu1intctrl: interrupt-controller {
  72                                 #interrupt-cells = <1>;
  73                                 compatible = "riscv,cpu-intc";
  74                                 interrupt-controller;
  75                         };
  76                 };
  77
  78                 cpu2: cpu@2 {
  79                         compatible = "sifive,u74-mc", "riscv";
  80                         reg = <2>;
  81                         d-cache-block-size = <64>;
  82                         d-cache-sets = <64>;
  83                         d-cache-size = <32768>;
  84                         d-tlb-sets = <1>;
  85                         d-tlb-size = <40>;
  86                         device_type = "cpu";
  87                         i-cache-block-size = <64>;
  88                         i-cache-sets = <64>;
  89                         i-cache-size = <32768>;
  90                         i-tlb-sets = <1>;
  91                         i-tlb-size = <40>;
  92                         mmu-type = "riscv,sv39";
  93                         next-level-cache = <&cachectrl>;
  94                         riscv,isa = "rv64imafdc";
  95                         tlb-split;
  96                         status = "okay";
  97
  98                         cpu2intctrl: interrupt-controller {
  99                                 #interrupt-cells = <1>;
 100                                 compatible = "riscv,cpu-intc";
 101                                 interrupt-controller;
 102                         };
 103                 };
 104
 105                 cpu3: cpu@3 {
 106                         compatible = "sifive,u74-mc", "riscv";
 107                         reg = <3>;
 108                         d-cache-block-size = <64>;
 109                         d-cache-sets = <64>;
 110                         d-cache-size = <32768>;
 111                         d-tlb-sets = <1>;
 112                         d-tlb-size = <40>;
 113                         device_type = "cpu";
 114                         i-cache-block-size = <64>;
 115                         i-cache-sets = <64>;
 116                         i-cache-size = <32768>;
 117                         i-tlb-sets = <1>;
 118                         i-tlb-size = <40>;
 119                         mmu-type = "riscv,sv39";
 120                         next-level-cache = <&cachectrl>;
 121                         riscv,isa = "rv64imafdc";
 122                         tlb-split;
 123                         status = "okay";
 124
 125                         cpu3intctrl: interrupt-controller {
 126                                 #interrupt-cells = <1>;
 127                                 compatible = "riscv,cpu-intc";
 128                                 interrupt-controller;
 129                         };
 130                 };
 131
 132                 cpu4: cpu@4 {
 133                         compatible = "sifive,u74-mc", "riscv";
 134                         reg = <4>;
 135                         d-cache-block-size = <64>;
 136                         d-cache-sets = <64>;
 137                         d-cache-size = <32768>;
 138                         d-tlb-sets = <1>;
 139                         d-tlb-size = <40>;
 140                         device_type = "cpu";
 141                         i-cache-block-size = <64>;
 142                         i-cache-sets = <64>;
 143                         i-cache-size = <32768>;
 144                         i-tlb-sets = <1>;
 145                         i-tlb-size = <40>;
 146                         mmu-type = "riscv,sv39";
 147                         next-level-cache = <&cachectrl>;
 148                         riscv,isa = "rv64imafdc";
 149                         tlb-split;
 150                         status = "okay";
 151
 152                         cpu4intctrl: interrupt-controller {
 153                                 #interrupt-cells = <1>;
 154                                 compatible = "riscv,cpu-intc";
 155                                 interrupt-controller;
 156                         };
 157                 };
 158         };
 159
 160         soc: soc {
 161                 compatible = "simple-bus";
 162                 interrupt-parent = <&plic>;
 163                 #address-cells = <2>;
 164                 #size-cells = <2>;
 165                 #clock-cells = <1>;
 166                 ranges;
 167
 168                 cachectrl: cache-controller@2010000 {
 169                         compatible = "sifive,fu740-c000-ccache", "cache";
 170                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 171                         reg-names = "control", "sideband";
 172                         interrupts = <1 3 4 2>;
 173                         cache-block-size = <64>;
 174                         cache-level = <2>;
 175                         cache-sets = <2048>;
 176                         cache-size = <2097152>;
 177                         cache-unified;
 178                 };
 179
 180                 aon_syscon: aon_syscon@17010000 {
 181                         compatible = "syscon";
 182                         reg = <0x0 0x17010000 0x0 0x1000>;
 183                 };
 184
 185                 stg_syscon: stg_syscon@10240000 {
 186                         compatible = "syscon";
 187                         reg = <0x0 0x10240000 0x0 0x1000>;
 188                 };
 189
 190                 sys_syscon: sys_syscon@13030000 {
 191                         compatible = "syscon";
 192                         reg = <0x0 0x13030000 0x0 0x1000>;
 193                 };
 194
 195                 clint: clint@2000000 {
 196                         compatible = "riscv,clint0";
 197                         reg = <0x0 0x2000000 0x0 0x10000>;
 198                         reg-names = "control";
 199                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 200                                                 &cpu1intctrl 3 &cpu1intctrl 7
 201                                                 &cpu2intctrl 3 &cpu2intctrl 7
 202                                                 &cpu3intctrl 3 &cpu3intctrl 7
 203                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 204                         #interrupt-cells = <1>;
 205                 };
 206
 207                 plic: plic@c000000 {
 208                         compatible = "riscv,plic0";
 209                         reg = <0x0 0xc000000 0x0 0x4000000>;
 210                         reg-names = "control";
 211                         interrupts-extended = <&cpu0intctrl 11
 212                                                 &cpu1intctrl 11 &cpu1intctrl 9
 213                                                 &cpu2intctrl 11 &cpu2intctrl 9
 214                                                 &cpu3intctrl 11 &cpu3intctrl 9
 215                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 216                         interrupt-controller;
 217                         #interrupt-cells = <1>;
 218                         riscv,max-priority = <7>;
 219                         riscv,ndev = <136>;
 220                 };
 221
 222                 clkgen: clock-controller {
 223                         compatible = "starfive,jh7110-clkgen";
 224                         reg = <0x0 0x13020000 0x0 0x10000>,
 225                                 <0x0 0x10230000 0x0 0x10000>,
 226                                 <0x0 0x17000000 0x0 0x10000>;
 227                         reg-names = "sys", "stg", "aon";
 228                         clocks = <&osc>, <&gmac1_rmii_refin>,
 229                                  <&gmac1_rgmii_rxin>,
 230                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 231                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 232                                  <&tdm_ext>, <&mclk_ext>,
 233                                  <&jtag_tck_inner>, <&bist_apb>,
 234                                  <&stg_apb>, <&clk_rtc>,
 235                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 236                         clock-names = "osc", "gmac1_rmii_refin",
 237                                 "gmac1_rgmii_rxin",
 238                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 239                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 240                                 "tdm_ext", "mclk_ext",
 241                                 "jtag_tck_inner", "bist_apb",
 242                                 "stg_apb", "clk_rtc",
 243                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 244                         #clock-cells = <1>;
 245                         status = "okay";
 246                 };
 247
 248                 clkvout: clock-controller@295C0000 {
 249                         compatible = "starfive,jh7110-clk-vout";
 250                         reg = <0x0 0x295C0000 0x0 0x10000>;
 251                         reg-names = "vout";
 252                         clocks = <&hdmitx0_pixelclk>,
 253                                  <&mipitx_dphy_rxesc>,
 254                                  <&mipitx_dphy_txbytehs>,
 255                                  <&clkgen JH7110_VOUT_SRC>,
 256                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 257                         clock-names = "hdmitx0_pixelclk",
 258                                       "mipitx_dphy_rxesc",
 259                                       "mipitx_dphy_txbytehs",
 260                                       "vout_src",
 261                                       "vout_top_ahb";
 262                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 263                         reset-names = "vout_src";
 264                         #clock-cells = <1>;
 265                         power-domains = <&pwrc JH7110_PD_VOUT>;
 266                         status = "okay";
 267                 };
 268
 269                 clkisp: clock-controller@19810000 {
 270                         compatible = "starfive,jh7110-clk-isp";
 271                         reg = <0x0 0x19810000 0x0 0x10000>;
 272                         reg-names = "isp";
 273                         #clock-cells = <1>;
 274                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 275                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 276                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 277                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 278                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 279                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 280                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 281                                       "u0_sft7110_noc_bus_clk_isp_axi";
 282                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 283                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 284                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 285                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 286                                       "rst_isp_noc_bus_n";
 287                         power-domains = <&pwrc JH7110_PD_ISP>;
 288                         status = "okay";
 289                 };
 290
 291                 qspi: spi@13010000 {
 292                         compatible = "cdns,qspi-nor";
 293                         #address-cells = <1>;
 294                         #size-cells = <0>;
 295                         reg = <0x0 0x13010000 0x0 0x10000
 296                                 0x0 0x21000000 0x0 0x400000>;
 297                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 298                         clock-names = "clk_ref";
 299                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 300                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 301                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 302                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 303                         cdns,fifo-depth = <256>;
 304                         cdns,fifo-width = <4>;
 305                         spi-max-frequency = <250000000>;
 306
 307                         nor_flash: nor-flash@0 {
 308                                 compatible = "jedec,spi-nor";
 309                                 reg=<0>;
 310                                 spi-max-frequency = <100000000>;
 311                                 cdns,tshsl-ns = <1>;
 312                                 cdns,tsd2d-ns = <1>;
 313                                 cdns,tchsh-ns = <1>;
 314                                 cdns,tslch-ns = <1>;
 315                         };
 316                 };
 317
 318                 otp: otp@17050000 {
 319                         compatible = "starfive,jh7110-otp";
 320                         reg = <0x0 0x17050000 0x0 0x10000>;
 321                         clock-frequency = <4000000>;
 322                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 323                         clock-names = "apb";
 324                 };
 325
 326                 usbdrd30: usbdrd{
 327                         compatible = "starfive,jh7110-cdns3";
 328                         clocks = <&clkgen JH7110_USB_125M>,
 329                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 330                                  <&clkgen JH7110_USB0_CLK_LPM>,
 331                                  <&clkgen JH7110_USB0_CLK_STB>,
 332                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 333                                  <&clkgen JH7110_USB0_CLK_AXI>,
 334                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 335                         clock-names = "125m","app","lpm","stb","apb","axi","utmi";
 336                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 337                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 338                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 339                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 340                         reset-names = "pwrup","apb","axi","utmi";
 341                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 342                         starfive,sys-syscon = <&sys_syscon 0x18>;
 343                         status = "disabled";
 344                         #address-cells = <2>;
 345                         #size-cells = <2>;
 346                         #interrupt-cells = <1>;
 347                         ranges;
 348                         usbdrd_cdns3: usb@10100000 {
 349                                 compatible = "cdns,usb3";
 350                                 reg = <0x0 0x10100000 0x0 0x10000>,
 351                                       <0x0 0x10110000 0x0 0x10000>,
 352                                       <0x0 0x10120000 0x0 0x10000>;
 353                                 reg-names = "otg", "xhci", "dev";
 354                                 interrupts = <100>, <109>, <110>;
 355                                 interrupt-names = "host", "peripheral", "otg";
 356                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 357                                 maximum-speed = "super-speed";
 358                         };
 359                 };
 360
 361                 timer: timer@13050000 {
 362                         compatible = "starfive,si5-timers";
 363                         reg = <0x0 0x13050000 0x0 0x10000>;
 364                         interrupts = <69>, <70>, <71> ,<72>;
 365                         interrupt-names = "timer0", "timer1",
 366                                           "timer2", "timer3";
 367                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 368                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 369                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 370                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 371                                  <&clkgen JH7110_TIMER_CLK_APB>;
 372                         clock-names = "timer0", "timer1",
 373                                       "timer2", "timer3", "apb_clk";
 374                         clock-frequency = <24000000>;
 375                         status = "okay";
 376                 };
 377
 378                 wdog: wdog@13070000 {
 379                         compatible = "starfive,dskit-wdt";
 380                         reg = <0x0 0x13070000 0x0 0x10000>;
 381                         interrupts = <68>;
 382                         interrupt-names = "wdog";
 383                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 384                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 385                         clock-names = "core_clk", "apb_clk";
 386                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 387                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 388                         reset-names = "rst_apb", "rst_core";
 389                         timeout-sec = <15>;
 390                         status = "okay";
 391                 };
 392
 393                 rtc: rtc@17040000 {
 394                         compatible = "starfive,rtc_hms";
 395                         reg = <0x0 0x17040000 0x0 0x10000>;
 396                         interrupts = <10>, <11>, <12>;
 397                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 398                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 399                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 400                         clock-names = "pclk", "cal_clk";
 401                         resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
 402                                  <&rstgen RSTN_U0_RTC_HMS_CAL>,
 403                                  <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
 404                         reset-names = "rst_apb", "rst_cal", "rst_osc";
 405                         rtc,cal-clock-freq = <1000000>;
 406                         status = "okay";
 407                 };
 408
 409                 pwrc: power-controller@17030000 {
 410                         compatible = "starfive,jh7110-pmu";
 411                         reg = <0x0 0x17030000 0x0 0x10000>;
 412                         interrupts = <111>;
 413                         #power-domain-cells = <1>;
 414                         status = "okay";
 415                 };
 416
 417                 uart0: serial@10000000 {
 418                         compatible = "snps,dw-apb-uart";
 419                         reg = <0x0 0x10000000 0x0 0x10000>;
 420                         reg-io-width = <4>;
 421                         reg-shift = <2>;
 422                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 423                                  <&clkgen JH7110_UART0_CLK_APB>;
 424                         clock-names = "baudclk", "apb_pclk";
 425                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 426                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 427                         interrupts = <32>;
 428                         status = "disabled";
 429                 };
 430
 431                 uart1: serial@10010000 {
 432                         compatible = "snps,dw-apb-uart";
 433                         reg = <0x0 0x10010000 0x0 0x10000>;
 434                         reg-io-width = <4>;
 435                         reg-shift = <2>;
 436                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 437                                  <&clkgen JH7110_UART1_CLK_APB>;
 438                         clock-names = "baudclk", "apb_pclk";
 439                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 440                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 441                         interrupts = <33>;
 442                         status = "disabled";
 443                 };
 444
 445                 uart2: serial@10020000 {
 446                         compatible = "snps,dw-apb-uart";
 447                         reg = <0x0 0x10020000 0x0 0x10000>;
 448                         reg-io-width = <4>;
 449                         reg-shift = <2>;
 450                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 451                                  <&clkgen JH7110_UART2_CLK_APB>;
 452                         clock-names = "baudclk", "apb_pclk";
 453                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 454                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 455                         interrupts = <34>;
 456                         status = "disabled";
 457                 };
 458
 459                 uart3: serial@12000000 {
 460                         compatible = "snps,dw-apb-uart";
 461                         reg = <0x0 0x12000000 0x0 0x10000>;
 462                         reg-io-width = <4>;
 463                         reg-shift = <2>;
 464                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 465                                  <&clkgen JH7110_UART3_CLK_APB>;
 466                         clock-names = "baudclk", "apb_pclk";
 467                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 468                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 469                         interrupts = <45>;
 470                         status = "disabled";
 471                 };
 472
 473                 uart4: serial@12010000 {
 474                         compatible = "snps,dw-apb-uart";
 475                         reg = <0x0 0x12010000 0x0 0x10000>;
 476                         reg-io-width = <4>;
 477                         reg-shift = <2>;
 478                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 479                                  <&clkgen JH7110_UART4_CLK_APB>;
 480                         clock-names = "baudclk", "apb_pclk";
 481                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 482                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 483                         interrupts = <46>;
 484                         status = "disabled";
 485                 };
 486
 487                 uart5: serial@12020000 {
 488                         compatible = "snps,dw-apb-uart";
 489                         reg = <0x0 0x12020000 0x0 0x10000>;
 490                         reg-io-width = <4>;
 491                         reg-shift = <2>;
 492                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 493                                  <&clkgen JH7110_UART5_CLK_APB>;
 494                         clock-names = "baudclk", "apb_pclk";
 495                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 496                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 497                         interrupts = <47>;
 498                         status = "disabled";
 499                 };
 500
 501                 dma: dma-controller@16050000 {
 502                         compatible = "starfive,axi-dma";
 503                         reg = <0x0 0x16050000 0x0 0x10000>;
 504                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 505                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 506                         clock-names = "core-clk", "cfgr-clk";
 507                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 508                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 509                         reset-names = "rst_axi", "rst_ahb";
 510                         interrupts = <73>;
 511                         #dma-cells = <2>;
 512                         dma-channels = <4>;
 513                         snps,dma-masters = <1>;
 514                         snps,data-width = <3>;
 515                         snps,num-hs-if = <56>;
 516                         snps,block-size = <65536 65536 65536 65536>;
 517                         snps,priority = <0 1 2 3>;
 518                         snps,axi-max-burst-len = <16>;
 519                         status = "disabled";
 520                 };
 521
 522                 gpio: gpio@13040000 {
 523                         compatible = "starfive,jh7110-sys-pinctrl";
 524                         reg = <0x0 0x13040000 0x0 0x10000>;
 525                         reg-names = "control";
 526                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 527                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 528                         interrupts = <86>;
 529                         interrupt-controller;
 530                         #gpio-cells = <2>;
 531                         ngpios = <64>;
 532                         status = "okay";
 533                 };
 534
 535                 gpioa: gpio@17020000 {
 536                         compatible = "starfive,jh7110-aon-pinctrl";
 537                         reg = <0x0 0x17020000 0x0 0x10000>;
 538                         reg-names = "control";
 539                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 540                         interrupts = <85>;
 541                         interrupt-controller;
 542                         #gpio-cells = <2>;
 543                         ngpios = <4>;
 544                         status = "okay";
 545                 };
 546
 547                 sfctemp: tmon@120e0000  {
 548                         compatible = "starfive,jh7110-temp";
 549                         reg = <0x0 0x120e0000 0x0 0x10000>;
 550                         interrupts = <81>;
 551                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 552                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 553                         clock-names = "sense", "bus";
 554                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 555                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 556                         reset-names = "sense", "bus";
 557                         #thermal-sensor-cells = <0>;
 558                         status = "disabled";
 559                 };
 560
 561                 thermal-zones {
 562                         cpu-thermal {
 563                                 polling-delay-passive = <250>;
 564                                 polling-delay = <15000>;
 565
 566                                 thermal-sensors = <&sfctemp>;
 567
 568                                 cooling-maps {
 569                                 };
 570
 571                                 trips {
 572                                         cpu_alert0: cpu_alert0 {
 573                                                 /* milliCelsius */
 574                                                 temperature = <75000>;
 575                                                 hysteresis = <2000>;
 576                                                 type = "passive";
 577                                         };
 578
 579                                         cpu_crit: cpu_crit {
 580                                                 /* milliCelsius */
 581                                                 temperature = <90000>;
 582                                                 hysteresis = <2000>;
 583                                                 type = "critical";
 584                                         };
 585                                 };
 586                         };
 587                 };
 588
 589                 trng: trng@1600C000 {
 590                         compatible = "starfive,trng";
 591                         reg = <0x0 0x1600C000 0x0 0x4000>;
 592                         clocks = <&clkgen JH7110_SEC_HCLK>,
 593                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 594                         clock-names = "hclk", "miscahb_clk";
 595                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 596                         interrupts = <30>;
 597                         status = "disabled";
 598                 };
 599
 600                 sec_dma: sec_dma@16008000 {
 601                         /*compatible = "arm,pl080", "arm,primecell";*/
 602                         compatible = "starfive,pl080";
 603                         reg = <0x0 0x16008000 0x0 0x4000>;
 604                         reg-names = "sec_dma";
 605                         interrupts = <29>;
 606                         clocks = <&clkgen JH7110_SEC_HCLK>,
 607                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 608                         clock-names = "sec_hclk","sec_ahb";
 609                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 610                         reset-names = "sec_hre";
 611                         lli-bus-interface-ahb1;
 612                         mem-bus-interface-ahb1;
 613                         memcpy-burst-size = <256>;
 614                         memcpy-bus-width = <32>;
 615                         #dma-cells = <2>;
 616                         status = "disabled";
 617                 };
 618
 619                 crypto: crypto@16000000 {
 620                         compatible = "starfive,jh7110-sec";
 621                         reg = <0x0 0x16000000 0x0 0x4000>,
 622                               <0x0 0x16008000 0x0 0x4000>;
 623                         reg-names = "secreg","secdma";
 624                         interrupts = <28>, <29>;
 625                         interrupt-names = "secirq", "dmairq";
 626                         clocks = <&clkgen JH7110_SEC_HCLK>,
 627                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 628                         clock-names = "sec_hclk","sec_ahb";
 629                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 630                         reset-names = "sec_hre";
 631                         enable-side-channel-mitigation = "true";
 632                         enable-dma = "true";
 633                         dmas = <&sec_dma 1 2>,
 634                                <&sec_dma 0 2>;
 635                         dma-names = "sec_m","sec_p";
 636                         status = "disabled";
 637                 };
 638
 639                 i2c0: i2c@10030000 {
 640                         compatible = "snps,designware-i2c";
 641                         reg = <0x0 0x10030000 0x0 0x10000>;
 642                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 643                                  <&clkgen JH7110_I2C0_CLK_APB>;
 644                         clock-names = "ref", "pclk";
 645                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 646                         interrupts = <35>;
 647                         #address-cells = <1>;
 648                         #size-cells = <0>;
 649                         status = "disabled";
 650                 };
 651
 652                 i2c1: i2c@10040000 {
 653                         compatible = "snps,designware-i2c";
 654                         reg = <0x0 0x10040000 0x0 0x10000>;
 655                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 656                                  <&clkgen JH7110_I2C1_CLK_APB>;
 657                         clock-names = "ref", "pclk";
 658                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 659                         interrupts = <36>;
 660                         #address-cells = <1>;
 661                         #size-cells = <0>;
 662                         status = "disabled";
 663                 };
 664
 665                 i2c2: i2c@10050000 {
 666                         compatible = "snps,designware-i2c";
 667                         reg = <0x0 0x10050000 0x0 0x10000>;
 668                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 669                                  <&clkgen JH7110_I2C2_CLK_APB>;
 670                         clock-names = "ref", "pclk";
 671                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 672                         interrupts = <37>;
 673                         #address-cells = <1>;
 674                         #size-cells = <0>;
 675                         status = "disabled";
 676                 };
 677
 678                 i2c3: i2c@12030000 {
 679                         compatible = "snps,designware-i2c";
 680                         reg = <0x0 0x12030000 0x0 0x10000>;
 681                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 682                                  <&clkgen JH7110_I2C3_CLK_APB>;
 683                         clock-names = "ref", "pclk";
 684                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 685                         interrupts = <48>;
 686                         #address-cells = <1>;
 687                         #size-cells = <0>;
 688                         status = "disabled";
 689                 };
 690
 691                 i2c4: i2c@12040000 {
 692                         compatible = "snps,designware-i2c";
 693                         reg = <0x0 0x12040000 0x0 0x10000>;
 694                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 695                                  <&clkgen JH7110_I2C4_CLK_APB>;
 696                         clock-names = "ref", "pclk";
 697                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 698                         interrupts = <49>;
 699                         #address-cells = <1>;
 700                         #size-cells = <0>;
 701                         status = "disabled";
 702                 };
 703
 704                 i2c5: i2c@12050000 {
 705                         compatible = "snps,designware-i2c";
 706                         reg = <0x0 0x12050000 0x0 0x10000>;
 707                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 708                                  <&clkgen JH7110_I2C5_CLK_APB>;
 709                         clock-names = "ref", "pclk";
 710                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 711                         interrupts = <50>;
 712                         #address-cells = <1>;
 713                         #size-cells = <0>;
 714                         status = "disabled";
 715                 };
 716
 717                 i2c6: i2c@12060000 {
 718                         compatible = "snps,designware-i2c";
 719                         reg = <0x0 0x12060000 0x0 0x10000>;
 720                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 721                                  <&clkgen JH7110_I2C6_CLK_APB>;
 722                         clock-names = "ref", "pclk";
 723                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 724                         interrupts = <51>;
 725                         #address-cells = <1>;
 726                         #size-cells = <0>;
 727                         status = "disabled";
 728                 };
 729
 730                 /* unremovable emmc as mmcblk0 */
 731                 sdio0: sdio0@16010000 {
 732                         compatible = "snps,dw-mshc";
 733                         reg = <0x0 0x16010000 0x0 0x10000>;
 734                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 735                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 736                         clock-names = "biu","ciu";
 737                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 738                         reset-names = "reset";
 739                         interrupts = <74>;
 740                         fifo-depth = <32>;
 741                         fifo-watermark-aligned;
 742                         data-addr = <0>;
 743                         status = "disabled";
 744                 };
 745
 746                 sdio1: sdio1@16020000 {
 747                         compatible = "snps,dw-mshc";
 748                         reg = <0x0 0x16020000 0x0 0x10000>;
 749                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 750                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 751                         clock-names = "biu","ciu";
 752                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 753                         reset-names = "reset";
 754                         interrupts = <75>;
 755                         fifo-depth = <32>;
 756                         fifo-watermark-aligned;
 757                         data-addr = <0>;
 758                         status = "disabled";
 759                 };
 760
 761                 vin_sysctl: vin_sysctl@19800000 {
 762                         compatible = "starfive,stf-vin";
 763                         reg = <0x0 0x19800000 0x0 0x10000>,
 764                                 <0x0 0x19810000 0x0 0x10000>,
 765                                 <0x0 0x19820000 0x0 0x10000>,
 766                                 <0x0 0x19830000 0x0 0x10000>,
 767                                 <0x0 0x19840000 0x0 0x10000>,
 768                                 <0x0 0x19870000 0x0 0x30000>,
 769                                 <0x0 0x11840000 0x0 0x10000>,
 770                                 <0x0 0x17030000 0x0 0x10000>,
 771                                 <0x0 0x13020000 0x0 0x10000>;
 772                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
 773                                 "isp", "trst", "pmu", "syscrg";
 774                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 775                                  <&clkisp JH7110_U0_VIN_PCLK>,
 776                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 777                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 778                                  <&clkisp JH7110_DVP_INV>,
 779                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 780                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 781                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 782                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 783                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 784                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 785                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 786                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 787                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 788                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 789                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 790                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 791                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 792                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 793                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 794                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 795                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 796                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 797                                 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
 798                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 799                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 800                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 801                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 802                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 803                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 804                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 805                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 806                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 807                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 808                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 809                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 810                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 811                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 812                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 813                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 814                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 815                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 816                                 "rst_isp_top_n", "rst_isp_top_axi";
 817                         starfive,aon-syscon = <&aon_syscon 0x00>;
 818                         power-domains = <&pwrc JH7110_PD_ISP>;
 819                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 820                         interrupts = <92 87 88 89 90>;
 821                         status = "disabled";
 822                 };
 823
 824                 jpu: jpu@11900000 {
 825                         compatible = "starfive,jpu";
 826                         reg = <0x0 0x13090000 0x0 0x300>;
 827                         interrupts = <14>;
 828                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 829                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 830                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 831                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 832                         clock-names = "axi_clk", "core_clk",
 833                                       "apb_clk", "noc_bus";
 834                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 835                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 836                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 837                         reset-names = "rst_axi", "rst_core", "rst_apb";
 838                         power-domains = <&pwrc JH7110_PD_VDEC>;
 839                         status = "disabled";
 840                 };
 841
 842                 vpu_dec: vpu_dec@130A0000 {
 843                         compatible = "starfive,vdec";
 844                         reg = <0x0 0x130A0000 0x0 0x10000>;
 845                         interrupts = <13>;
 846                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 847                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 848                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 849                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 850                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 851                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 852                                       "apb_clk", "noc_bus";
 853                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 854                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 855                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 856                                 <&rstgen RSTN_U0_WAVE511_APB>,
 857                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 858                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 859                                       "rst_apb", "rst_sram";
 860                         starfive,vdec_noc_ctrl;
 861                         power-domains = <&pwrc JH7110_PD_VDEC>;
 862                         status = "disabled";
 863                 };
 864
 865                 vpu_enc: vpu_enc@130B0000 {
 866                         compatible = "starfive,venc";
 867                         reg = <0x0 0x130B0000 0x0 0x10000>;
 868                         interrupts = <15>;
 869                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 870                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 871                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 872                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 873                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 874                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 875                                       "apb_clk", "noc_bus";
 876                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 877                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 878                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 879                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 880                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 881                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 882                                       "rst_apb", "rst_sram";
 883                         starfive,venc_noc_ctrl;
 884                         power-domains = <&pwrc JH7110_PD_VENC>;
 885                         status = "disabled";
 886                 };
 887
 888                 rstgen: reset-controller {
 889                         compatible = "starfive,jh7110-reset";
 890                         reg = <0x0 0x13020000 0x0 0x10000>,
 891                                 <0x0 0x10230000 0x0 0x10000>,
 892                                 <0x0 0x17000000 0x0 0x10000>,
 893                                 <0x0 0x19810000 0x0 0x10000>,
 894                                 <0x0 0x295C0000 0x0 0x10000>;
 895                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 896                         #reset-cells = <1>;
 897                         status = "okay";
 898                 };
 899
 900                 stmmac_axi_setup: stmmac-axi-config {
 901                         snps,wr_osr_lmt = <0xf>;
 902                         snps,rd_osr_lmt = <0xf>;
 903                         snps,blen = <256 128 64 32 0 0 0>;
 904                 };
 905
 906                 gmac0: ethernet@16030000 {
 907                         compatible = "starfive,jh7110-eqos-5.20";
 908                         reg = <0x0 0x16030000 0x0 0x10000>;
 909                         clock-names = "gtx",
 910                                 "tx",
 911                                 "ptp_ref",
 912                                 "stmmaceth",
 913                                 "pclk",
 914                                 "gtxc";
 915                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 916                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 917                                  <&clkgen JH7110_GMAC0_PTP>,
 918                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 919                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 920                                  <&clkgen JH7110_GMAC0_GTXC>;
 921                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 922                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 923                         reset-names = "ahb", "stmmaceth";
 924                         interrupts = <7>, <6>, <5> ;
 925                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 926                         max-frame-size = <9000>;
 927                         phy-mode = "rgmii-id";
 928                         snps,multicast-filter-bins = <64>;
 929                         snps,perfect-filter-entries = <128>;
 930                         rx-fifo-depth = <2048>;
 931                         tx-fifo-depth = <2048>;
 932                         snps,fixed-burst;
 933                         snps,no-pbl-x8;
 934                         snps,force_thresh_dma_mode;
 935                         snps,axi-config = <&stmmac_axi_setup>;
 936                         snps,tso;
 937                         snps,en-tx-lpi-clockgating;
 938                         snps,en-lpi;
 939                         snps,write-requests = <4>;
 940                         snps,read-requests = <4>;
 941                         snps,burst-map = <0x7>;
 942                         snps,txpbl = <16>;
 943                         snps,rxpbl = <16>;
 944                         status = "disabled";
 945                 };
 946
 947                 gmac1: ethernet@16040000 {
 948                         compatible = "starfive,jh7110-eqos-5.20";
 949                         reg = <0x0 0x16040000 0x0 0x10000>;
 950                         clock-names = "gtx",
 951                                 "tx",
 952                                 "ptp_ref",
 953                                 "stmmaceth",
 954                                 "pclk",
 955                                 "gtxc";
 956                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 957                                  <&clkgen JH7110_GMAC5_CLK_TX>,
 958                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
 959                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
 960                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
 961                                  <&clkgen JH7110_GMAC1_GTXC>;
 962                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
 963                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 964                         reset-names = "ahb", "stmmaceth";
 965                         interrupts = <78>, <77>, <76> ;
 966                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 967                         max-frame-size = <9000>;
 968                         phy-mode = "rgmii-id";
 969                         snps,multicast-filter-bins = <64>;
 970                         snps,perfect-filter-entries = <128>;
 971                         rx-fifo-depth = <2048>;
 972                         tx-fifo-depth = <2048>;
 973                         snps,fixed-burst;
 974                         snps,no-pbl-x8;
 975                         snps,force_thresh_dma_mode;
 976                         snps,axi-config = <&stmmac_axi_setup>;
 977                         snps,tso;
 978                         snps,en-tx-lpi-clockgating;
 979                         snps,en-lpi;
 980                         snps,write-requests = <4>;
 981                         snps,read-requests = <4>;
 982                         snps,burst-map = <0x7>;
 983                         snps,txpbl = <16>;
 984                         snps,rxpbl = <16>;
 985                         status = "disabled";
 986                 };
 987
 988                 gpu: gpu@18000000 {
 989                         compatible = "img-gpu";
 990                         reg = <0x0 0x18000000 0x0 0x100000>,
 991                                 <0x0 0x130C000 0x0 0x10000>;
 992                         clocks = <&clkgen JH7110_GPU_CLK_APB>,
 993                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
 994                                  <&clkgen JH7110_GPU_CORE_CLK>,
 995                                  <&clkgen JH7110_GPU_SYS_CLK>,
 996                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
 997                         clock-names = "clk_apb", "clk_rtc", "clk_core",
 998                                         "clk_sys", "clk_axi";
 999                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1000                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1001                         reset-names = "rst_apb", "rst_doma";
1002                         power-domains = <&pwrc JH7110_PD_GPUA>;
1003                         interrupts = <82>;
1004                         current-clock = <8000000>;
1005                         status = "disabled";
1006                 };
1007
1008                 can0: can@130d0000 {
1009                         compatible = "ipms,can";
1010                         reg = <0x0 0x130d0000 0x0 0x1000>;
1011                         interrupts = <112>;
1012                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1013                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1014                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1015                         clock-names = "apb_clk", "core_clk", "timer_clk";
1016                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1017                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1018                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1019                         reset-names = "rst_apb", "rst_core", "rst_timer";
1020                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1021                         syscon,can_or_canfd = <0>;
1022                         status = "disabled";
1023                 };
1024
1025                 can1: can@130e0000 {
1026                         compatible = "ipms,can";
1027                         reg = <0x0 0x130e0000 0x0 0x1000>;
1028                         interrupts = <113>;
1029                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1030                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1031                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1032                         clock-names = "apb_clk", "core_clk", "timer_clk";
1033                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1034                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1035                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1036                         reset-names = "rst_apb", "rst_core", "rst_timer";
1037                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1038                         syscon,can_or_canfd = <0>;
1039                         status = "disabled";
1040                 };
1041
1042                 tdm: tdm@10090000 {
1043                         compatible = "starfive,sf-tdm";
1044                         reg = <0x0 0x10090000 0x0 0x1000>;
1045                         reg-names = "tdm";
1046                         clocks = <&clkgen JH7110_AHB0>,
1047                                  <&clkgen JH7110_TDM_CLK_AHB>,
1048                                  <&clkgen JH7110_APB0>,
1049                                  <&clkgen JH7110_TDM_CLK_APB>,
1050                                  <&clkgen JH7110_TDM_INTERNAL>,
1051                                  <&tdm_ext>,
1052                                  <&clkgen JH7110_TDM_CLK_TDM>,
1053                                  <&clkgen JH7110_MCLK_INNER>;
1054                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1055                                       "clk_apb0", "clk_tdm_apb",
1056                                       "clk_tdm_internal", "clk_tdm_ext",
1057                                       "clk_tdm", "mclk_inner";
1058                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1059                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1060                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1061                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1062                         dmas = <&dma 20 1>, <&dma 21 1>;
1063                         dma-names = "rx","tx";
1064                         #sound-dai-cells = <0>;
1065                         status = "disabled";
1066                 };
1067
1068                 spdif0: spdif0@100a0000 {
1069                         compatible = "starfive,sf-spdif";
1070                         reg = <0x0 0x100a0000 0x0 0x1000>;
1071                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1072                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1073                                  <&clkgen JH7110_APB0>,
1074                                  <&clkgen JH7110_AUDIO_ROOT>,
1075                                  <&clkgen JH7110_MCLK_INNER>;
1076                         clock-names = "spdif-apb", "spdif-core", "apb0",
1077                                       "audroot", "mclk_inner";
1078                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1079                         reset-names = "rst_apb";
1080                         interrupts = <84>;
1081                         interrupt-names = "tx";
1082                         #sound-dai-cells = <0>;
1083                         status = "disabled";
1084                 };
1085
1086                 pwmdac: pwmdac@100b0000 {
1087                         compatible = "starfive,pwmdac";
1088                         reg = <0x0 0x100b0000 0x0 0x1000>;
1089                         clocks = <&clkgen JH7110_APB0>,
1090                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1091                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1092                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1093                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1094                         reset-names = "rst-apb";
1095                         dmas = <&dma 22 1>;
1096                         dma-names = "tx";
1097                         #sound-dai-cells = <0>;
1098                         status = "disabled";
1099                 };
1100
1101                 i2stx: i2stx@100c0000 {
1102                         compatible = "snps,designware-i2stx";
1103                         reg = <0x0 0x100c0000 0x0 0x1000>;
1104                         interrupt-names = "tx";
1105                         #sound-dai-cells = <0>;
1106                         dmas = <&dma 28 1>;
1107                         dma-names = "rx";
1108                         status = "disabled";
1109                 };
1110
1111                 pdm: pdm@100d0000 {
1112                         compatible = "starfive,sf-pdm";
1113                         reg = <0x0 0x100d0000 0x0 0x1000>;
1114                         reg-names = "pdm";
1115                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1116                                  <&clkgen JH7110_APB0>,
1117                                  <&clkgen JH7110_PDM_CLK_APB>,
1118                                  <&clkgen JH7110_MCLK_INNER>,
1119                                  <&clkgen JH7110_MCLK>,
1120                                  <&clkgen JH7110_MCLK_OUT>;
1121                         clock-names = "pdm_mclk", "clk_apb0",
1122                                       "pdm_apb", "mclk_inner",
1123                                       "clk_mclk", "mclk_out";
1124                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1125                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1126                         reset-names = "pdm_dmic", "pdm_apb";
1127                         #sound-dai-cells = <0>;
1128                 };
1129
1130                 i2srx_mst: i2srx_mst@100e0000 {
1131                         compatible = "snps,i2srx-master";
1132                         reg = <0x0 0x100e0000 0x0 0x1000>;
1133                         clocks = <&clkgen JH7110_APB0>,
1134                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1135                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1136                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1137                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1138                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1139                         clock-names = "apb0", "i2srx_apb",
1140                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1141                                       "i2srx_bclk", "i2srx_lrck";
1142                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1143                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1144                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1145                         dmas = <&dma 24 1>;
1146                         dma-names = "rx";
1147                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1148                         #sound-dai-cells = <0>;
1149                         status = "disabled";
1150                 };
1151
1152                 i2srx_3ch: i2srx_3ch@100e0000 {
1153                         compatible = "snps,designware-i2srx";
1154                         reg = <0x0 0x100e0000 0x0 0x1000>;
1155                         clocks = <&clkgen JH7110_APB0>,
1156                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1157                                  <&clkgen JH7110_AUDIO_ROOT>,
1158                                  <&clkgen JH7110_MCLK_INNER>,
1159                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1160                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1161                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1162                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1163                         clock-names = "apb0", "3ch-apb",
1164                                         "audioroot", "mclk-inner",
1165                                         "bclk_mst", "3ch-lrck",
1166                                         "rx-bclk", "rx-lrck";
1167                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1168                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1169                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1170                         dmas = <&dma 24 1>;
1171                         dma-names = "rx";
1172                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1173                         #sound-dai-cells = <0>;
1174                         status = "disabled";
1175                 };
1176
1177                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1178                         compatible = "snps,designware-i2stx-4ch0";
1179                         reg = <0x0 0x120b0000 0x0 0x1000>;
1180                         clocks = <&clkgen JH7110_MCLK_INNER>,
1181                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1182                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1183                                  <&clkgen JH7110_MCLK>,
1184                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1185                                  <&clkgen JH7110_I2STX0_4CHLRCK>;
1186                         clock-names = "inner", "bclk-mst",
1187                                         "lrck-mst", "mclk",
1188                                         "bclk0", "lrck0";
1189                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1190                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1191                         reset-names = "rst_apb0", "rst_bclk0";
1192                         dmas = <&dma 47 1>;
1193                         dma-names = "tx";
1194                         #sound-dai-cells = <0>;
1195                         status = "disabled";
1196                 };
1197
1198                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1199                         compatible = "snps,designware-i2stx-4ch1";
1200                         reg = <0x0 0x120c0000 0x0 0x1000>;
1201                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1202                                  <&clkgen JH7110_MCLK_INNER>,
1203                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1204                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1205                                  <&clkgen JH7110_MCLK>,
1206                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1207                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1208                                  <&clkgen JH7110_MCLK_OUT>,
1209                                  <&clkgen JH7110_APB0>,
1210                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1211                                  <&mclk_ext>,
1212                                  <&i2stx_bclk_ext>,
1213                                  <&i2stx_lrck_ext>;
1214                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1215                                         "lrck_mst", "mclk", "4chbclk",
1216                                         "4chlrck", "mclk_out",
1217                                         "apb0", "clk_apb",
1218                                         "mclk_ext", "bclk_ext", "lrck_ext";
1219
1220                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1221                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1222                         reset-names = "rst_apb1", "rst_bclk1";
1223                         dmas = <&dma 48 1>;
1224                         dma-names = "tx";
1225                         #sound-dai-cells = <0>;
1226                         status = "disabled";
1227                 };
1228
1229                 ptc: pwm@120d0000 {
1230                         compatible = "starfive,pwm";
1231                         reg = <0x0 0x120d0000 0x0 0x10000>;
1232                         reg-names = "control";
1233                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1234                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1235                         starfive,approx-freq = <2000000>;
1236                         #pwm-cells=<3>;
1237                         starfive,npwm = <8>;
1238                         status = "disabled";
1239                 };
1240
1241                 spdif_transmitter: spdif_transmitter {
1242                         compatible = "linux,spdif-dit";
1243                         #sound-dai-cells = <0>;
1244                         status = "disabled";
1245                 };
1246
1247                 spdif_receiver: spdif_receiver {
1248                         compatible = "linux,spdif-dir";
1249                         #sound-dai-cells = <0>;
1250                         status = "disabled";
1251                 };
1252
1253                 pwmdac_codec: pwmdac-transmitter {
1254                         compatible = "linux,pwmdac-dit";
1255                         #sound-dai-cells = <0>;
1256                         status = "disabled";
1257                 };
1258
1259                 dmic_codec: dmic_codec {
1260                         compatible = "dmic-codec";
1261                         #sound-dai-cells = <0>;
1262                         status = "disabled";
1263                 };
1264
1265                 spi0: spi@10060000 {
1266                         compatible = "arm,pl022", "arm,primecell";
1267                         reg = <0x0 0x10060000 0x0 0x10000>;
1268                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1269                         clock-names = "apb_pclk";
1270                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1271                         reset-names = "rst_apb";
1272                         interrupts = <38>;
1273                         /* shortage of dma channel that not be used */
1274                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1275                         /*dma-names = "rx","tx";*/
1276                         arm,primecell-periphid = <0x00041022>;
1277                         num-cs = <1>;
1278                         #address-cells = <1>;
1279                         #size-cells = <0>;
1280                         status = "disabled";
1281                 };
1282
1283                 spi1: spi@10070000 {
1284                         compatible = "arm,pl022", "arm,primecell";
1285                         reg = <0x0 0x10070000 0x0 0x10000>;
1286                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1287                         clock-names = "apb_pclk";
1288                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1289                         reset-names = "rst_apb";
1290                         interrupts = <39>;
1291                         /* shortage of dma channel that not be used */
1292                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1293                         /*dma-names = "rx","tx";*/
1294                         arm,primecell-periphid = <0x00041022>;
1295                         num-cs = <1>;
1296                         #address-cells = <1>;
1297                         #size-cells = <0>;
1298                         status = "disabled";
1299                 };
1300
1301                 spi2: spi@10080000 {
1302                         compatible = "arm,pl022", "arm,primecell";
1303                         reg = <0x0 0x10080000 0x0 0x10000>;
1304                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1305                         clock-names = "apb_pclk";
1306                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1307                         reset-names = "rst_apb";
1308                         interrupts = <40>;
1309                         /* shortage of dma channel that not be used */
1310                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1311                         /*dma-names = "rx","tx";*/
1312                         arm,primecell-periphid = <0x00041022>;
1313                         num-cs = <1>;
1314                         #address-cells = <1>;
1315                         #size-cells = <0>;
1316                         status = "disabled";
1317                 };
1318
1319                 spi3: spi@12070000 {
1320                         compatible = "arm,pl022", "arm,primecell";
1321                         reg = <0x0 0x12070000 0x0 0x10000>;
1322                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1323                         clock-names = "apb_pclk";
1324                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1325                         reset-names = "rst_apb";
1326                         interrupts = <52>;
1327                         /* shortage of dma channel that not be used */
1328                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1329                         /*dma-names = "rx","tx";*/
1330                         arm,primecell-periphid = <0x00041022>;
1331                         num-cs = <1>;
1332                         #address-cells = <1>;
1333                         #size-cells = <0>;
1334                         status = "disabled";
1335                 };
1336
1337                 spi4: spi@12080000 {
1338                         compatible = "arm,pl022", "arm,primecell";
1339                         reg = <0x0 0x12080000 0x0 0x10000>;
1340                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1341                         clock-names = "apb_pclk";
1342                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1343                         reset-names = "rst_apb";
1344                         interrupts = <53>;
1345                         /* shortage of dma channel that not be used */
1346                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1347                         /*dma-names = "rx","tx";*/
1348                         arm,primecell-periphid = <0x00041022>;
1349                         num-cs = <1>;
1350                         #address-cells = <1>;
1351                         #size-cells = <0>;
1352                         status = "disabled";
1353                 };
1354
1355                 spi5: spi@12090000 {
1356                         compatible = "arm,pl022", "arm,primecell";
1357                         reg = <0x0 0x12090000 0x0 0x10000>;
1358                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1359                         clock-names = "apb_pclk";
1360                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1361                         reset-names = "rst_apb";
1362                         interrupts = <54>;
1363                         /* shortage of dma channel that not be used */
1364                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1365                         /*dma-names = "rx","tx";*/
1366                         arm,primecell-periphid = <0x00041022>;
1367                         num-cs = <1>;
1368                         #address-cells = <1>;
1369                         #size-cells = <0>;
1370                         status = "disabled";
1371                 };
1372
1373                 spi6: spi@120A0000 {
1374                         compatible = "arm,pl022", "arm,primecell";
1375                         reg = <0x0 0x120A0000 0x0 0x10000>;
1376                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1377                         clock-names = "apb_pclk";
1378                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1379                         reset-names = "rst_apb";
1380                         interrupts = <55>;
1381                         /* shortage of dma channel that not be used */
1382                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1383                         /*dma-names = "rx","tx";*/
1384                         arm,primecell-periphid = <0x00041022>;
1385                         num-cs = <1>;
1386                         #address-cells = <1>;
1387                         #size-cells = <0>;
1388                         status = "disabled";
1389                 };
1390
1391                 pcie0: pcie@2B000000 {
1392                         compatible = "plda,pci-xpressrich3-axi";
1393                         #address-cells = <3>;
1394                         #size-cells = <2>;
1395                         #interrupt-cells = <1>;
1396                         reg = <0x0 0x2B000000 0x0 0x1000000
1397                                0x9 0x40000000 0x0 0x10000000>;
1398                         reg-names = "reg", "config";
1399                         device_type = "pci";
1400                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1401                         bus-range = <0x0 0xff>;
1402                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>;
1403                         msi-parent = <&plic>;
1404                         interrupts = <56>;
1405                         interrupt-controller;
1406                         interrupt-names = "msi";
1407                         interrupt-parent = <&plic>;
1408                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1409                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1410                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1411                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1412                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1413                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1414                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1415                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1416                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1417                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1418                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1419                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1420                                       "rst_brg", "rst_core", "rst_apb";
1421                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1422                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1423                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1424                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1425                         clock-names = "noc", "tl", "axi_mst0", "apb";
1426                         status = "disabled";
1427                 };
1428
1429                 pcie1: pcie@2C000000 {
1430                         compatible = "plda,pci-xpressrich3-axi";
1431                         #address-cells = <3>;
1432                         #size-cells = <2>;
1433                         #interrupt-cells = <1>;
1434                         reg = <0x0 0x2C000000 0x0 0x1000000
1435                                0x9 0xc0000000 0x0 0x10000000>;
1436                         reg-names = "reg", "config";
1437                         device_type = "pci";
1438                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1439                         bus-range = <0x0 0xff>;
1440                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>;
1441                         msi-parent = <&plic>;
1442                         interrupts = <57>;
1443                         interrupt-controller;
1444                         interrupt-names = "msi";
1445                         interrupt-parent = <&plic>;
1446                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1447                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1448                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1449                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1450                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1451                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1452                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1453                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1454                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1455                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1456                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1457                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1458                                       "rst_brg", "rst_core", "rst_apb";
1459                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1460                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1461                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1462                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1463                         clock-names = "noc", "tl", "axi_mst0", "apb";
1464                         status = "disabled";
1465                 };
1466
1467                 mailbox_contrl0: mailbox@0 {
1468                         compatible = "starfive,mail_box";
1469                         reg = <0x0 0x13060000 0x0 0x0001000>;
1470                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1471                         clock-names = "clk_apb";
1472                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1473                         reset-names = "mbx_rre";
1474                         interrupts = <26 27>;
1475                         #mbox-cells = <2>;
1476                         status = "disabled";
1477                 };
1478
1479                 mailbox_client0: mailbox_client@0 {
1480                         compatible = "starfive,mailbox-test";
1481                         mbox-names = "rx", "tx";
1482                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1483                         status = "disabled";
1484                 };
1485
1486                 display: display-subsystem {
1487                         compatible = "verisilicon,display-subsystem";
1488                         ports = <&dc_out_dpi0>;
1489                         status = "disabled";
1490                 };
1491
1492                 dssctrl: dssctrl@295B0000 {
1493                         compatible = "verisilicon,dss-ctrl", "syscon";
1494                         reg = <0 0x295B0000 0 0x90>;
1495                 };
1496
1497                 tda988x_pin: tda988x_pin {
1498                         compatible = "starfive,tda998x_rgb_pin";
1499                         status = "disabled";
1500                 };
1501
1502                 hdmi_output: hdmi-output {
1503                         compatible = "verisilicon,hdmi-encoder";
1504                         //verisilicon,dss-syscon = <&dssctrl>;
1505                         //verisilicon,mux-mask = <0x70 0x380>;
1506                         //verisilicon,mux-val = <0x40 0x280>;
1507                         status = "disabled";
1508                 };
1509
1510                 dc8200: dc8200@29400000 {
1511                         compatible = "verisilicon,dc8200";
1512                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1513                         reg = <0x0 0x29400000 0x0 0x100>,
1514                               <0x0 0x29400800 0x0 0x2000>,
1515                               <0x0 0x17030000 0x0 0x1000>;
1516                         interrupts = <95>;
1517                         status = "disabled";
1518                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1519                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1520                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1521                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1522                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1523                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1524                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1525                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1526                                  <&clkgen JH7110_VOUT_SRC>,
1527                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1528                                  <&clkgen JH7110_AHB1>,
1529                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1530                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1531                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1532                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1533                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1534                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1535                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1536                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1537                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1538                                  <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1539                                  <&hdmitx0_pixelclk>,
1540                                  <&clkvout JH7110_DC8200_PIX0>,
1541                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1542                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1543                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1544                                         "noc_disp","noc_isp","noc_stg","vout_src",
1545                                         "top_vout_axi","ahb1","top_vout_ahb",
1546                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1547                                         "axi_clk","core_clk","vout_ahb",
1548                                         "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1549                                         "dc8200_pix0_out","dc8200_pix1_out";
1550                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1551                                  <&rstgen RSTN_U0_DC8200_AXI>,
1552                                  <&rstgen RSTN_U0_DC8200_AHB>,
1553                                  <&rstgen RSTN_U0_DC8200_CORE>,
1554                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1555                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1556                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1557                                  <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
1558                                  <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
1559                                  <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
1560                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1561                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
1562                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
1563                                  <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
1564                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1565                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1566                                         "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
1567                                         "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
1568                         power-domains = <&pwrc JH7110_PD_VOUT>;
1569                 };
1570
1571                 encoder: display-encoder {
1572                         compatible = "verisilicon,dsi-encoder";
1573                         status = "disabled";
1574                 };
1575
1576                 mipi_dphy: mipi-dphy@295e0000{
1577                         compatible = "starfive,jh7100-mipi-dphy-tx";
1578                         reg = <0x0 0x295e0000 0x0 0x10000>;
1579                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1580                         clock-names = "dphy_txesc";
1581                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1582                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1583                         reset-names = "dphy_sys", "dphy_txbytehs";
1584                         #phy-cells = <0>;
1585                         status = "disabled";
1586                 };
1587
1588                  mipi_dsi: mipi@295d0000 {
1589                         compatible = "cdns,dsi";
1590                         reg = <0x0 0x295d0000 0x0 0x10000>;
1591                         interrupts = <98>;
1592                         reg-names = "dsi";
1593                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1594                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1595                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1596                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1597                         clock-names = "sys", "apb", "txesc", "dpi";
1598                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1599                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1600                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1601                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1602                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1603                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1604                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1605                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1606                         phys = <&mipi_dphy>;
1607                         phy-names = "dphy";
1608                         status = "disabled";
1609
1610                         port {
1611                                 dsi_out_port: endpoint@0 {
1612                                         remote-endpoint = <&panel_dsi_port>;
1613                                 };
1614                                 dsi_in_port: endpoint@1 {
1615                                         remote-endpoint = <&mipi_out>;
1616                                 };
1617                         };
1618
1619                         mipi_panel: panel@0 {
1620                                 /*compatible = "";*/
1621                                 status = "okay";
1622                         };
1623                 };
1624
1625                 hdmi: hdmi@29590000 {
1626                         compatible = "rockchip,rk3036-inno-hdmi";
1627                         reg = <0x0 0x29590000 0x0 0x4000>;
1628                         interrupts = <99>;
1629                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1630                         /*clocks = <&cru  PCLK_HDMI>;*/
1631                         /*clock-names = "pclk";*/
1632                         /*pinctrl-names = "default";*/
1633                         /*pinctrl-0 = <&hdmi_ctl>;*/
1634                         status = "disabled";
1635                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1636                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1637                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1638                                  <&hdmitx0_pixelclk>;
1639                         clock-names = "sysclk", "mclk","bclk","pclk";
1640                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1641                         reset-names = "hdmi_tx";
1642                 };
1643
1644                 sound: snd-card {
1645                         compatible = "simple-audio-card";
1646                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1647                         #address-cells = <1>;
1648                         #size-cells = <0>;
1649                 };
1650
1651                 co_process: e24@0 {
1652                         compatible = "starfive,e24";
1653                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1654                                 <0x0 0xc0111000 0x0 0x0001f000>;
1655                         reg-names = "ecmd", "espace";
1656                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1657                                  <&clkgen JH7110_E2_CLK_CORE>,
1658                                  <&clkgen JH7110_E2_CLK_DBG>;
1659                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1660                         resets = <&rstgen RSTN_U0_E24_CORE>;
1661                         reset-names = "e24_core";
1662                         starfive,stg-syscon = <&stg_syscon>;
1663                         interrupt-parent = <&plic>;
1664                         firmware-name = "e24_elf";
1665                         irq-mode = <1>;
1666                         mbox-names = "tx", "rx";
1667                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1668                         #address-cells = <1>;
1669                         #size-cells = <1>;
1670                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1671                         status = "disabled";
1672                         dsp@0 {};
1673                 };
1674
1675                 xrp: xrp@0 {
1676                         compatible = "cdns,xrp";
1677                         reg = <0x0  0x10230000 0x0 0x00010000
1678                                 0x0  0x10240000 0x0 0x00010000>;
1679                         memory-region = <&xrp_reserved>;
1680                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1681                         clock-names = "core_clk";
1682                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1683                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1684                         reset-names = "rst_core","rst_axi";
1685                         starfive,stg-syscon = <&stg_syscon>;
1686                         firmware-name = "hifi4_elf";
1687                         #address-cells = <1>;
1688                         #size-cells = <1>;
1689                         ranges = <0x40000000 0x0 0x20000000 0x040000
1690                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1691                         status = "disabled";
1692                         dsp@0 {
1693                         };
1694                 };
1695         };
1696 };