arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "sifive,u74-mc", "riscv";
  26                         reg = <0>;
  27                         d-cache-block-size = <64>;
  28                         d-cache-sets = <64>;
  29                         d-cache-size = <8192>;
  30                         d-tlb-sets = <1>;
  31                         d-tlb-size = <40>;
  32                         device_type = "cpu";
  33                         i-cache-block-size = <64>;
  34                         i-cache-sets = <64>;
  35                         i-cache-size = <16384>;
  36                         i-tlb-sets = <1>;
  37                         i-tlb-size = <40>;
  38                         mmu-type = "riscv,sv39";
  39                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  40                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  41                         next-level-cache = <&cachectrl>;
  42                         riscv,isa = "rv64imac";
  43                         tlb-split;
  44                         status = "disabled";
  45
  46                         cpu0intctrl: interrupt-controller {
  47                                 #interrupt-cells = <1>;
  48                                 compatible = "riscv,cpu-intc";
  49                                 interrupt-controller;
  50                         };
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         compatible = "sifive,u74-mc", "riscv";
  55                         reg = <1>;
  56                         d-cache-block-size = <64>;
  57                         d-cache-sets = <64>;
  58                         d-cache-size = <32768>;
  59                         d-tlb-sets = <1>;
  60                         d-tlb-size = <40>;
  61                         device_type = "cpu";
  62                         i-cache-block-size = <64>;
  63                         i-cache-sets = <64>;
  64                         i-cache-size = <32768>;
  65                         i-tlb-sets = <1>;
  66                         i-tlb-size = <40>;
  67                         mmu-type = "riscv,sv39";
  68                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  69                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  70                         next-level-cache = <&cachectrl>;
  71                         riscv,isa = "rv64imafdc";
  72                         tlb-split;
  73                         status = "okay";
  74
  75                         cpu1intctrl: interrupt-controller {
  76                                 #interrupt-cells = <1>;
  77                                 compatible = "riscv,cpu-intc";
  78                                 interrupt-controller;
  79                         };
  80                 };
  81
  82                 cpu2: cpu@2 {
  83                         compatible = "sifive,u74-mc", "riscv";
  84                         reg = <2>;
  85                         d-cache-block-size = <64>;
  86                         d-cache-sets = <64>;
  87                         d-cache-size = <32768>;
  88                         d-tlb-sets = <1>;
  89                         d-tlb-size = <40>;
  90                         device_type = "cpu";
  91                         i-cache-block-size = <64>;
  92                         i-cache-sets = <64>;
  93                         i-cache-size = <32768>;
  94                         i-tlb-sets = <1>;
  95                         i-tlb-size = <40>;
  96                         mmu-type = "riscv,sv39";
  97                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  98                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  99                         next-level-cache = <&cachectrl>;
 100                         riscv,isa = "rv64imafdc";
 101                         tlb-split;
 102                         status = "okay";
 103
 104                         cpu2intctrl: interrupt-controller {
 105                                 #interrupt-cells = <1>;
 106                                 compatible = "riscv,cpu-intc";
 107                                 interrupt-controller;
 108                         };
 109                 };
 110
 111                 cpu3: cpu@3 {
 112                         compatible = "sifive,u74-mc", "riscv";
 113                         reg = <3>;
 114                         d-cache-block-size = <64>;
 115                         d-cache-sets = <64>;
 116                         d-cache-size = <32768>;
 117                         d-tlb-sets = <1>;
 118                         d-tlb-size = <40>;
 119                         device_type = "cpu";
 120                         i-cache-block-size = <64>;
 121                         i-cache-sets = <64>;
 122                         i-cache-size = <32768>;
 123                         i-tlb-sets = <1>;
 124                         i-tlb-size = <40>;
 125                         mmu-type = "riscv,sv39";
 126                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 127                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 128                         next-level-cache = <&cachectrl>;
 129                         riscv,isa = "rv64imafdc";
 130                         tlb-split;
 131                         status = "okay";
 132
 133                         cpu3intctrl: interrupt-controller {
 134                                 #interrupt-cells = <1>;
 135                                 compatible = "riscv,cpu-intc";
 136                                 interrupt-controller;
 137                         };
 138                 };
 139
 140                 cpu4: cpu@4 {
 141                         compatible = "sifive,u74-mc", "riscv";
 142                         reg = <4>;
 143                         d-cache-block-size = <64>;
 144                         d-cache-sets = <64>;
 145                         d-cache-size = <32768>;
 146                         d-tlb-sets = <1>;
 147                         d-tlb-size = <40>;
 148                         device_type = "cpu";
 149                         i-cache-block-size = <64>;
 150                         i-cache-sets = <64>;
 151                         i-cache-size = <32768>;
 152                         i-tlb-sets = <1>;
 153                         i-tlb-size = <40>;
 154                         mmu-type = "riscv,sv39";
 155                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 156                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 157                         next-level-cache = <&cachectrl>;
 158                         riscv,isa = "rv64imafdc";
 159                         tlb-split;
 160                         status = "okay";
 161
 162                         cpu4intctrl: interrupt-controller {
 163                                 #interrupt-cells = <1>;
 164                                 compatible = "riscv,cpu-intc";
 165                                 interrupt-controller;
 166                         };
 167                 };
 168         };
 169
 170     idle-states {
 171         CPU_RET_0_0: cpu-retentive-0-0 {
 172             compatible = "riscv,idle-state";
 173             riscv,sbi-suspend-param = <0x10000000>;
 174             entry-latency-us = <20>;
 175             exit-latency-us = <40>;
 176             min-residency-us = <80>;
 177         };
 178
 179         CPU_NONRET_0_0: cpu-nonretentive-0-0 {
 180             compatible = "riscv,idle-state";
 181             riscv,sbi-suspend-param = <0x90000000>;
 182             entry-latency-us = <250>;
 183             exit-latency-us = <500>;
 184             min-residency-us = <950>;
 185         };
 186
 187         CLUSTER_RET_0: cluster-retentive-0 {
 188             compatible = "riscv,idle-state";
 189             riscv,sbi-suspend-param = <0x11000000>;
 190             local-timer-stop;
 191             entry-latency-us = <50>;
 192             exit-latency-us = <100>;
 193             min-residency-us = <250>;
 194             wakeup-latency-us = <130>;
 195         };
 196
 197         CLUSTER_NONRET_0: cluster-nonretentive-0 {
 198             compatible = "riscv,idle-state";
 199             riscv,sbi-suspend-param = <0x91000000>;
 200             local-timer-stop;
 201             entry-latency-us = <600>;
 202             exit-latency-us = <1100>;
 203             min-residency-us = <2700>;
 204             wakeup-latency-us = <1500>;
 205         };
 206         };
 207
 208         soc: soc {
 209                 compatible = "simple-bus";
 210                 interrupt-parent = <&plic>;
 211                 #address-cells = <2>;
 212                 #size-cells = <2>;
 213                 #clock-cells = <1>;
 214                 ranges;
 215
 216                 cachectrl: cache-controller@2010000 {
 217                         compatible = "sifive,fu740-c000-ccache", "cache";
 218                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 219                         reg-names = "control", "sideband";
 220                         interrupts = <1 3 4 2>;
 221                         cache-block-size = <64>;
 222                         cache-level = <2>;
 223                         cache-sets = <2048>;
 224                         cache-size = <2097152>;
 225                         cache-unified;
 226                 };
 227
 228                 aon_syscon: aon_syscon@17010000 {
 229                         compatible = "syscon";
 230                         reg = <0x0 0x17010000 0x0 0x1000>;
 231                 };
 232
 233                 stg_syscon: stg_syscon@10240000 {
 234                         compatible = "syscon";
 235                         reg = <0x0 0x10240000 0x0 0x1000>;
 236                 };
 237
 238                 sys_syscon: sys_syscon@13030000 {
 239                         compatible = "syscon";
 240                         reg = <0x0 0x13030000 0x0 0x1000>;
 241                 };
 242
 243                 clint: clint@2000000 {
 244                         compatible = "riscv,clint0";
 245                         reg = <0x0 0x2000000 0x0 0x10000>;
 246                         reg-names = "control";
 247                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 248                                                 &cpu1intctrl 3 &cpu1intctrl 7
 249                                                 &cpu2intctrl 3 &cpu2intctrl 7
 250                                                 &cpu3intctrl 3 &cpu3intctrl 7
 251                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 252                         #interrupt-cells = <1>;
 253                 };
 254
 255                 plic: plic@c000000 {
 256                         compatible = "riscv,plic0";
 257                         reg = <0x0 0xc000000 0x0 0x4000000>;
 258                         reg-names = "control";
 259                         interrupts-extended = <&cpu0intctrl 11
 260                                                 &cpu1intctrl 11 &cpu1intctrl 9
 261                                                 &cpu2intctrl 11 &cpu2intctrl 9
 262                                                 &cpu3intctrl 11 &cpu3intctrl 9
 263                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <1>;
 266                         riscv,max-priority = <7>;
 267                         riscv,ndev = <136>;
 268                 };
 269
 270                 clkgen: clock-controller {
 271                         compatible = "starfive,jh7110-clkgen";
 272                         reg = <0x0 0x13020000 0x0 0x10000>,
 273                                 <0x0 0x10230000 0x0 0x10000>,
 274                                 <0x0 0x17000000 0x0 0x10000>;
 275                         reg-names = "sys", "stg", "aon";
 276                         clocks = <&osc>, <&gmac1_rmii_refin>,
 277                                  <&gmac1_rgmii_rxin>,
 278                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 279                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 280                                  <&tdm_ext>, <&mclk_ext>,
 281                                  <&jtag_tck_inner>, <&bist_apb>,
 282                                  <&clk_rtc>,
 283                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 284                         clock-names = "osc", "gmac1_rmii_refin",
 285                                 "gmac1_rgmii_rxin",
 286                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 287                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 288                                 "tdm_ext", "mclk_ext",
 289                                 "jtag_tck_inner", "bist_apb",
 290                                 "clk_rtc",
 291                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 292                         #clock-cells = <1>;
 293                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 294                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 295                         status = "okay";
 296                 };
 297
 298                 clkvout: clock-controller@295C0000 {
 299                         compatible = "starfive,jh7110-clk-vout";
 300                         reg = <0x0 0x295C0000 0x0 0x10000>;
 301                         reg-names = "vout";
 302                         clocks = <&hdmitx0_pixelclk>,
 303                                  <&mipitx_dphy_rxesc>,
 304                                  <&mipitx_dphy_txbytehs>,
 305                                  <&clkgen JH7110_VOUT_SRC>,
 306                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 307                         clock-names = "hdmitx0_pixelclk",
 308                                       "mipitx_dphy_rxesc",
 309                                       "mipitx_dphy_txbytehs",
 310                                       "vout_src",
 311                                       "vout_top_ahb";
 312                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 313                         reset-names = "vout_src";
 314                         #clock-cells = <1>;
 315                         power-domains = <&pwrc JH7110_PD_VOUT>;
 316                         status = "okay";
 317                 };
 318
 319                 clkisp: clock-controller@19810000 {
 320                         compatible = "starfive,jh7110-clk-isp";
 321                         reg = <0x0 0x19810000 0x0 0x10000>;
 322                         reg-names = "isp";
 323                         #clock-cells = <1>;
 324                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 325                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 326                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 327                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 328                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 329                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 330                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 331                                       "u0_sft7110_noc_bus_clk_isp_axi";
 332                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 333                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 334                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 335                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 336                                       "rst_isp_noc_bus_n";
 337                         power-domains = <&pwrc JH7110_PD_ISP>;
 338                         status = "okay";
 339                 };
 340
 341                 qspi: spi@13010000 {
 342                         compatible = "cdns,qspi-nor";
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         reg = <0x0 0x13010000 0x0 0x10000
 346                                 0x0 0x21000000 0x0 0x400000>;
 347                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 348                         clock-names = "clk_ref";
 349                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 350                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 351                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 352                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 353                         cdns,fifo-depth = <256>;
 354                         cdns,fifo-width = <4>;
 355                         spi-max-frequency = <250000000>;
 356
 357                         nor_flash: nor-flash@0 {
 358                                 compatible = "jedec,spi-nor";
 359                                 reg=<0>;
 360                                 spi-max-frequency = <100000000>;
 361                                 cdns,tshsl-ns = <1>;
 362                                 cdns,tsd2d-ns = <1>;
 363                                 cdns,tchsh-ns = <1>;
 364                                 cdns,tslch-ns = <1>;
 365                         };
 366                 };
 367
 368                 otp: otp@17050000 {
 369                         compatible = "starfive,jh7110-otp";
 370                         reg = <0x0 0x17050000 0x0 0x10000>;
 371                         clock-frequency = <4000000>;
 372                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 373                         clock-names = "apb";
 374                 };
 375
 376                 usbdrd30: usbdrd{
 377                         compatible = "starfive,jh7110-cdns3";
 378                         reg = <0x0 0x10210000 0x0 0x1000>,
 379                               <0x0 0x10200000 0x0 0x1000>;
 380                         clocks = <&clkgen JH7110_USB_125M>,
 381                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 382                                  <&clkgen JH7110_USB0_CLK_LPM>,
 383                                  <&clkgen JH7110_USB0_CLK_STB>,
 384                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 385                                  <&clkgen JH7110_USB0_CLK_AXI>,
 386                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 387                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 388                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 389                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 390                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 391                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 392                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 393                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 394                         reset-names = "pwrup","apb","axi","utmi", "phy";
 395                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 396                         starfive,sys-syscon = <&sys_syscon 0x18>;
 397                         status = "disabled";
 398                         #address-cells = <2>;
 399                         #size-cells = <2>;
 400                         #interrupt-cells = <1>;
 401                         ranges;
 402                         usbdrd_cdns3: usb@10100000 {
 403                                 compatible = "cdns,usb3";
 404                                 reg = <0x0 0x10100000 0x0 0x10000>,
 405                                       <0x0 0x10110000 0x0 0x10000>,
 406                                       <0x0 0x10120000 0x0 0x10000>;
 407                                 reg-names = "otg", "xhci", "dev";
 408                                 interrupts = <100>, <108>, <110>;
 409                                 interrupt-names = "host", "peripheral", "otg";
 410                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 411                                 maximum-speed = "super-speed";
 412                         };
 413                 };
 414
 415                 timer: timer@13050000 {
 416                         compatible = "starfive,timers";
 417                         reg = <0x0 0x13050000 0x0 0x10000>;
 418                         interrupts = <69>, <70>, <71> ,<72>;
 419                         interrupt-names = "timer0", "timer1",
 420                                           "timer2", "timer3";
 421                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 422                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 423                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 424                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 425                                  <&clkgen JH7110_TIMER_CLK_APB>;
 426                         clock-names = "timer0", "timer1",
 427                                       "timer2", "timer3", "apb_clk";
 428                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 429                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 430                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 431                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 432                                  <&rstgen RSTN_U0_TIMER_APB>;
 433                         reset-names = "timer0", "timer1",
 434                                       "timer2", "timer3", "apb_rst";
 435                         clock-frequency = <24000000>;
 436                         status = "okay";
 437                 };
 438
 439                 wdog: wdog@13070000 {
 440                         compatible = "starfive,dskit-wdt";
 441                         reg = <0x0 0x13070000 0x0 0x10000>;
 442                         interrupts = <68>;
 443                         interrupt-names = "wdog";
 444                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 445                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 446                         clock-names = "core_clk", "apb_clk";
 447                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 448                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 449                         reset-names = "rst_apb", "rst_core";
 450                         timeout-sec = <15>;
 451                         status = "okay";
 452                 };
 453
 454                 rtc: rtc@17040000 {
 455                         compatible = "starfive,rtc_hms";
 456                         reg = <0x0 0x17040000 0x0 0x10000>;
 457                         interrupts = <10>, <11>, <12>;
 458                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 459                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 460                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 461                         clock-names = "pclk", "cal_clk";
 462                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 463                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 464                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 465                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 466                         rtc,cal-clock-freq = <1000000>;
 467                         status = "okay";
 468                 };
 469
 470                 pwrc: power-controller@17030000 {
 471                         compatible = "starfive,jh7110-pmu";
 472                         reg = <0x0 0x17030000 0x0 0x10000>;
 473                         interrupts = <111>;
 474                         #power-domain-cells = <1>;
 475                         status = "okay";
 476                 };
 477
 478                 uart0: serial@10000000 {
 479                         compatible = "snps,dw-apb-uart";
 480                         reg = <0x0 0x10000000 0x0 0x10000>;
 481                         reg-io-width = <4>;
 482                         reg-shift = <2>;
 483                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 484                                  <&clkgen JH7110_UART0_CLK_APB>;
 485                         clock-names = "baudclk", "apb_pclk";
 486                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 487                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 488                         interrupts = <32>;
 489                         status = "disabled";
 490                 };
 491
 492                 uart1: serial@10010000 {
 493                         compatible = "snps,dw-apb-uart";
 494                         reg = <0x0 0x10010000 0x0 0x10000>;
 495                         reg-io-width = <4>;
 496                         reg-shift = <2>;
 497                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 498                                  <&clkgen JH7110_UART1_CLK_APB>;
 499                         clock-names = "baudclk", "apb_pclk";
 500                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 501                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 502                         interrupts = <33>;
 503                         status = "disabled";
 504                 };
 505
 506                 uart2: serial@10020000 {
 507                         compatible = "snps,dw-apb-uart";
 508                         reg = <0x0 0x10020000 0x0 0x10000>;
 509                         reg-io-width = <4>;
 510                         reg-shift = <2>;
 511                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 512                                  <&clkgen JH7110_UART2_CLK_APB>;
 513                         clock-names = "baudclk", "apb_pclk";
 514                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 515                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 516                         interrupts = <34>;
 517                         status = "disabled";
 518                 };
 519
 520                 uart3: serial@12000000 {
 521                         compatible = "snps,dw-apb-uart";
 522                         reg = <0x0 0x12000000 0x0 0x10000>;
 523                         reg-io-width = <4>;
 524                         reg-shift = <2>;
 525                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 526                                  <&clkgen JH7110_UART3_CLK_APB>;
 527                         clock-names = "baudclk", "apb_pclk";
 528                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 529                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 530                         interrupts = <45>;
 531                         status = "disabled";
 532                 };
 533
 534                 uart4: serial@12010000 {
 535                         compatible = "snps,dw-apb-uart";
 536                         reg = <0x0 0x12010000 0x0 0x10000>;
 537                         reg-io-width = <4>;
 538                         reg-shift = <2>;
 539                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 540                                  <&clkgen JH7110_UART4_CLK_APB>;
 541                         clock-names = "baudclk", "apb_pclk";
 542                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 543                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 544                         interrupts = <46>;
 545                         status = "disabled";
 546                 };
 547
 548                 uart5: serial@12020000 {
 549                         compatible = "snps,dw-apb-uart";
 550                         reg = <0x0 0x12020000 0x0 0x10000>;
 551                         reg-io-width = <4>;
 552                         reg-shift = <2>;
 553                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 554                                  <&clkgen JH7110_UART5_CLK_APB>;
 555                         clock-names = "baudclk", "apb_pclk";
 556                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 557                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 558                         interrupts = <47>;
 559                         status = "disabled";
 560                 };
 561
 562                 dma: dma-controller@16050000 {
 563                         compatible = "starfive,axi-dma";
 564                         reg = <0x0 0x16050000 0x0 0x10000>;
 565                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 566                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 567                         clock-names = "core-clk", "cfgr-clk";
 568                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 569                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 570                         reset-names = "rst_axi", "rst_ahb";
 571                         interrupts = <73>;
 572                         #dma-cells = <2>;
 573                         dma-channels = <4>;
 574                         snps,dma-masters = <1>;
 575                         snps,data-width = <3>;
 576                         snps,num-hs-if = <56>;
 577                         snps,block-size = <65536 65536 65536 65536>;
 578                         snps,priority = <0 1 2 3>;
 579                         snps,axi-max-burst-len = <16>;
 580                         status = "disabled";
 581                 };
 582
 583                 gpio: gpio@13040000 {
 584                         compatible = "starfive,jh7110-sys-pinctrl";
 585                         reg = <0x0 0x13040000 0x0 0x10000>;
 586                         reg-names = "control";
 587                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 588                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 589                         interrupts = <86>;
 590                         interrupt-controller;
 591                         #gpio-cells = <2>;
 592                         ngpios = <64>;
 593                         status = "okay";
 594                 };
 595
 596                 gpioa: gpio@17020000 {
 597                         compatible = "starfive,jh7110-aon-pinctrl";
 598                         reg = <0x0 0x17020000 0x0 0x10000>;
 599                         reg-names = "control";
 600                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 601                         interrupts = <85>;
 602                         interrupt-controller;
 603                         #gpio-cells = <2>;
 604                         ngpios = <4>;
 605                         status = "okay";
 606                 };
 607
 608                 sfctemp: tmon@120e0000  {
 609                         compatible = "starfive,jh7110-temp";
 610                         reg = <0x0 0x120e0000 0x0 0x10000>;
 611                         interrupts = <81>;
 612                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 613                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 614                         clock-names = "sense", "bus";
 615                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 616                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 617                         reset-names = "sense", "bus";
 618                         #thermal-sensor-cells = <0>;
 619                         status = "disabled";
 620                 };
 621
 622                 thermal-zones {
 623                         cpu-thermal {
 624                                 polling-delay-passive = <250>;
 625                                 polling-delay = <15000>;
 626
 627                                 thermal-sensors = <&sfctemp>;
 628
 629                                 cooling-maps {
 630                                 };
 631
 632                                 trips {
 633                                         cpu_alert0: cpu_alert0 {
 634                                                 /* milliCelsius */
 635                                                 temperature = <75000>;
 636                                                 hysteresis = <2000>;
 637                                                 type = "passive";
 638                                         };
 639
 640                                         cpu_crit: cpu_crit {
 641                                                 /* milliCelsius */
 642                                                 temperature = <90000>;
 643                                                 hysteresis = <2000>;
 644                                                 type = "critical";
 645                                         };
 646                                 };
 647                         };
 648                 };
 649
 650                 trng: trng@1600C000 {
 651                         compatible = "starfive,trng";
 652                         reg = <0x0 0x1600C000 0x0 0x4000>;
 653                         clocks = <&clkgen JH7110_SEC_HCLK>,
 654                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 655                         clock-names = "hclk", "miscahb_clk";
 656                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 657                         interrupts = <30>;
 658                         status = "disabled";
 659                 };
 660
 661                 sec_dma: sec_dma@16008000 {
 662                         /*compatible = "arm,pl080", "arm,primecell";*/
 663                         compatible = "starfive,pl080";
 664                         reg = <0x0 0x16008000 0x0 0x4000>;
 665                         reg-names = "sec_dma";
 666                         interrupts = <29>;
 667                         clocks = <&clkgen JH7110_SEC_HCLK>,
 668                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 669                         clock-names = "sec_hclk","sec_ahb";
 670                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 671                         reset-names = "sec_hre";
 672                         lli-bus-interface-ahb1;
 673                         mem-bus-interface-ahb1;
 674                         memcpy-burst-size = <256>;
 675                         memcpy-bus-width = <32>;
 676                         #dma-cells = <2>;
 677                         status = "disabled";
 678                 };
 679
 680                 crypto: crypto@16000000 {
 681                         compatible = "starfive,jh7110-sec";
 682                         reg = <0x0 0x16000000 0x0 0x4000>,
 683                               <0x0 0x16008000 0x0 0x4000>;
 684                         reg-names = "secreg","secdma";
 685                         interrupts = <28>, <29>;
 686                         interrupt-names = "secirq", "dmairq";
 687                         clocks = <&clkgen JH7110_SEC_HCLK>,
 688                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 689                         clock-names = "sec_hclk","sec_ahb";
 690                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 691                         reset-names = "sec_hre";
 692                         enable-side-channel-mitigation = "true";
 693                         enable-dma = "true";
 694                         dmas = <&sec_dma 1 2>,
 695                                <&sec_dma 0 2>;
 696                         dma-names = "sec_m","sec_p";
 697                         status = "disabled";
 698                 };
 699
 700                 i2c0: i2c@10030000 {
 701                         compatible = "snps,designware-i2c";
 702                         reg = <0x0 0x10030000 0x0 0x10000>;
 703                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 704                                  <&clkgen JH7110_I2C0_CLK_APB>;
 705                         clock-names = "ref", "pclk";
 706                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 707                         interrupts = <35>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                         status = "disabled";
 711                 };
 712
 713                 i2c1: i2c@10040000 {
 714                         compatible = "snps,designware-i2c";
 715                         reg = <0x0 0x10040000 0x0 0x10000>;
 716                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 717                                  <&clkgen JH7110_I2C1_CLK_APB>;
 718                         clock-names = "ref", "pclk";
 719                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 720                         interrupts = <36>;
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                         status = "disabled";
 724                 };
 725
 726                 i2c2: i2c@10050000 {
 727                         compatible = "snps,designware-i2c";
 728                         reg = <0x0 0x10050000 0x0 0x10000>;
 729                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 730                                  <&clkgen JH7110_I2C2_CLK_APB>;
 731                         clock-names = "ref", "pclk";
 732                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 733                         interrupts = <37>;
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                         status = "disabled";
 737                 };
 738
 739                 i2c3: i2c@12030000 {
 740                         compatible = "snps,designware-i2c";
 741                         reg = <0x0 0x12030000 0x0 0x10000>;
 742                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 743                                  <&clkgen JH7110_I2C3_CLK_APB>;
 744                         clock-names = "ref", "pclk";
 745                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 746                         interrupts = <48>;
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749                         status = "disabled";
 750                 };
 751
 752                 i2c4: i2c@12040000 {
 753                         compatible = "snps,designware-i2c";
 754                         reg = <0x0 0x12040000 0x0 0x10000>;
 755                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 756                                  <&clkgen JH7110_I2C4_CLK_APB>;
 757                         clock-names = "ref", "pclk";
 758                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 759                         interrupts = <49>;
 760                         #address-cells = <1>;
 761                         #size-cells = <0>;
 762                         status = "disabled";
 763                 };
 764
 765                 i2c5: i2c@12050000 {
 766                         compatible = "snps,designware-i2c";
 767                         reg = <0x0 0x12050000 0x0 0x10000>;
 768                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 769                                  <&clkgen JH7110_I2C5_CLK_APB>;
 770                         clock-names = "ref", "pclk";
 771                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 772                         interrupts = <50>;
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         status = "disabled";
 776                 };
 777
 778                 i2c6: i2c@12060000 {
 779                         compatible = "snps,designware-i2c";
 780                         reg = <0x0 0x12060000 0x0 0x10000>;
 781                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 782                                  <&clkgen JH7110_I2C6_CLK_APB>;
 783                         clock-names = "ref", "pclk";
 784                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 785                         interrupts = <51>;
 786                         #address-cells = <1>;
 787                         #size-cells = <0>;
 788                         status = "disabled";
 789                 };
 790
 791                 /* unremovable emmc as mmcblk0 */
 792                 sdio0: sdio0@16010000 {
 793                         compatible = "snps,dw-mshc";
 794                         reg = <0x0 0x16010000 0x0 0x10000>;
 795                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 796                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 797                         clock-names = "biu","ciu";
 798                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 799                         reset-names = "reset";
 800                         interrupts = <74>;
 801                         fifo-depth = <32>;
 802                         fifo-watermark-aligned;
 803                         data-addr = <0>;
 804                         status = "disabled";
 805                 };
 806
 807                 sdio1: sdio1@16020000 {
 808                         compatible = "snps,dw-mshc";
 809                         reg = <0x0 0x16020000 0x0 0x10000>;
 810                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 811                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 812                         clock-names = "biu","ciu";
 813                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 814                         reset-names = "reset";
 815                         interrupts = <75>;
 816                         fifo-depth = <32>;
 817                         fifo-watermark-aligned;
 818                         data-addr = <0>;
 819                         status = "disabled";
 820                 };
 821
 822                 vin_sysctl: vin_sysctl@19800000 {
 823                         compatible = "starfive,stf-vin";
 824                         reg = <0x0 0x19800000 0x0 0x10000>,
 825                                 <0x0 0x19810000 0x0 0x10000>,
 826                                 <0x0 0x19820000 0x0 0x10000>,
 827                                 <0x0 0x19840000 0x0 0x10000>,
 828                                 <0x0 0x19870000 0x0 0x30000>,
 829                                 <0x0 0x11840000 0x0 0x10000>,
 830                                 <0x0 0x17030000 0x0 0x10000>,
 831                                 <0x0 0x13020000 0x0 0x10000>;
 832                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 833                                 "isp", "trst", "pmu", "syscrg";
 834                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 835                                  <&clkisp JH7110_U0_VIN_PCLK>,
 836                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 837                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 838                                  <&clkisp JH7110_DVP_INV>,
 839                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 840                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 841                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 842                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 843                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 844                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 845                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 846                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 847                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 848                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 849                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 850                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 851                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 852                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 853                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 854                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 855                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 856                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 857                                 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
 858                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 859                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 860                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 861                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 862                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 863                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 864                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 865                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 866                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 867                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 868                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 869                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 870                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 871                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 872                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 873                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 874                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 875                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 876                                 "rst_isp_top_n", "rst_isp_top_axi";
 877                         starfive,aon-syscon = <&aon_syscon 0x00>;
 878                         power-domains = <&pwrc JH7110_PD_ISP>;
 879                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 880                         interrupts = <92 87 88 89 90>;
 881                         status = "disabled";
 882                 };
 883
 884                 jpu: jpu@11900000 {
 885                         compatible = "starfive,jpu";
 886                         reg = <0x0 0x13090000 0x0 0x300>;
 887                         interrupts = <14>;
 888                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 889                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 890                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 891                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 892                         clock-names = "axi_clk", "core_clk",
 893                                       "apb_clk", "noc_bus";
 894                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 895                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 896                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 897                         reset-names = "rst_axi", "rst_core", "rst_apb";
 898                         power-domains = <&pwrc JH7110_PD_VDEC>;
 899                         status = "disabled";
 900                 };
 901
 902                 vpu_dec: vpu_dec@130A0000 {
 903                         compatible = "starfive,vdec";
 904                         reg = <0x0 0x130A0000 0x0 0x10000>;
 905                         interrupts = <13>;
 906                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 907                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 908                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 909                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 910                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 911                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 912                                       "apb_clk", "noc_bus";
 913                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 914                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 915                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 916                                 <&rstgen RSTN_U0_WAVE511_APB>,
 917                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 918                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 919                                       "rst_apb", "rst_sram";
 920                         starfive,vdec_noc_ctrl;
 921                         power-domains = <&pwrc JH7110_PD_VDEC>;
 922                         status = "disabled";
 923                 };
 924
 925                 vpu_enc: vpu_enc@130B0000 {
 926                         compatible = "starfive,venc";
 927                         reg = <0x0 0x130B0000 0x0 0x10000>;
 928                         interrupts = <15>;
 929                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 930                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 931                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 932                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 933                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 934                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 935                                       "apb_clk", "noc_bus";
 936                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 937                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 938                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 939                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 940                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 941                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 942                                       "rst_apb", "rst_sram";
 943                         starfive,venc_noc_ctrl;
 944                         power-domains = <&pwrc JH7110_PD_VENC>;
 945                         status = "disabled";
 946                 };
 947
 948                 rstgen: reset-controller {
 949                         compatible = "starfive,jh7110-reset";
 950                         reg = <0x0 0x13020000 0x0 0x10000>,
 951                                 <0x0 0x10230000 0x0 0x10000>,
 952                                 <0x0 0x17000000 0x0 0x10000>,
 953                                 <0x0 0x19810000 0x0 0x10000>,
 954                                 <0x0 0x295C0000 0x0 0x10000>;
 955                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 956                         #reset-cells = <1>;
 957                         status = "okay";
 958                 };
 959
 960                 stmmac_axi_setup: stmmac-axi-config {
 961                         snps,wr_osr_lmt = <0xf>;
 962                         snps,rd_osr_lmt = <0xf>;
 963                         snps,blen = <256 128 64 32 0 0 0>;
 964                 };
 965
 966                 gmac0: ethernet@16030000 {
 967                         compatible = "starfive,jh7110-eqos-5.20";
 968                         reg = <0x0 0x16030000 0x0 0x10000>;
 969                         clock-names = "gtx",
 970                                 "tx",
 971                                 "ptp_ref",
 972                                 "stmmaceth",
 973                                 "pclk",
 974                                 "gtxc";
 975                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 976                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 977                                  <&clkgen JH7110_GMAC0_PTP>,
 978                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 979                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 980                                  <&clkgen JH7110_GMAC0_GTXC>;
 981                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 982                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 983                         reset-names = "ahb", "stmmaceth";
 984                         interrupts = <7>, <6>, <5> ;
 985                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 986                         max-frame-size = <9000>;
 987                         phy-mode = "rgmii-id";
 988                         snps,multicast-filter-bins = <64>;
 989                         snps,perfect-filter-entries = <128>;
 990                         rx-fifo-depth = <2048>;
 991                         tx-fifo-depth = <2048>;
 992                         snps,fixed-burst;
 993                         snps,no-pbl-x8;
 994                         snps,force_thresh_dma_mode;
 995                         snps,axi-config = <&stmmac_axi_setup>;
 996                         snps,tso;
 997                         snps,en-tx-lpi-clockgating;
 998                         snps,en-lpi;
 999                         snps,write-requests = <4>;
1000                         snps,read-requests = <4>;
1001                         snps,burst-map = <0x7>;
1002                         snps,txpbl = <16>;
1003                         snps,rxpbl = <16>;
1004                         status = "disabled";
1005                 };
1006
1007                 gmac1: ethernet@16040000 {
1008                         compatible = "starfive,jh7110-eqos-5.20";
1009                         reg = <0x0 0x16040000 0x0 0x10000>;
1010                         clock-names = "gtx",
1011                                 "tx",
1012                                 "ptp_ref",
1013                                 "stmmaceth",
1014                                 "pclk",
1015                                 "gtxc";
1016                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1017                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1018                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1019                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1020                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1021                                  <&clkgen JH7110_GMAC1_GTXC>;
1022                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1023                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1024                         reset-names = "ahb", "stmmaceth";
1025                         interrupts = <78>, <77>, <76> ;
1026                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1027                         max-frame-size = <9000>;
1028                         phy-mode = "rgmii-id";
1029                         snps,multicast-filter-bins = <64>;
1030                         snps,perfect-filter-entries = <128>;
1031                         rx-fifo-depth = <2048>;
1032                         tx-fifo-depth = <2048>;
1033                         snps,fixed-burst;
1034                         snps,no-pbl-x8;
1035                         snps,force_thresh_dma_mode;
1036                         snps,axi-config = <&stmmac_axi_setup>;
1037                         snps,tso;
1038                         snps,en-tx-lpi-clockgating;
1039                         snps,en-lpi;
1040                         snps,write-requests = <4>;
1041                         snps,read-requests = <4>;
1042                         snps,burst-map = <0x7>;
1043                         snps,txpbl = <16>;
1044                         snps,rxpbl = <16>;
1045                         status = "disabled";
1046                 };
1047
1048                 gpu: gpu@18000000 {
1049                         compatible = "img-gpu";
1050                         reg = <0x0 0x18000000 0x0 0x100000>,
1051                                 <0x0 0x130C000 0x0 0x10000>;
1052                         clocks = <&clkgen JH7110_GPU_CLK_APB>,
1053                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1054                                  <&clkgen JH7110_GPU_CORE_CLK>,
1055                                  <&clkgen JH7110_GPU_SYS_CLK>,
1056                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1057                         clock-names = "clk_apb", "clk_rtc", "clk_core",
1058                                         "clk_sys", "clk_axi";
1059                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1060                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1061                         reset-names = "rst_apb", "rst_doma";
1062                         power-domains = <&pwrc JH7110_PD_GPUA>;
1063                         interrupts = <82>;
1064                         current-clock = <8000000>;
1065                         status = "disabled";
1066                 };
1067
1068                 can0: can@130d0000 {
1069                         compatible = "ipms,can";
1070                         reg = <0x0 0x130d0000 0x0 0x1000>;
1071                         interrupts = <112>;
1072                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1073                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1074                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1075                         clock-names = "apb_clk", "core_clk", "timer_clk";
1076                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1077                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1078                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1079                         reset-names = "rst_apb", "rst_core", "rst_timer";
1080                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1081                         syscon,can_or_canfd = <0>;
1082                         status = "disabled";
1083                 };
1084
1085                 can1: can@130e0000 {
1086                         compatible = "ipms,can";
1087                         reg = <0x0 0x130e0000 0x0 0x1000>;
1088                         interrupts = <113>;
1089                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1090                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1091                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1092                         clock-names = "apb_clk", "core_clk", "timer_clk";
1093                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1094                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1095                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1096                         reset-names = "rst_apb", "rst_core", "rst_timer";
1097                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1098                         syscon,can_or_canfd = <0>;
1099                         status = "disabled";
1100                 };
1101
1102                 tdm: tdm@10090000 {
1103                         compatible = "starfive,sf-tdm";
1104                         reg = <0x0 0x10090000 0x0 0x1000>;
1105                         reg-names = "tdm";
1106                         clocks = <&clkgen JH7110_AHB0>,
1107                                  <&clkgen JH7110_TDM_CLK_AHB>,
1108                                  <&clkgen JH7110_APB0>,
1109                                  <&clkgen JH7110_TDM_CLK_APB>,
1110                                  <&clkgen JH7110_TDM_INTERNAL>,
1111                                  <&tdm_ext>,
1112                                  <&clkgen JH7110_TDM_CLK_TDM>,
1113                                  <&clkgen JH7110_MCLK_INNER>;
1114                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1115                                       "clk_apb0", "clk_tdm_apb",
1116                                       "clk_tdm_internal", "clk_tdm_ext",
1117                                       "clk_tdm", "mclk_inner";
1118                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1119                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1120                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1121                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1122                         dmas = <&dma 20 1>, <&dma 21 1>;
1123                         dma-names = "rx","tx";
1124                         #sound-dai-cells = <0>;
1125                         status = "disabled";
1126                 };
1127
1128                 spdif0: spdif0@100a0000 {
1129                         compatible = "starfive,sf-spdif";
1130                         reg = <0x0 0x100a0000 0x0 0x1000>;
1131                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1132                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1133                                  <&clkgen JH7110_AUDIO_ROOT>,
1134                                  <&clkgen JH7110_MCLK_INNER>;
1135                         clock-names = "spdif-apb", "spdif-core",
1136                                       "audroot", "mclk_inner";
1137                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1138                         reset-names = "rst_apb";
1139                         interrupts = <84>;
1140                         interrupt-names = "tx";
1141                         #sound-dai-cells = <0>;
1142                         status = "disabled";
1143                 };
1144
1145                 pwmdac: pwmdac@100b0000 {
1146                         compatible = "starfive,pwmdac";
1147                         reg = <0x0 0x100b0000 0x0 0x1000>;
1148                         clocks = <&clkgen JH7110_APB0>,
1149                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1150                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1151                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1152                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1153                         reset-names = "rst-apb";
1154                         dmas = <&dma 22 1>;
1155                         dma-names = "tx";
1156                         #sound-dai-cells = <0>;
1157                         status = "disabled";
1158                 };
1159
1160                 i2stx: i2stx@100c0000 {
1161                         compatible = "snps,designware-i2stx";
1162                         reg = <0x0 0x100c0000 0x0 0x1000>;
1163                         interrupt-names = "tx";
1164                         #sound-dai-cells = <0>;
1165                         dmas = <&dma 28 1>;
1166                         dma-names = "rx";
1167                         status = "disabled";
1168                 };
1169
1170                 pdm: pdm@100d0000 {
1171                         compatible = "starfive,sf-pdm";
1172                         reg = <0x0 0x100d0000 0x0 0x1000>;
1173                         reg-names = "pdm";
1174                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1175                                  <&clkgen JH7110_APB0>,
1176                                  <&clkgen JH7110_PDM_CLK_APB>,
1177                                  <&clkgen JH7110_MCLK_INNER>,
1178                                  <&clkgen JH7110_MCLK>,
1179                                  <&clkgen JH7110_MCLK_OUT>;
1180                         clock-names = "pdm_mclk", "clk_apb0",
1181                                       "pdm_apb", "mclk_inner",
1182                                       "clk_mclk", "mclk_out";
1183                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1184                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1185                         reset-names = "pdm_dmic", "pdm_apb";
1186                         #sound-dai-cells = <0>;
1187                 };
1188
1189                 i2srx_mst: i2srx_mst@100e0000 {
1190                         compatible = "snps,i2srx-master";
1191                         reg = <0x0 0x100e0000 0x0 0x1000>;
1192                         clocks = <&clkgen JH7110_APB0>,
1193                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1194                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1195                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1196                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1197                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1198                         clock-names = "apb0", "i2srx_apb",
1199                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1200                                       "i2srx_bclk", "i2srx_lrck";
1201                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1202                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1203                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1204                         dmas = <&dma 24 1>;
1205                         dma-names = "rx";
1206                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1207                         #sound-dai-cells = <0>;
1208                         status = "disabled";
1209                 };
1210
1211                 i2srx_3ch: i2srx_3ch@100e0000 {
1212                         compatible = "snps,designware-i2srx";
1213                         reg = <0x0 0x100e0000 0x0 0x1000>;
1214                         clocks = <&clkgen JH7110_APB0>,
1215                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1216                                  <&clkgen JH7110_AUDIO_ROOT>,
1217                                  <&clkgen JH7110_MCLK_INNER>,
1218                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1219                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1220                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1221                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1222                                  <&clkgen JH7110_MCLK>,
1223                                  <&i2srx_bclk_ext>,
1224                                  <&i2srx_lrck_ext>;
1225                         clock-names = "apb0", "3ch-apb",
1226                                         "audioroot", "mclk-inner",
1227                                         "bclk_mst", "3ch-lrck",
1228                                         "rx-bclk", "rx-lrck",
1229                                         "mclk", "bclk-ext",
1230                                         "lrck-ext";
1231                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1232                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1233                         dmas = <&dma 24 1>;
1234                         dma-names = "rx";
1235                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1236                         #sound-dai-cells = <0>;
1237                         status = "disabled";
1238                 };
1239
1240                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1241                         compatible = "snps,designware-i2stx-4ch0";
1242                         reg = <0x0 0x120b0000 0x0 0x1000>;
1243                         clocks = <&clkgen JH7110_MCLK_INNER>,
1244                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1245                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1246                                  <&clkgen JH7110_MCLK>,
1247                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1248                                  <&clkgen JH7110_I2STX0_4CHLRCK>;
1249                         clock-names = "inner", "bclk-mst",
1250                                         "lrck-mst", "mclk",
1251                                         "bclk0", "lrck0";
1252                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1253                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1254                         dmas = <&dma 47 1>;
1255                         dma-names = "tx";
1256                         #sound-dai-cells = <0>;
1257                         status = "disabled";
1258                 };
1259
1260                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1261                         compatible = "snps,designware-i2stx-4ch1";
1262                         reg = <0x0 0x120c0000 0x0 0x1000>;
1263                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1264                                  <&clkgen JH7110_MCLK_INNER>,
1265                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1266                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1267                                  <&clkgen JH7110_MCLK>,
1268                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1269                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1270                                  <&clkgen JH7110_MCLK_OUT>,
1271                                  <&clkgen JH7110_APB0>,
1272                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1273                                  <&mclk_ext>,
1274                                  <&i2stx_bclk_ext>,
1275                                  <&i2stx_lrck_ext>;
1276                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1277                                         "lrck_mst", "mclk", "4chbclk",
1278                                         "4chlrck", "mclk_out",
1279                                         "apb0", "clk_apb",
1280                                         "mclk_ext", "bclk_ext", "lrck_ext";
1281
1282                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1283                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1284                         dmas = <&dma 48 1>;
1285                         dma-names = "tx";
1286                         #sound-dai-cells = <0>;
1287                         status = "disabled";
1288                 };
1289
1290                 ptc: pwm@120d0000 {
1291                         compatible = "starfive,pwm";
1292                         reg = <0x0 0x120d0000 0x0 0x10000>;
1293                         reg-names = "control";
1294                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1295                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1296                         starfive,approx-freq = <2000000>;
1297                         #pwm-cells=<3>;
1298                         starfive,npwm = <8>;
1299                         status = "disabled";
1300                 };
1301
1302                 spdif_transmitter: spdif_transmitter {
1303                         compatible = "linux,spdif-dit";
1304                         #sound-dai-cells = <0>;
1305                         status = "disabled";
1306                 };
1307
1308                 spdif_receiver: spdif_receiver {
1309                         compatible = "linux,spdif-dir";
1310                         #sound-dai-cells = <0>;
1311                         status = "disabled";
1312                 };
1313
1314                 pwmdac_codec: pwmdac-transmitter {
1315                         compatible = "linux,pwmdac-dit";
1316                         #sound-dai-cells = <0>;
1317                         status = "disabled";
1318                 };
1319
1320                 dmic_codec: dmic_codec {
1321                         compatible = "dmic-codec";
1322                         #sound-dai-cells = <0>;
1323                         status = "disabled";
1324                 };
1325
1326                 spi0: spi@10060000 {
1327                         compatible = "arm,pl022", "arm,primecell";
1328                         reg = <0x0 0x10060000 0x0 0x10000>;
1329                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1330                         clock-names = "apb_pclk";
1331                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1332                         reset-names = "rst_apb";
1333                         interrupts = <38>;
1334                         /* shortage of dma channel that not be used */
1335                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1336                         /*dma-names = "rx","tx";*/
1337                         arm,primecell-periphid = <0x00041022>;
1338                         num-cs = <1>;
1339                         #address-cells = <1>;
1340                         #size-cells = <0>;
1341                         status = "disabled";
1342                 };
1343
1344                 spi1: spi@10070000 {
1345                         compatible = "arm,pl022", "arm,primecell";
1346                         reg = <0x0 0x10070000 0x0 0x10000>;
1347                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1348                         clock-names = "apb_pclk";
1349                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1350                         reset-names = "rst_apb";
1351                         interrupts = <39>;
1352                         /* shortage of dma channel that not be used */
1353                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1354                         /*dma-names = "rx","tx";*/
1355                         arm,primecell-periphid = <0x00041022>;
1356                         num-cs = <1>;
1357                         #address-cells = <1>;
1358                         #size-cells = <0>;
1359                         status = "disabled";
1360                 };
1361
1362                 spi2: spi@10080000 {
1363                         compatible = "arm,pl022", "arm,primecell";
1364                         reg = <0x0 0x10080000 0x0 0x10000>;
1365                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1366                         clock-names = "apb_pclk";
1367                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1368                         reset-names = "rst_apb";
1369                         interrupts = <40>;
1370                         /* shortage of dma channel that not be used */
1371                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1372                         /*dma-names = "rx","tx";*/
1373                         arm,primecell-periphid = <0x00041022>;
1374                         num-cs = <1>;
1375                         #address-cells = <1>;
1376                         #size-cells = <0>;
1377                         status = "disabled";
1378                 };
1379
1380                 spi3: spi@12070000 {
1381                         compatible = "arm,pl022", "arm,primecell";
1382                         reg = <0x0 0x12070000 0x0 0x10000>;
1383                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1384                         clock-names = "apb_pclk";
1385                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1386                         reset-names = "rst_apb";
1387                         interrupts = <52>;
1388                         /* shortage of dma channel that not be used */
1389                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1390                         /*dma-names = "rx","tx";*/
1391                         arm,primecell-periphid = <0x00041022>;
1392                         num-cs = <1>;
1393                         #address-cells = <1>;
1394                         #size-cells = <0>;
1395                         status = "disabled";
1396                 };
1397
1398                 spi4: spi@12080000 {
1399                         compatible = "arm,pl022", "arm,primecell";
1400                         reg = <0x0 0x12080000 0x0 0x10000>;
1401                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1402                         clock-names = "apb_pclk";
1403                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1404                         reset-names = "rst_apb";
1405                         interrupts = <53>;
1406                         /* shortage of dma channel that not be used */
1407                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1408                         /*dma-names = "rx","tx";*/
1409                         arm,primecell-periphid = <0x00041022>;
1410                         num-cs = <1>;
1411                         #address-cells = <1>;
1412                         #size-cells = <0>;
1413                         status = "disabled";
1414                 };
1415
1416                 spi5: spi@12090000 {
1417                         compatible = "arm,pl022", "arm,primecell";
1418                         reg = <0x0 0x12090000 0x0 0x10000>;
1419                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1420                         clock-names = "apb_pclk";
1421                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1422                         reset-names = "rst_apb";
1423                         interrupts = <54>;
1424                         /* shortage of dma channel that not be used */
1425                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1426                         /*dma-names = "rx","tx";*/
1427                         arm,primecell-periphid = <0x00041022>;
1428                         num-cs = <1>;
1429                         #address-cells = <1>;
1430                         #size-cells = <0>;
1431                         status = "disabled";
1432                 };
1433
1434                 spi6: spi@120A0000 {
1435                         compatible = "arm,pl022", "arm,primecell";
1436                         reg = <0x0 0x120A0000 0x0 0x10000>;
1437                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1438                         clock-names = "apb_pclk";
1439                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1440                         reset-names = "rst_apb";
1441                         interrupts = <55>;
1442                         /* shortage of dma channel that not be used */
1443                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1444                         /*dma-names = "rx","tx";*/
1445                         arm,primecell-periphid = <0x00041022>;
1446                         num-cs = <1>;
1447                         #address-cells = <1>;
1448                         #size-cells = <0>;
1449                         status = "disabled";
1450                 };
1451
1452                 pcie0: pcie@2B000000 {
1453                         compatible = "plda,pci-xpressrich3-axi";
1454                         #address-cells = <3>;
1455                         #size-cells = <2>;
1456                         #interrupt-cells = <1>;
1457                         reg = <0x0 0x2B000000 0x0 0x1000000
1458                                0x9 0x40000000 0x0 0x10000000>;
1459                         reg-names = "reg", "config";
1460                         device_type = "pci";
1461                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1462                         bus-range = <0x0 0xff>;
1463                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>;
1464                         msi-parent = <&plic>;
1465                         interrupts = <56>;
1466                         interrupt-controller;
1467                         interrupt-names = "msi";
1468                         interrupt-parent = <&plic>;
1469                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1470                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1471                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1472                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1473                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1474                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1475                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1476                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1477                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1478                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1479                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1480                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1481                                       "rst_brg", "rst_core", "rst_apb";
1482                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1483                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1484                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1485                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1486                         clock-names = "noc", "tl", "axi_mst0", "apb";
1487                         status = "disabled";
1488                 };
1489
1490                 pcie1: pcie@2C000000 {
1491                         compatible = "plda,pci-xpressrich3-axi";
1492                         #address-cells = <3>;
1493                         #size-cells = <2>;
1494                         #interrupt-cells = <1>;
1495                         reg = <0x0 0x2C000000 0x0 0x1000000
1496                                0x9 0xc0000000 0x0 0x10000000>;
1497                         reg-names = "reg", "config";
1498                         device_type = "pci";
1499                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1500                         bus-range = <0x0 0xff>;
1501                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>;
1502                         msi-parent = <&plic>;
1503                         interrupts = <57>;
1504                         interrupt-controller;
1505                         interrupt-names = "msi";
1506                         interrupt-parent = <&plic>;
1507                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1508                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1509                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1510                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1511                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1512                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1513                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1514                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1515                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1516                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1517                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1518                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1519                                       "rst_brg", "rst_core", "rst_apb";
1520                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1521                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1522                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1523                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1524                         clock-names = "noc", "tl", "axi_mst0", "apb";
1525                         status = "disabled";
1526                 };
1527
1528                 mailbox_contrl0: mailbox@0 {
1529                         compatible = "starfive,mail_box";
1530                         reg = <0x0 0x13060000 0x0 0x0001000>;
1531                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1532                         clock-names = "clk_apb";
1533                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1534                         reset-names = "mbx_rre";
1535                         interrupts = <26 27>;
1536                         #mbox-cells = <2>;
1537                         status = "disabled";
1538                 };
1539
1540                 mailbox_client0: mailbox_client@0 {
1541                         compatible = "starfive,mailbox-test";
1542                         mbox-names = "rx", "tx";
1543                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1544                         status = "disabled";
1545                 };
1546
1547                 display: display-subsystem {
1548                         compatible = "verisilicon,display-subsystem";
1549                         ports = <&dc_out_dpi0>;
1550                         status = "disabled";
1551                 };
1552
1553                 dssctrl: dssctrl@295B0000 {
1554                         compatible = "verisilicon,dss-ctrl", "syscon";
1555                         reg = <0 0x295B0000 0 0x90>;
1556                 };
1557
1558                 tda988x_pin: tda988x_pin {
1559                         compatible = "starfive,tda998x_rgb_pin";
1560                         status = "disabled";
1561                 };
1562
1563                 hdmi_output: hdmi-output {
1564                         compatible = "verisilicon,hdmi-encoder";
1565                         //verisilicon,dss-syscon = <&dssctrl>;
1566                         //verisilicon,mux-mask = <0x70 0x380>;
1567                         //verisilicon,mux-val = <0x40 0x280>;
1568                         status = "disabled";
1569                 };
1570
1571                 dc8200: dc8200@29400000 {
1572                         compatible = "verisilicon,dc8200";
1573                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1574                         reg = <0x0 0x29400000 0x0 0x100>,
1575                               <0x0 0x29400800 0x0 0x2000>,
1576                               <0x0 0x17030000 0x0 0x1000>;
1577                         interrupts = <95>;
1578                         status = "disabled";
1579                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1580                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1581                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1582                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1583                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1584                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1585                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1586                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1587                                  <&clkgen JH7110_VOUT_SRC>,
1588                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1589                                  <&clkgen JH7110_AHB1>,
1590                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1591                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1592                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1593                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1594                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1595                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1596                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1597                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1598                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1599                                  <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1600                                  <&hdmitx0_pixelclk>,
1601                                  <&clkvout JH7110_DC8200_PIX0>,
1602                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1603                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1604                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1605                                         "noc_disp","noc_isp","noc_stg","vout_src",
1606                                         "top_vout_axi","ahb1","top_vout_ahb",
1607                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1608                                         "axi_clk","core_clk","vout_ahb",
1609                                         "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1610                                         "dc8200_pix0_out","dc8200_pix1_out";
1611                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1612                                  <&rstgen RSTN_U0_DC8200_AXI>,
1613                                  <&rstgen RSTN_U0_DC8200_AHB>,
1614                                  <&rstgen RSTN_U0_DC8200_CORE>,
1615                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1616                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1617                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1618                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1619                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1620                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1621                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1622                                         "rst_noc_disp","rst_noc_stg";
1623                         power-domains = <&pwrc JH7110_PD_VOUT>;
1624                 };
1625
1626                 encoder: display-encoder {
1627                         compatible = "verisilicon,dsi-encoder";
1628                         status = "disabled";
1629                 };
1630
1631                 mipi_dphy: mipi-dphy@295e0000{
1632                         compatible = "starfive,jh7100-mipi-dphy-tx";
1633                         reg = <0x0 0x295e0000 0x0 0x10000>;
1634                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1635                         clock-names = "dphy_txesc";
1636                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1637                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1638                         reset-names = "dphy_sys", "dphy_txbytehs";
1639                         #phy-cells = <0>;
1640                         status = "disabled";
1641                 };
1642
1643                  mipi_dsi: mipi@295d0000 {
1644                         compatible = "cdns,dsi";
1645                         reg = <0x0 0x295d0000 0x0 0x10000>;
1646                         interrupts = <98>;
1647                         reg-names = "dsi";
1648                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1649                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1650                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1651                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1652                         clock-names = "sys", "apb", "txesc", "dpi";
1653                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1654                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1655                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1656                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1657                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1658                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1659                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1660                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1661                         phys = <&mipi_dphy>;
1662                         phy-names = "dphy";
1663                         status = "disabled";
1664
1665                         port {
1666                                 dsi_out_port: endpoint@0 {
1667                                         remote-endpoint = <&panel_dsi_port>;
1668                                 };
1669                                 dsi_in_port: endpoint@1 {
1670                                         remote-endpoint = <&mipi_out>;
1671                                 };
1672                         };
1673
1674                         mipi_panel: panel@0 {
1675                                 /*compatible = "";*/
1676                                 status = "okay";
1677                         };
1678                 };
1679
1680                 hdmi: hdmi@29590000 {
1681                         compatible = "rockchip,rk3036-inno-hdmi";
1682                         reg = <0x0 0x29590000 0x0 0x4000>;
1683                         interrupts = <99>;
1684                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1685                         /*clocks = <&cru  PCLK_HDMI>;*/
1686                         /*clock-names = "pclk";*/
1687                         /*pinctrl-names = "default";*/
1688                         /*pinctrl-0 = <&hdmi_ctl>;*/
1689                         status = "disabled";
1690                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1691                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1692                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1693                                  <&hdmitx0_pixelclk>;
1694                         clock-names = "sysclk", "mclk","bclk","pclk";
1695                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1696                         reset-names = "hdmi_tx";
1697                 };
1698
1699                 sound: snd-card {
1700                         compatible = "simple-audio-card";
1701                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1702                         #address-cells = <1>;
1703                         #size-cells = <0>;
1704                 };
1705
1706                 co_process: e24@0 {
1707                         compatible = "starfive,e24";
1708                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1709                                 <0x0 0xc0111000 0x0 0x0001f000>;
1710                         reg-names = "ecmd", "espace";
1711                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1712                                  <&clkgen JH7110_E2_CLK_CORE>,
1713                                  <&clkgen JH7110_E2_CLK_DBG>;
1714                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1715                         resets = <&rstgen RSTN_U0_E24_CORE>;
1716                         reset-names = "e24_core";
1717                         starfive,stg-syscon = <&stg_syscon>;
1718                         interrupt-parent = <&plic>;
1719                         firmware-name = "e24_elf";
1720                         irq-mode = <1>;
1721                         mbox-names = "tx", "rx";
1722                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1723                         #address-cells = <1>;
1724                         #size-cells = <1>;
1725                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1726                         status = "disabled";
1727                         dsp@0 {};
1728                 };
1729
1730                 xrp: xrp@0 {
1731                         compatible = "cdns,xrp";
1732                         reg = <0x0  0x10230000 0x0 0x00010000
1733                                 0x0  0x10240000 0x0 0x00010000>;
1734                         memory-region = <&xrp_reserved>;
1735                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1736                         clock-names = "core_clk";
1737                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1738                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1739                         reset-names = "rst_core","rst_axi";
1740                         starfive,stg-syscon = <&stg_syscon>;
1741                         firmware-name = "hifi4_elf";
1742                         #address-cells = <1>;
1743                         #size-cells = <1>;
1744                         ranges = <0x40000000 0x0 0x20000000 0x040000
1745                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1746                         status = "disabled";
1747                         dsp@0 {
1748                         };
1749                 };
1750         };
1751 };