1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110-clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
13 #include <dt-bindings/power/jh7110-power.h>
16 compatible = "starfive,jh7110";
20 cluster0_opp: opp-table-0 {
21 compatible = "operating-points-v2";
24 opp-hz = /bits/ 64 <375000000>;
25 opp-microvolt = <880000>;
28 opp-hz = /bits/ 64 <500000000>;
29 opp-microvolt = <880000>;
32 opp-hz = /bits/ 64 <625000000>;
33 opp-microvolt = <880000>;
36 opp-hz = /bits/ 64 <750000000>;
37 opp-microvolt = <880000>;
40 opp-hz = /bits/ 64 <875000000>;
41 opp-microvolt = <880000>;
44 opp-hz = /bits/ 64 <1000000000>;
45 opp-microvolt = <900000>;
48 opp-hz = /bits/ 64 <1250000000>;
49 opp-microvolt = <950000>;
52 opp-hz = /bits/ 64 <1375000000>;
53 opp-microvolt = <1000000>;
56 opp-hz = /bits/ 64 <1500000000>;
57 opp-microvolt = <1100000>;
60 opp-hz = /bits/ 64 <1625000000>;
61 opp-microvolt = <1100000>;
64 opp-hz = /bits/ 64 <1750000000>;
65 opp-microvolt = <1200000>;
74 compatible = "sifive,u74-mc", "riscv";
76 d-cache-block-size = <64>;
78 d-cache-size = <8192>;
82 i-cache-block-size = <64>;
84 i-cache-size = <16384>;
87 mmu-type = "riscv,sv39";
88 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
89 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
90 next-level-cache = <&cachectrl>;
91 riscv,isa = "rv64imac";
95 cpu0intctrl: interrupt-controller {
96 #interrupt-cells = <1>;
97 compatible = "riscv,cpu-intc";
103 compatible = "sifive,u74-mc", "riscv";
105 d-cache-block-size = <64>;
107 d-cache-size = <32768>;
111 i-cache-block-size = <64>;
113 i-cache-size = <32768>;
116 mmu-type = "riscv,sv39";
117 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
118 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
119 next-level-cache = <&cachectrl>;
120 riscv,isa = "rv64imafdc";
123 operating-points-v2 = <&cluster0_opp>;
125 cpu1intctrl: interrupt-controller {
126 #interrupt-cells = <1>;
127 compatible = "riscv,cpu-intc";
128 interrupt-controller;
133 compatible = "sifive,u74-mc", "riscv";
135 d-cache-block-size = <64>;
137 d-cache-size = <32768>;
141 i-cache-block-size = <64>;
143 i-cache-size = <32768>;
146 mmu-type = "riscv,sv39";
147 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
148 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
149 next-level-cache = <&cachectrl>;
150 riscv,isa = "rv64imafdc";
153 operating-points-v2 = <&cluster0_opp>;
155 cpu2intctrl: interrupt-controller {
156 #interrupt-cells = <1>;
157 compatible = "riscv,cpu-intc";
158 interrupt-controller;
163 compatible = "sifive,u74-mc", "riscv";
165 d-cache-block-size = <64>;
167 d-cache-size = <32768>;
171 i-cache-block-size = <64>;
173 i-cache-size = <32768>;
176 mmu-type = "riscv,sv39";
177 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
178 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
179 next-level-cache = <&cachectrl>;
180 riscv,isa = "rv64imafdc";
183 operating-points-v2 = <&cluster0_opp>;
185 cpu3intctrl: interrupt-controller {
186 #interrupt-cells = <1>;
187 compatible = "riscv,cpu-intc";
188 interrupt-controller;
193 compatible = "sifive,u74-mc", "riscv";
195 d-cache-block-size = <64>;
197 d-cache-size = <32768>;
201 i-cache-block-size = <64>;
203 i-cache-size = <32768>;
206 mmu-type = "riscv,sv39";
207 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
208 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
209 next-level-cache = <&cachectrl>;
210 riscv,isa = "rv64imafdc";
213 operating-points-v2 = <&cluster0_opp>;
215 cpu4intctrl: interrupt-controller {
216 #interrupt-cells = <1>;
217 compatible = "riscv,cpu-intc";
218 interrupt-controller;
224 CPU_RET_0_0: cpu-retentive-0-0 {
225 compatible = "starfive,jh7110-idle-state";
226 riscv,sbi-suspend-param = <0x10000000>;
227 entry-latency-us = <20>;
228 exit-latency-us = <40>;
229 min-residency-us = <80>;
232 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
233 compatible = "starfive,jh7110-idle-state";
234 riscv,sbi-suspend-param = <0x90000000>;
235 entry-latency-us = <250>;
236 exit-latency-us = <500>;
237 min-residency-us = <950>;
240 CLUSTER_RET_0: cluster-retentive-0 {
241 compatible = "starfive,jh7110-idle-state";
242 riscv,sbi-suspend-param = <0x11000000>;
244 entry-latency-us = <50>;
245 exit-latency-us = <100>;
246 min-residency-us = <250>;
247 wakeup-latency-us = <130>;
250 CLUSTER_NONRET_0: cluster-nonretentive-0 {
251 compatible = "starfive,jh7110-idle-state";
252 riscv,sbi-suspend-param = <0x91000000>;
254 entry-latency-us = <600>;
255 exit-latency-us = <1100>;
256 min-residency-us = <2700>;
257 wakeup-latency-us = <1500>;
262 compatible = "simple-bus";
263 interrupt-parent = <&plic>;
264 #address-cells = <2>;
269 cachectrl: cache-controller@2010000 {
270 compatible = "sifive,fu740-c000-ccache", "cache";
271 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
272 reg-names = "control", "sideband";
273 interrupts = <1 3 4 2>;
274 cache-block-size = <64>;
277 cache-size = <2097152>;
281 aon_syscon: aon_syscon@17010000 {
282 compatible = "syscon";
283 reg = <0x0 0x17010000 0x0 0x1000>;
286 stg_syscon: stg_syscon@10240000 {
287 compatible = "syscon";
288 reg = <0x0 0x10240000 0x0 0x1000>;
291 sys_syscon: sys_syscon@13030000 {
292 compatible = "syscon";
293 reg = <0x0 0x13030000 0x0 0x1000>;
296 clint: clint@2000000 {
297 compatible = "riscv,clint0";
298 reg = <0x0 0x2000000 0x0 0x10000>;
299 reg-names = "control";
300 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
301 &cpu1intctrl 3 &cpu1intctrl 7
302 &cpu2intctrl 3 &cpu2intctrl 7
303 &cpu3intctrl 3 &cpu3intctrl 7
304 &cpu4intctrl 3 &cpu4intctrl 7>;
305 #interrupt-cells = <1>;
309 compatible = "riscv,plic0";
310 reg = <0x0 0xc000000 0x0 0x4000000>;
311 reg-names = "control";
312 interrupts-extended = <&cpu0intctrl 11
313 &cpu1intctrl 11 &cpu1intctrl 9
314 &cpu2intctrl 11 &cpu2intctrl 9
315 &cpu3intctrl 11 &cpu3intctrl 9
316 &cpu4intctrl 11 &cpu4intctrl 9>;
317 interrupt-controller;
318 #interrupt-cells = <1>;
319 riscv,max-priority = <7>;
323 clkgen: clock-controller {
324 compatible = "starfive,jh7110-clkgen";
325 reg = <0x0 0x13020000 0x0 0x10000>,
326 <0x0 0x10230000 0x0 0x10000>,
327 <0x0 0x17000000 0x0 0x10000>;
328 reg-names = "sys", "stg", "aon";
329 clocks = <&osc>, <&gmac1_rmii_refin>,
331 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
332 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
333 <&tdm_ext>, <&mclk_ext>,
334 <&jtag_tck_inner>, <&bist_apb>,
336 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
337 clock-names = "osc", "gmac1_rmii_refin",
339 "i2stx_bclk_ext", "i2stx_lrck_ext",
340 "i2srx_bclk_ext", "i2srx_lrck_ext",
341 "tdm_ext", "mclk_ext",
342 "jtag_tck_inner", "bist_apb",
344 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
346 starfive,sys-syscon = <&sys_syscon 0x18 0x1c
347 0x20 0x24 0x28 0x2c 0x30 0x34>;
351 clkvout: clock-controller@295C0000 {
352 compatible = "starfive,jh7110-clk-vout";
353 reg = <0x0 0x295C0000 0x0 0x10000>;
355 clocks = <&hdmitx0_pixelclk>,
356 <&mipitx_dphy_rxesc>,
357 <&mipitx_dphy_txbytehs>,
358 <&clkgen JH7110_VOUT_SRC>,
359 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
360 clock-names = "hdmitx0_pixelclk",
362 "mipitx_dphy_txbytehs",
365 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
366 reset-names = "vout_src";
368 power-domains = <&pwrc JH7110_PD_VOUT>;
372 clkisp: clock-controller@19810000 {
373 compatible = "starfive,jh7110-clk-isp";
374 reg = <0x0 0x19810000 0x0 0x10000>;
377 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
378 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
379 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
380 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
381 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
382 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
383 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
384 "u0_sft7110_noc_bus_clk_isp_axi";
385 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
386 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
387 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
388 reset-names = "rst_isp_top_n", "rst_isp_top_axi",
390 power-domains = <&pwrc JH7110_PD_ISP>;
395 compatible = "cdns,qspi-nor";
396 #address-cells = <1>;
398 reg = <0x0 0x13010000 0x0 0x10000
399 0x0 0x21000000 0x0 0x400000>;
400 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
401 clock-names = "clk_ref";
402 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
403 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
404 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
405 resets-names = "rst_apb", "rst_ahb", "rst_ref";
406 cdns,fifo-depth = <256>;
407 cdns,fifo-width = <4>;
408 spi-max-frequency = <250000000>;
410 nor_flash: nor-flash@0 {
411 compatible = "jedec,spi-nor";
413 spi-max-frequency = <100000000>;
422 compatible = "starfive,jh7110-otp";
423 reg = <0x0 0x17050000 0x0 0x10000>;
424 clock-frequency = <4000000>;
425 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
430 compatible = "starfive,jh7110-cdns3";
431 reg = <0x0 0x10210000 0x0 0x1000>,
432 <0x0 0x10200000 0x0 0x1000>;
433 clocks = <&clkgen JH7110_USB_125M>,
434 <&clkgen JH7110_USB0_CLK_APP_125>,
435 <&clkgen JH7110_USB0_CLK_LPM>,
436 <&clkgen JH7110_USB0_CLK_STB>,
437 <&clkgen JH7110_USB0_CLK_USB_APB>,
438 <&clkgen JH7110_USB0_CLK_AXI>,
439 <&clkgen JH7110_USB0_CLK_UTMI_APB>,
440 <&clkgen JH7110_PCIE0_CLK_APB>;
441 clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
442 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
443 <&rstgen RSTN_U0_CDN_USB_APB>,
444 <&rstgen RSTN_U0_CDN_USB_AXI>,
445 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
446 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
447 reset-names = "pwrup","apb","axi","utmi", "phy";
448 starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
449 starfive,sys-syscon = <&sys_syscon 0x18>;
451 #address-cells = <2>;
453 #interrupt-cells = <1>;
455 usbdrd_cdns3: usb@10100000 {
456 compatible = "cdns,usb3";
457 reg = <0x0 0x10100000 0x0 0x10000>,
458 <0x0 0x10110000 0x0 0x10000>,
459 <0x0 0x10120000 0x0 0x10000>;
460 reg-names = "otg", "xhci", "dev";
461 interrupts = <100>, <108>, <110>;
462 interrupt-names = "host", "peripheral", "otg";
463 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
464 maximum-speed = "super-speed";
468 timer: timer@13050000 {
469 compatible = "starfive,jh7110-timers";
470 reg = <0x0 0x13050000 0x0 0x10000>;
471 interrupts = <69>, <70>, <71> ,<72>;
472 interrupt-names = "timer0", "timer1",
474 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
475 <&clkgen JH7110_TIMER_CLK_TIMER1>,
476 <&clkgen JH7110_TIMER_CLK_TIMER2>,
477 <&clkgen JH7110_TIMER_CLK_TIMER3>,
478 <&clkgen JH7110_TIMER_CLK_APB>;
479 clock-names = "timer0", "timer1",
480 "timer2", "timer3", "apb_clk";
481 resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
482 <&rstgen RSTN_U0_TIMER_TIMER1>,
483 <&rstgen RSTN_U0_TIMER_TIMER2>,
484 <&rstgen RSTN_U0_TIMER_TIMER3>,
485 <&rstgen RSTN_U0_TIMER_APB>;
486 reset-names = "timer0", "timer1",
487 "timer2", "timer3", "apb_rst";
488 clock-frequency = <24000000>;
492 wdog: wdog@13070000 {
493 compatible = "starfive,jh7110-wdt";
494 reg = <0x0 0x13070000 0x0 0x10000>;
496 interrupt-names = "wdog";
497 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
498 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
499 clock-names = "core_clk", "apb_clk";
500 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
501 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
502 reset-names = "rst_apb", "rst_core";
508 compatible = "starfive,jh7110-rtc";
509 reg = <0x0 0x17040000 0x0 0x10000>;
510 interrupts = <10>, <11>, <12>;
511 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
512 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
513 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
514 clock-names = "pclk", "cal_clk";
515 resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
516 <&rstgen RSTN_U0_RTC_HMS_APB>,
517 <&rstgen RSTN_U0_RTC_HMS_CAL>;
518 reset-names = "rst_osc", "rst_apb", "rst_cal";
519 rtc,cal-clock-freq = <1000000>;
523 pwrc: power-controller@17030000 {
524 compatible = "starfive,jh7110-pmu";
525 reg = <0x0 0x17030000 0x0 0x10000>;
527 #power-domain-cells = <1>;
531 uart0: serial@10000000 {
532 compatible = "snps,dw-apb-uart";
533 reg = <0x0 0x10000000 0x0 0x10000>;
536 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
537 <&clkgen JH7110_UART0_CLK_APB>;
538 clock-names = "baudclk", "apb_pclk";
539 resets = <&rstgen RSTN_U0_DW_UART_APB>,
540 <&rstgen RSTN_U0_DW_UART_CORE>;
545 uart1: serial@10010000 {
546 compatible = "snps,dw-apb-uart";
547 reg = <0x0 0x10010000 0x0 0x10000>;
550 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
551 <&clkgen JH7110_UART1_CLK_APB>;
552 clock-names = "baudclk", "apb_pclk";
553 resets = <&rstgen RSTN_U1_DW_UART_APB>,
554 <&rstgen RSTN_U1_DW_UART_CORE>;
559 uart2: serial@10020000 {
560 compatible = "snps,dw-apb-uart";
561 reg = <0x0 0x10020000 0x0 0x10000>;
564 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
565 <&clkgen JH7110_UART2_CLK_APB>;
566 clock-names = "baudclk", "apb_pclk";
567 resets = <&rstgen RSTN_U2_DW_UART_APB>,
568 <&rstgen RSTN_U2_DW_UART_CORE>;
573 uart3: serial@12000000 {
574 compatible = "snps,dw-apb-uart";
575 reg = <0x0 0x12000000 0x0 0x10000>;
578 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
579 <&clkgen JH7110_UART3_CLK_APB>;
580 clock-names = "baudclk", "apb_pclk";
581 resets = <&rstgen RSTN_U3_DW_UART_APB>,
582 <&rstgen RSTN_U3_DW_UART_CORE>;
587 uart4: serial@12010000 {
588 compatible = "snps,dw-apb-uart";
589 reg = <0x0 0x12010000 0x0 0x10000>;
592 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
593 <&clkgen JH7110_UART4_CLK_APB>;
594 clock-names = "baudclk", "apb_pclk";
595 resets = <&rstgen RSTN_U4_DW_UART_APB>,
596 <&rstgen RSTN_U4_DW_UART_CORE>;
601 uart5: serial@12020000 {
602 compatible = "snps,dw-apb-uart";
603 reg = <0x0 0x12020000 0x0 0x10000>;
606 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
607 <&clkgen JH7110_UART5_CLK_APB>;
608 clock-names = "baudclk", "apb_pclk";
609 resets = <&rstgen RSTN_U5_DW_UART_APB>,
610 <&rstgen RSTN_U5_DW_UART_CORE>;
615 dma: dma-controller@16050000 {
616 compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
617 reg = <0x0 0x16050000 0x0 0x10000>;
618 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
619 <&clkgen JH7110_DMA1P_CLK_AHB>;
620 clock-names = "core-clk", "cfgr-clk";
621 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
622 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
623 reset-names = "rst_axi", "rst_ahb";
627 snps,dma-masters = <1>;
628 snps,data-width = <3>;
629 snps,num-hs-if = <56>;
630 snps,block-size = <65536 65536 65536 65536>;
631 snps,priority = <0 1 2 3>;
632 snps,axi-max-burst-len = <16>;
636 gpio: gpio@13040000 {
637 compatible = "starfive,jh7110-sys-pinctrl";
638 reg = <0x0 0x13040000 0x0 0x10000>;
639 reg-names = "control";
640 clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
641 resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
643 interrupt-controller;
649 gpioa: gpio@17020000 {
650 compatible = "starfive,jh7110-aon-pinctrl";
651 reg = <0x0 0x17020000 0x0 0x10000>;
652 reg-names = "control";
653 resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
655 interrupt-controller;
661 sfctemp: tmon@120e0000 {
662 compatible = "starfive,jh7110-temp";
663 reg = <0x0 0x120e0000 0x0 0x10000>;
665 clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
666 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
667 clock-names = "sense", "bus";
668 resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
669 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
670 reset-names = "sense", "bus";
671 #thermal-sensor-cells = <0>;
677 polling-delay-passive = <250>;
678 polling-delay = <15000>;
680 thermal-sensors = <&sfctemp>;
686 cpu_alert0: cpu_alert0 {
688 temperature = <75000>;
695 temperature = <90000>;
703 trng: trng@1600C000 {
704 compatible = "starfive,jh7110-trng";
705 reg = <0x0 0x1600C000 0x0 0x4000>;
706 clocks = <&clkgen JH7110_SEC_HCLK>,
707 <&clkgen JH7110_SEC_MISCAHB_CLK>;
708 clock-names = "hclk", "miscahb_clk";
709 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
714 sec_dma: sec_dma@16008000 {
715 compatible = "arm,pl080", "arm,primecell";
716 arm,primecell-periphid = <0x00041080>;
717 reg = <0x0 0x16008000 0x0 0x4000>;
718 reg-names = "sec_dma";
720 clocks = <&clkgen JH7110_SEC_HCLK>,
721 <&clkgen JH7110_SEC_MISCAHB_CLK>;
722 clock-names = "sec_hclk","apb_pclk";
723 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
724 reset-names = "sec_hre";
725 lli-bus-interface-ahb1;
726 mem-bus-interface-ahb1;
727 memcpy-burst-size = <256>;
728 memcpy-bus-width = <32>;
733 crypto: crypto@16000000 {
734 compatible = "starfive,jh7110-sec";
735 reg = <0x0 0x16000000 0x0 0x4000>,
736 <0x0 0x16008000 0x0 0x4000>;
737 reg-names = "secreg","secdma";
738 interrupts = <28>, <29>;
739 interrupt-names = "secirq", "dmairq";
740 clocks = <&clkgen JH7110_SEC_HCLK>,
741 <&clkgen JH7110_SEC_MISCAHB_CLK>;
742 clock-names = "sec_hclk","sec_ahb";
743 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
744 reset-names = "sec_hre";
745 enable-side-channel-mitigation = "true";
747 dmas = <&sec_dma 1 2>,
749 dma-names = "sec_m","sec_p";
754 compatible = "snps,designware-i2c";
755 reg = <0x0 0x10030000 0x0 0x10000>;
756 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
757 <&clkgen JH7110_I2C0_CLK_APB>;
758 clock-names = "ref", "pclk";
759 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
761 #address-cells = <1>;
767 compatible = "snps,designware-i2c";
768 reg = <0x0 0x10040000 0x0 0x10000>;
769 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
770 <&clkgen JH7110_I2C1_CLK_APB>;
771 clock-names = "ref", "pclk";
772 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
774 #address-cells = <1>;
780 compatible = "snps,designware-i2c";
781 reg = <0x0 0x10050000 0x0 0x10000>;
782 clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
783 <&clkgen JH7110_I2C2_CLK_APB>;
784 clock-names = "ref", "pclk";
785 resets = <&rstgen RSTN_U2_DW_I2C_APB>;
787 #address-cells = <1>;
793 compatible = "snps,designware-i2c";
794 reg = <0x0 0x12030000 0x0 0x10000>;
795 clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
796 <&clkgen JH7110_I2C3_CLK_APB>;
797 clock-names = "ref", "pclk";
798 resets = <&rstgen RSTN_U3_DW_I2C_APB>;
800 #address-cells = <1>;
806 compatible = "snps,designware-i2c";
807 reg = <0x0 0x12040000 0x0 0x10000>;
808 clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
809 <&clkgen JH7110_I2C4_CLK_APB>;
810 clock-names = "ref", "pclk";
811 resets = <&rstgen RSTN_U4_DW_I2C_APB>;
813 #address-cells = <1>;
819 compatible = "snps,designware-i2c";
820 reg = <0x0 0x12050000 0x0 0x10000>;
821 clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
822 <&clkgen JH7110_I2C5_CLK_APB>;
823 clock-names = "ref", "pclk";
824 resets = <&rstgen RSTN_U5_DW_I2C_APB>;
826 #address-cells = <1>;
832 compatible = "snps,designware-i2c";
833 reg = <0x0 0x12060000 0x0 0x10000>;
834 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
835 <&clkgen JH7110_I2C6_CLK_APB>;
836 clock-names = "ref", "pclk";
837 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
839 #address-cells = <1>;
844 /* unremovable emmc as mmcblk0 */
845 sdio0: sdio0@16010000 {
846 compatible = "starfive,jh7110-sdio";
847 reg = <0x0 0x16010000 0x0 0x10000>;
848 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
849 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
850 clock-names = "biu","ciu";
851 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
852 reset-names = "reset";
855 fifo-watermark-aligned;
857 starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
861 sdio1: sdio1@16020000 {
862 compatible = "starfive,jh7110-sdio";
863 reg = <0x0 0x16020000 0x0 0x10000>;
864 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
865 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
866 clock-names = "biu","ciu";
867 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
868 reset-names = "reset";
871 fifo-watermark-aligned;
876 vin_sysctl: vin_sysctl@19800000 {
877 compatible = "starfive,jh7110-vin";
878 reg = <0x0 0x19800000 0x0 0x10000>,
879 <0x0 0x19810000 0x0 0x10000>,
880 <0x0 0x19820000 0x0 0x10000>,
881 <0x0 0x19840000 0x0 0x10000>,
882 <0x0 0x19870000 0x0 0x30000>,
883 <0x0 0x11840000 0x0 0x10000>,
884 <0x0 0x17030000 0x0 0x10000>,
885 <0x0 0x13020000 0x0 0x10000>;
886 reg-names = "csi2rx", "vclk", "vrst", "sctrl",
887 "isp", "trst", "pmu", "syscrg";
888 clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
889 <&clkisp JH7110_U0_VIN_PCLK>,
890 <&clkisp JH7110_U0_VIN_SYS_CLK>,
891 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
892 <&clkisp JH7110_DVP_INV>,
893 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
894 <&clkisp JH7110_MIPI_RX0_PXL>,
895 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
896 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
897 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
898 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
899 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
900 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
901 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
902 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
903 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
904 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
905 clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
906 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
907 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
908 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
909 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
910 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
911 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
912 resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
913 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
914 <&rstgen RSTN_U0_VIN_N_PCLK>,
915 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
916 <&rstgen RSTN_U0_VIN_P_AXIRD>,
917 <&rstgen RSTN_U0_VIN_P_AXIWR>,
918 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
919 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
920 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
921 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
922 <&rstgen RSTN_U0_M31DPHY_HW>,
923 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
924 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
925 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
926 reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
927 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
928 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
929 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
930 "rst_isp_top_n", "rst_isp_top_axi";
931 starfive,aon-syscon = <&aon_syscon 0x00>;
932 power-domains = <&pwrc JH7110_PD_ISP>;
933 /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
934 interrupts = <92 87 88 89 90>;
939 compatible = "starfive,jpu";
940 reg = <0x0 0x13090000 0x0 0x300>;
942 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
943 <&clkgen JH7110_CODAJ12_CLK_CORE>,
944 <&clkgen JH7110_CODAJ12_CLK_APB>,
945 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
946 clock-names = "axi_clk", "core_clk",
947 "apb_clk", "noc_bus";
948 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
949 <&rstgen RSTN_U0_CODAJ12_CORE>,
950 <&rstgen RSTN_U0_CODAJ12_APB>;
951 reset-names = "rst_axi", "rst_core", "rst_apb";
952 power-domains = <&pwrc JH7110_PD_VDEC>;
956 vpu_dec: vpu_dec@130A0000 {
957 compatible = "starfive,vdec";
958 reg = <0x0 0x130A0000 0x0 0x10000>;
960 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
961 <&clkgen JH7110_WAVE511_CLK_BPU>,
962 <&clkgen JH7110_WAVE511_CLK_VCE>,
963 <&clkgen JH7110_WAVE511_CLK_APB>,
964 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
965 clock-names = "axi_clk", "bpu_clk", "vce_clk",
966 "apb_clk", "noc_bus";
967 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
968 <&rstgen RSTN_U0_WAVE511_BPU>,
969 <&rstgen RSTN_U0_WAVE511_VCE>,
970 <&rstgen RSTN_U0_WAVE511_APB>,
971 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
972 reset-names = "rst_axi", "rst_bpu", "rst_vce",
973 "rst_apb", "rst_sram";
974 starfive,vdec_noc_ctrl;
975 power-domains = <&pwrc JH7110_PD_VDEC>;
979 vpu_enc: vpu_enc@130B0000 {
980 compatible = "starfive,venc";
981 reg = <0x0 0x130B0000 0x0 0x10000>;
983 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
984 <&clkgen JH7110_WAVE420L_CLK_BPU>,
985 <&clkgen JH7110_WAVE420L_CLK_VCE>,
986 <&clkgen JH7110_WAVE420L_CLK_APB>,
987 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
988 clock-names = "axi_clk", "bpu_clk", "vce_clk",
989 "apb_clk", "noc_bus";
990 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
991 <&rstgen RSTN_U0_WAVE420L_BPU>,
992 <&rstgen RSTN_U0_WAVE420L_VCE>,
993 <&rstgen RSTN_U0_WAVE420L_APB>,
994 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
995 reset-names = "rst_axi", "rst_bpu", "rst_vce",
996 "rst_apb", "rst_sram";
997 starfive,venc_noc_ctrl;
998 power-domains = <&pwrc JH7110_PD_VENC>;
1002 rstgen: reset-controller {
1003 compatible = "starfive,jh7110-reset";
1004 reg = <0x0 0x13020000 0x0 0x10000>,
1005 <0x0 0x10230000 0x0 0x10000>,
1006 <0x0 0x17000000 0x0 0x10000>,
1007 <0x0 0x19810000 0x0 0x10000>,
1008 <0x0 0x295C0000 0x0 0x10000>;
1009 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
1014 stmmac_axi_setup: stmmac-axi-config {
1015 snps,wr_osr_lmt = <0xf>;
1016 snps,rd_osr_lmt = <0xf>;
1017 snps,blen = <256 128 64 32 0 0 0>;
1020 gmac0: ethernet@16030000 {
1021 compatible = "starfive,dwmac","snps,dwmac-5.10a";
1022 reg = <0x0 0x16030000 0x0 0x10000>;
1023 clock-names = "gtx",
1029 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
1030 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
1031 <&clkgen JH7110_GMAC0_PTP>,
1032 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
1033 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
1034 <&clkgen JH7110_GMAC0_GTXC>;
1035 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
1036 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
1037 reset-names = "ahb", "stmmaceth";
1038 interrupts = <7>, <6>, <5> ;
1039 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1040 max-frame-size = <9000>;
1041 phy-mode = "rgmii-id";
1042 snps,multicast-filter-bins = <64>;
1043 snps,perfect-filter-entries = <128>;
1044 rx-fifo-depth = <2048>;
1045 tx-fifo-depth = <2048>;
1048 snps,force_thresh_dma_mode;
1049 snps,axi-config = <&stmmac_axi_setup>;
1051 snps,en-tx-lpi-clockgating;
1053 snps,write-requests = <4>;
1054 snps,read-requests = <4>;
1055 snps,burst-map = <0x7>;
1058 status = "disabled";
1061 gmac1: ethernet@16040000 {
1062 compatible = "starfive,dwmac","snps,dwmac-5.10a";
1063 reg = <0x0 0x16040000 0x0 0x10000>;
1064 clock-names = "gtx",
1070 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1071 <&clkgen JH7110_GMAC5_CLK_TX>,
1072 <&clkgen JH7110_GMAC5_CLK_PTP>,
1073 <&clkgen JH7110_GMAC5_CLK_AHB>,
1074 <&clkgen JH7110_GMAC5_CLK_AXI>,
1075 <&clkgen JH7110_GMAC1_GTXC>;
1076 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1077 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1078 reset-names = "ahb", "stmmaceth";
1079 interrupts = <78>, <77>, <76> ;
1080 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1081 max-frame-size = <9000>;
1082 phy-mode = "rgmii-id";
1083 snps,multicast-filter-bins = <64>;
1084 snps,perfect-filter-entries = <128>;
1085 rx-fifo-depth = <2048>;
1086 tx-fifo-depth = <2048>;
1089 snps,force_thresh_dma_mode;
1090 snps,axi-config = <&stmmac_axi_setup>;
1092 snps,en-tx-lpi-clockgating;
1094 snps,write-requests = <4>;
1095 snps,read-requests = <4>;
1096 snps,burst-map = <0x7>;
1099 status = "disabled";
1103 compatible = "img-gpu";
1104 reg = <0x0 0x18000000 0x0 0x100000>,
1105 <0x0 0x130C000 0x0 0x10000>;
1106 clocks = <&clkgen JH7110_GPU_CORE>,
1107 <&clkgen JH7110_GPU_CLK_APB>,
1108 <&clkgen JH7110_GPU_RTC_TOGGLE>,
1109 <&clkgen JH7110_GPU_CORE_CLK>,
1110 <&clkgen JH7110_GPU_SYS_CLK>,
1111 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1112 clock-names = "clk_bv", "clk_apb", "clk_rtc",
1113 "clk_core", "clk_sys", "clk_axi";
1114 resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1115 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1116 reset-names = "rst_apb", "rst_doma";
1117 power-domains = <&pwrc JH7110_PD_GPUA>;
1119 current-clock = <8000000>;
1120 status = "disabled";
1123 can0: can@130d0000 {
1124 compatible = "starfive,jh7110-can", "ipms,can";
1125 reg = <0x0 0x130d0000 0x0 0x1000>;
1127 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1128 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1129 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1130 clock-names = "apb_clk", "core_clk", "timer_clk";
1131 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1132 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1133 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1134 reset-names = "rst_apb", "rst_core", "rst_timer";
1135 frequency = <40000000>;
1136 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1137 syscon,can_or_canfd = <0>;
1138 status = "disabled";
1141 can1: can@130e0000 {
1142 compatible = "starfive,jh7110-can", "ipms,can";
1143 reg = <0x0 0x130e0000 0x0 0x1000>;
1145 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1146 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1147 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1148 clock-names = "apb_clk", "core_clk", "timer_clk";
1149 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1150 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1151 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1152 reset-names = "rst_apb", "rst_core", "rst_timer";
1153 frequency = <40000000>;
1154 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1155 syscon,can_or_canfd = <1>;
1156 status = "disabled";
1160 compatible = "starfive,jh7110-tdm";
1161 reg = <0x0 0x10090000 0x0 0x1000>;
1163 clocks = <&clkgen JH7110_AHB0>,
1164 <&clkgen JH7110_TDM_CLK_AHB>,
1165 <&clkgen JH7110_APB0>,
1166 <&clkgen JH7110_TDM_CLK_APB>,
1167 <&clkgen JH7110_TDM_INTERNAL>,
1169 <&clkgen JH7110_TDM_CLK_TDM>,
1170 <&clkgen JH7110_MCLK_INNER>;
1171 clock-names = "clk_ahb0", "clk_tdm_ahb",
1172 "clk_apb0", "clk_tdm_apb",
1173 "clk_tdm_internal", "clk_tdm_ext",
1174 "clk_tdm", "mclk_inner";
1175 resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1176 <&rstgen RSTN_U0_TDM16SLOT_APB>,
1177 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1178 reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1179 dmas = <&dma 20 1>, <&dma 21 1>;
1180 dma-names = "rx","tx";
1181 #sound-dai-cells = <0>;
1182 status = "disabled";
1185 spdif0: spdif0@100a0000 {
1186 compatible = "starfive,jh7110-spdif";
1187 reg = <0x0 0x100a0000 0x0 0x1000>;
1188 clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1189 <&clkgen JH7110_SPDIF_CLK_CORE>,
1190 <&clkgen JH7110_AUDIO_ROOT>,
1191 <&clkgen JH7110_MCLK_INNER>,
1192 <&mclk_ext>, <&clkgen JH7110_MCLK>;
1193 clock-names = "spdif-apb", "spdif-core",
1194 "audroot", "mclk_inner",
1196 resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1197 reset-names = "rst_apb";
1199 interrupt-names = "tx";
1200 #sound-dai-cells = <0>;
1201 status = "disabled";
1204 pwmdac: pwmdac@100b0000 {
1205 compatible = "starfive,jh7110-pwmdac";
1206 reg = <0x0 0x100b0000 0x0 0x1000>;
1207 clocks = <&clkgen JH7110_APB0>,
1208 <&clkgen JH7110_PWMDAC_CLK_APB>,
1209 <&clkgen JH7110_PWMDAC_CLK_CORE>;
1210 clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1211 resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1212 reset-names = "rst-apb";
1215 #sound-dai-cells = <0>;
1216 status = "disabled";
1219 i2stx: i2stx@100c0000 {
1220 compatible = "snps,designware-i2stx";
1221 reg = <0x0 0x100c0000 0x0 0x1000>;
1222 interrupt-names = "tx";
1223 #sound-dai-cells = <0>;
1226 status = "disabled";
1230 compatible = "starfive,jh7110-pdm";
1231 reg = <0x0 0x100d0000 0x0 0x1000>;
1233 clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1234 <&clkgen JH7110_APB0>,
1235 <&clkgen JH7110_PDM_CLK_APB>,
1236 <&clkgen JH7110_MCLK>,
1238 clock-names = "pdm_mclk", "clk_apb0",
1239 "pdm_apb", "clk_mclk",
1241 resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1242 <&rstgen RSTN_U0_PDM_4MIC_APB>;
1243 reset-names = "pdm_dmic", "pdm_apb";
1244 #sound-dai-cells = <0>;
1247 i2srx_mst: i2srx_mst@100e0000 {
1248 compatible = "starfive,jh7110-i2srx-master";
1249 reg = <0x0 0x100e0000 0x0 0x1000>;
1250 clocks = <&clkgen JH7110_APB0>,
1251 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1252 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1253 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1254 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1255 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1256 clock-names = "apb0", "i2srx_apb",
1257 "i2srx_bclk_mst", "i2srx_lrck_mst",
1258 "i2srx_bclk", "i2srx_lrck";
1259 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1260 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1261 reset-names = "rst_apb_rx", "rst_bclk_rx";
1264 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1265 #sound-dai-cells = <0>;
1266 status = "disabled";
1269 i2srx_3ch: i2srx_3ch@100e0000 {
1270 compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1271 reg = <0x0 0x100e0000 0x0 0x1000>;
1272 clocks = <&clkgen JH7110_APB0>,
1273 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1274 <&clkgen JH7110_AUDIO_ROOT>,
1275 <&clkgen JH7110_MCLK_INNER>,
1276 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1277 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1278 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1279 <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1280 <&clkgen JH7110_MCLK>,
1283 clock-names = "apb0", "3ch-apb",
1284 "audioroot", "mclk-inner",
1285 "bclk_mst", "3ch-lrck",
1286 "rx-bclk", "rx-lrck",
1289 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1290 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1293 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1294 #sound-dai-cells = <0>;
1295 status = "disabled";
1298 i2stx_4ch0: i2stx_4ch0@120b0000 {
1299 compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1300 reg = <0x0 0x120b0000 0x0 0x1000>;
1301 clocks = <&clkgen JH7110_MCLK_INNER>,
1302 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1303 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1304 <&clkgen JH7110_MCLK>,
1305 <&clkgen JH7110_I2STX0_4CHBCLK>,
1306 <&clkgen JH7110_I2STX0_4CHLRCK>,
1307 <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1309 clock-names = "inner", "bclk-mst",
1312 "i2s_apb", "mclk_ext";
1313 resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1314 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1315 reset-names = "rst_apb", "rst_bclk";
1318 #sound-dai-cells = <0>;
1319 status = "disabled";
1322 i2stx_4ch1: i2stx_4ch1@120c0000 {
1323 compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1324 reg = <0x0 0x120c0000 0x0 0x1000>;
1325 clocks = <&clkgen JH7110_AUDIO_ROOT>,
1326 <&clkgen JH7110_MCLK_INNER>,
1327 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1328 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1329 <&clkgen JH7110_MCLK>,
1330 <&clkgen JH7110_I2STX1_4CHBCLK>,
1331 <&clkgen JH7110_I2STX1_4CHLRCK>,
1332 <&clkgen JH7110_MCLK_OUT>,
1333 <&clkgen JH7110_APB0>,
1334 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1338 clock-names = "audroot", "mclk_inner", "bclk_mst",
1339 "lrck_mst", "mclk", "4chbclk",
1340 "4chlrck", "mclk_out",
1342 "mclk_ext", "bclk_ext", "lrck_ext";
1343 resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1344 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1347 #sound-dai-cells = <0>;
1348 status = "disabled";
1352 compatible = "starfive,jh7110-pwm";
1353 reg = <0x0 0x120d0000 0x0 0x10000>;
1354 reg-names = "control";
1355 clocks = <&clkgen JH7110_PWM_CLK_APB>;
1356 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1357 starfive,approx-freq = <2000000>;
1359 starfive,npwm = <8>;
1360 status = "disabled";
1363 spdif_transmitter: spdif_transmitter {
1364 compatible = "linux,spdif-dit";
1365 #sound-dai-cells = <0>;
1366 status = "disabled";
1369 pwmdac_codec: pwmdac-transmitter {
1370 compatible = "starfive,jh7110-pwmdac-dit";
1371 #sound-dai-cells = <0>;
1372 status = "disabled";
1375 dmic_codec: dmic_codec {
1376 compatible = "dmic-codec";
1377 #sound-dai-cells = <0>;
1378 status = "disabled";
1381 spi0: spi@10060000 {
1382 compatible = "arm,pl022", "arm,primecell";
1383 reg = <0x0 0x10060000 0x0 0x10000>;
1384 clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1385 clock-names = "apb_pclk";
1386 resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1387 reset-names = "rst_apb";
1389 /* shortage of dma channel that not be used */
1390 /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1391 /*dma-names = "rx","tx";*/
1392 arm,primecell-periphid = <0x00041022>;
1394 #address-cells = <1>;
1396 status = "disabled";
1399 spi1: spi@10070000 {
1400 compatible = "arm,pl022", "arm,primecell";
1401 reg = <0x0 0x10070000 0x0 0x10000>;
1402 clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1403 clock-names = "apb_pclk";
1404 resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1405 reset-names = "rst_apb";
1407 /* shortage of dma channel that not be used */
1408 /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1409 /*dma-names = "rx","tx";*/
1410 arm,primecell-periphid = <0x00041022>;
1412 #address-cells = <1>;
1414 status = "disabled";
1417 spi2: spi@10080000 {
1418 compatible = "arm,pl022", "arm,primecell";
1419 reg = <0x0 0x10080000 0x0 0x10000>;
1420 clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1421 clock-names = "apb_pclk";
1422 resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1423 reset-names = "rst_apb";
1425 /* shortage of dma channel that not be used */
1426 /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1427 /*dma-names = "rx","tx";*/
1428 arm,primecell-periphid = <0x00041022>;
1430 #address-cells = <1>;
1432 status = "disabled";
1435 spi3: spi@12070000 {
1436 compatible = "arm,pl022", "arm,primecell";
1437 reg = <0x0 0x12070000 0x0 0x10000>;
1438 clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1439 clock-names = "apb_pclk";
1440 resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1441 reset-names = "rst_apb";
1443 /* shortage of dma channel that not be used */
1444 /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1445 /*dma-names = "rx","tx";*/
1446 arm,primecell-periphid = <0x00041022>;
1448 #address-cells = <1>;
1450 status = "disabled";
1453 spi4: spi@12080000 {
1454 compatible = "arm,pl022", "arm,primecell";
1455 reg = <0x0 0x12080000 0x0 0x10000>;
1456 clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1457 clock-names = "apb_pclk";
1458 resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1459 reset-names = "rst_apb";
1461 /* shortage of dma channel that not be used */
1462 /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1463 /*dma-names = "rx","tx";*/
1464 arm,primecell-periphid = <0x00041022>;
1466 #address-cells = <1>;
1468 status = "disabled";
1471 spi5: spi@12090000 {
1472 compatible = "arm,pl022", "arm,primecell";
1473 reg = <0x0 0x12090000 0x0 0x10000>;
1474 clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1475 clock-names = "apb_pclk";
1476 resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1477 reset-names = "rst_apb";
1479 /* shortage of dma channel that not be used */
1480 /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1481 /*dma-names = "rx","tx";*/
1482 arm,primecell-periphid = <0x00041022>;
1484 #address-cells = <1>;
1486 status = "disabled";
1489 spi6: spi@120A0000 {
1490 compatible = "arm,pl022", "arm,primecell";
1491 reg = <0x0 0x120A0000 0x0 0x10000>;
1492 clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1493 clock-names = "apb_pclk";
1494 resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1495 reset-names = "rst_apb";
1497 /* shortage of dma channel that not be used */
1498 /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1499 /*dma-names = "rx","tx";*/
1500 arm,primecell-periphid = <0x00041022>;
1502 #address-cells = <1>;
1504 status = "disabled";
1507 pcie0: pcie@2B000000 {
1508 compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1509 #address-cells = <3>;
1511 #interrupt-cells = <1>;
1512 reg = <0x0 0x2B000000 0x0 0x1000000
1513 0x9 0x40000000 0x0 0x10000000>;
1514 reg-names = "reg", "config";
1515 device_type = "pci";
1516 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1517 bus-range = <0x0 0xff>;
1518 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
1519 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
1520 msi-parent = <&plic>;
1522 interrupt-controller;
1523 interrupt-names = "msi";
1524 interrupt-parent = <&plic>;
1525 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1526 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1527 <0x0 0x0 0x0 0x2 &plic 0x2>,
1528 <0x0 0x0 0x0 0x3 &plic 0x3>,
1529 <0x0 0x0 0x0 0x4 &plic 0x4>;
1530 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1531 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1532 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1533 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1534 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1535 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1536 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1537 "rst_brg", "rst_core", "rst_apb";
1538 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1539 <&clkgen JH7110_PCIE0_CLK_TL>,
1540 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1541 <&clkgen JH7110_PCIE0_CLK_APB>;
1542 clock-names = "noc", "tl", "axi_mst0", "apb";
1543 status = "disabled";
1546 pcie1: pcie@2C000000 {
1547 compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1548 #address-cells = <3>;
1550 #interrupt-cells = <1>;
1551 reg = <0x0 0x2C000000 0x0 0x1000000
1552 0x9 0xc0000000 0x0 0x10000000>;
1553 reg-names = "reg", "config";
1554 device_type = "pci";
1555 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1556 bus-range = <0x0 0xff>;
1557 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
1558 <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
1559 msi-parent = <&plic>;
1561 interrupt-controller;
1562 interrupt-names = "msi";
1563 interrupt-parent = <&plic>;
1564 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1565 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1566 <0x0 0x0 0x0 0x2 &plic 0x2>,
1567 <0x0 0x0 0x0 0x3 &plic 0x3>,
1568 <0x0 0x0 0x0 0x4 &plic 0x4>;
1569 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1570 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1571 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1572 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1573 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1574 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1575 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1576 "rst_brg", "rst_core", "rst_apb";
1577 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1578 <&clkgen JH7110_PCIE1_CLK_TL>,
1579 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1580 <&clkgen JH7110_PCIE1_CLK_APB>;
1581 clock-names = "noc", "tl", "axi_mst0", "apb";
1582 status = "disabled";
1585 mailbox_contrl0: mailbox@0 {
1586 compatible = "starfive,mail_box";
1587 reg = <0x0 0x13060000 0x0 0x0001000>;
1588 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1589 clock-names = "clk_apb";
1590 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1591 reset-names = "mbx_rre";
1592 interrupts = <26 27>;
1594 status = "disabled";
1597 mailbox_client0: mailbox_client@0 {
1598 compatible = "starfive,mailbox-test";
1599 mbox-names = "rx", "tx";
1600 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1601 status = "disabled";
1604 display: display-subsystem {
1605 compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1606 ports = <&dc_out_dpi0>;
1607 status = "disabled";
1610 dssctrl: dssctrl@295B0000 {
1611 compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1612 reg = <0 0x295B0000 0 0x90>;
1615 tda988x_pin: tda988x_pin {
1616 compatible = "starfive,tda998x_rgb_pin";
1617 status = "disabled";
1620 rgb_output: rgb-output {
1621 compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1622 //verisilicon,dss-syscon = <&dssctrl>;
1623 //verisilicon,mux-mask = <0x70 0x380>;
1624 //verisilicon,mux-val = <0x40 0x280>;
1625 status = "disabled";
1628 dc8200: dc8200@29400000 {
1629 compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1630 verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1631 reg = <0x0 0x29400000 0x0 0x100>,
1632 <0x0 0x29400800 0x0 0x2000>,
1633 <0x0 0x17030000 0x0 0x1000>;
1635 status = "disabled";
1636 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1637 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1638 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1639 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1640 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1641 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1642 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1643 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1644 <&clkgen JH7110_VOUT_SRC>,
1645 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1646 <&clkgen JH7110_AHB1>,
1647 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1648 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1649 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1650 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1651 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1652 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1653 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1654 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1655 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1656 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1657 <&hdmitx0_pixelclk>,
1658 <&clkvout JH7110_DC8200_PIX0>,
1659 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1660 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1661 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1662 "noc_disp","noc_isp","noc_stg","vout_src",
1663 "top_vout_axi","ahb1","top_vout_ahb",
1664 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1665 "axi_clk","core_clk","vout_ahb",
1666 "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1667 "dc8200_pix0_out","dc8200_pix1_out";
1668 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1669 <&rstgen RSTN_U0_DC8200_AXI>,
1670 <&rstgen RSTN_U0_DC8200_AHB>,
1671 <&rstgen RSTN_U0_DC8200_CORE>,
1672 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1673 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1674 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1675 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1676 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1677 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1678 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1679 "rst_noc_disp","rst_noc_stg";
1680 power-domains = <&pwrc JH7110_PD_VOUT>;
1683 dsi_output: dsi-output {
1684 compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1685 status = "disabled";
1688 mipi_dphy: mipi-dphy@295e0000{
1689 compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1690 reg = <0x0 0x295e0000 0x0 0x10000>;
1691 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1692 clock-names = "dphy_txesc";
1693 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1694 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1695 reset-names = "dphy_sys", "dphy_txbytehs";
1697 status = "disabled";
1700 mipi_dsi: mipi@295d0000 {
1701 compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1702 reg = <0x0 0x295d0000 0x0 0x10000>;
1705 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1706 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1707 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1708 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1709 clock-names = "sys", "apb", "txesc", "dpi";
1710 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1711 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1712 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1713 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1714 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1715 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1716 reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1717 "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1718 phys = <&mipi_dphy>;
1720 status = "disabled";
1723 dsi_out_port: endpoint@0 {
1724 remote-endpoint = <&panel_dsi_port>;
1726 dsi_in_port: endpoint@1 {
1727 remote-endpoint = <&mipi_out>;
1731 mipi_panel: panel@0 {
1732 /*compatible = "";*/
1737 hdmi: hdmi@29590000 {
1738 compatible = "starfive,jh7110-hdmi","inno,hdmi";
1739 reg = <0x0 0x29590000 0x0 0x4000>;
1741 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1742 /*clocks = <&cru PCLK_HDMI>;*/
1743 /*clock-names = "pclk";*/
1744 /*pinctrl-names = "default";*/
1745 /*pinctrl-0 = <&hdmi_ctl>;*/
1746 status = "disabled";
1747 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1748 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1749 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1750 <&hdmitx0_pixelclk>;
1751 clock-names = "sysclk", "mclk", "bclk", "pclk";
1752 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1753 reset-names = "hdmi_tx";
1754 #sound-dai-cells = <0>;
1758 compatible = "simple-audio-card";
1759 simple-audio-card,name = "Starfive-Multi-Sound-Card";
1760 #address-cells = <1>;
1765 compatible = "starfive,e24";
1766 reg = <0x0 0xc0110000 0x0 0x00001000>,
1767 <0x0 0xc0111000 0x0 0x0001f000>;
1768 reg-names = "ecmd", "espace";
1769 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1770 <&clkgen JH7110_E2_CLK_CORE>,
1771 <&clkgen JH7110_E2_CLK_DBG>;
1772 clock-names = "clk_rtc", "clk_core", "clk_dbg";
1773 resets = <&rstgen RSTN_U0_E24_CORE>;
1774 reset-names = "e24_core";
1775 starfive,stg-syscon = <&stg_syscon>;
1776 interrupt-parent = <&plic>;
1777 firmware-name = "e24_elf";
1779 mbox-names = "tx", "rx";
1780 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1781 #address-cells = <1>;
1783 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1784 status = "disabled";
1789 compatible = "cdns,xrp";
1790 reg = <0x0 0x10230000 0x0 0x00010000
1791 0x0 0x10240000 0x0 0x00010000>;
1792 memory-region = <&xrp_reserved>;
1793 clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1794 clock-names = "core_clk";
1795 resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1796 <&rstgen RSTN_U0_HIFI4_AXI>;
1797 reset-names = "rst_core","rst_axi";
1798 starfive,stg-syscon = <&stg_syscon>;
1799 firmware-name = "hifi4_elf";
1800 #address-cells = <1>;
1802 ranges = <0x40000000 0x0 0x20000000 0x040000
1803 0xf0000000 0x0 0xf0000000 0x03000000>;
1804 status = "disabled";
1809 starfive_cpufreq: starfive,jh7110-cpufreq {
1810 compatible = "starfive,jh7110-cpufreq";
1811 clocks = <&clkgen JH7110_PLL0_OUT>,
1812 <&clkgen JH7110_CPU_ROOT>,
1814 clock-names = "pll0", "cpu_clk", "osc";