arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110_clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12
  13 / {
  14         compatible = "starfive,jh7110";
  15         #address-cells = <2>;
  16         #size-cells = <2>;
  17
  18         cpus {
  19                 #address-cells = <1>;
  20                 #size-cells = <0>;
  21
  22                 cpu0: cpu@0 {
  23                         compatible = "sifive,u74-mc", "riscv";
  24                         reg = <0>;
  25                         d-cache-block-size = <64>;
  26                         d-cache-sets = <64>;
  27                         d-cache-size = <8192>;
  28                         d-tlb-sets = <1>;
  29                         d-tlb-size = <40>;
  30                         device_type = "cpu";
  31                         i-cache-block-size = <64>;
  32                         i-cache-sets = <64>;
  33                         i-cache-size = <16384>;
  34                         i-tlb-sets = <1>;
  35                         i-tlb-size = <40>;
  36                         mmu-type = "riscv,sv39";
  37                         next-level-cache = <&cachectrl>;
  38                         riscv,isa = "rv64imac";
  39                         tlb-split;
  40                         status = "disabled";
  41
  42                         cpu0intctrl: interrupt-controller {
  43                                 #interrupt-cells = <1>;
  44                                 compatible = "riscv,cpu-intc";
  45                                 interrupt-controller;
  46                         };
  47                 };
  48
  49                 cpu1: cpu@1 {
  50                         compatible = "sifive,u74-mc", "riscv";
  51                         reg = <1>;
  52                         d-cache-block-size = <64>;
  53                         d-cache-sets = <64>;
  54                         d-cache-size = <32768>;
  55                         d-tlb-sets = <1>;
  56                         d-tlb-size = <40>;
  57                         device_type = "cpu";
  58                         i-cache-block-size = <64>;
  59                         i-cache-sets = <64>;
  60                         i-cache-size = <32768>;
  61                         i-tlb-sets = <1>;
  62                         i-tlb-size = <40>;
  63                         mmu-type = "riscv,sv39";
  64                         next-level-cache = <&cachectrl>;
  65                         riscv,isa = "rv64imafdc";
  66                         tlb-split;
  67                         status = "okay";
  68
  69                         cpu1intctrl: interrupt-controller {
  70                                 #interrupt-cells = <1>;
  71                                 compatible = "riscv,cpu-intc";
  72                                 interrupt-controller;
  73                         };
  74                 };
  75
  76                 cpu2: cpu@2 {
  77                         compatible = "sifive,u74-mc", "riscv";
  78                         reg = <2>;
  79                         d-cache-block-size = <64>;
  80                         d-cache-sets = <64>;
  81                         d-cache-size = <32768>;
  82                         d-tlb-sets = <1>;
  83                         d-tlb-size = <40>;
  84                         device_type = "cpu";
  85                         i-cache-block-size = <64>;
  86                         i-cache-sets = <64>;
  87                         i-cache-size = <32768>;
  88                         i-tlb-sets = <1>;
  89                         i-tlb-size = <40>;
  90                         mmu-type = "riscv,sv39";
  91                         next-level-cache = <&cachectrl>;
  92                         riscv,isa = "rv64imafdc";
  93                         tlb-split;
  94                         status = "okay";
  95
  96                         cpu2intctrl: interrupt-controller {
  97                                 #interrupt-cells = <1>;
  98                                 compatible = "riscv,cpu-intc";
  99                                 interrupt-controller;
 100                         };
 101                 };
 102
 103                 cpu3: cpu@3 {
 104                         compatible = "sifive,u74-mc", "riscv";
 105                         reg = <3>;
 106                         d-cache-block-size = <64>;
 107                         d-cache-sets = <64>;
 108                         d-cache-size = <32768>;
 109                         d-tlb-sets = <1>;
 110                         d-tlb-size = <40>;
 111                         device_type = "cpu";
 112                         i-cache-block-size = <64>;
 113                         i-cache-sets = <64>;
 114                         i-cache-size = <32768>;
 115                         i-tlb-sets = <1>;
 116                         i-tlb-size = <40>;
 117                         mmu-type = "riscv,sv39";
 118                         next-level-cache = <&cachectrl>;
 119                         riscv,isa = "rv64imafdc";
 120                         tlb-split;
 121                         status = "okay";
 122
 123                         cpu3intctrl: interrupt-controller {
 124                                 #interrupt-cells = <1>;
 125                                 compatible = "riscv,cpu-intc";
 126                                 interrupt-controller;
 127                         };
 128                 };
 129
 130                 cpu4: cpu@4 {
 131                         compatible = "sifive,u74-mc", "riscv";
 132                         reg = <4>;
 133                         d-cache-block-size = <64>;
 134                         d-cache-sets = <64>;
 135                         d-cache-size = <32768>;
 136                         d-tlb-sets = <1>;
 137                         d-tlb-size = <40>;
 138                         device_type = "cpu";
 139                         i-cache-block-size = <64>;
 140                         i-cache-sets = <64>;
 141                         i-cache-size = <32768>;
 142                         i-tlb-sets = <1>;
 143                         i-tlb-size = <40>;
 144                         mmu-type = "riscv,sv39";
 145                         next-level-cache = <&cachectrl>;
 146                         riscv,isa = "rv64imafdc";
 147                         tlb-split;
 148                         status = "okay";
 149
 150                         cpu4intctrl: interrupt-controller {
 151                                 #interrupt-cells = <1>;
 152                                 compatible = "riscv,cpu-intc";
 153                                 interrupt-controller;
 154                         };
 155                 };
 156         };
 157
 158         soc: soc {
 159                 compatible = "simple-bus";
 160                 interrupt-parent = <&plic>;
 161                 #address-cells = <2>;
 162                 #size-cells = <2>;
 163                 #clock-cells = <1>;
 164                 ranges;
 165
 166                 cachectrl: cache-controller@2010000 {
 167                         compatible = "sifive,fu740-c000-ccache", "cache";
 168                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 169                         reg-names = "control", "sideband";
 170                         interrupts = <1 3 4 2>;
 171                         cache-block-size = <64>;
 172                         cache-level = <2>;
 173                         cache-sets = <2048>;
 174                         cache-size = <2097152>;
 175                         cache-unified;
 176                 };
 177
 178                 aon_syscon: aon_syscon@17010000 {
 179                         compatible = "syscon";
 180                         reg = <0x0 0x17010000 0x0 0x1000>;
 181                 };
 182
 183                 stg_syscon: stg_syscon@10240000 {
 184                         compatible = "syscon";
 185                         reg = <0x0 0x10240000 0x0 0x1000>;
 186                 };
 187
 188                 sys_syscon: sys_syscon@13030000 {
 189                         compatible = "syscon";
 190                         reg = <0x0 0x13030000 0x0 0x1000>;
 191                 };
 192
 193                 clint: clint@2000000 {
 194                         compatible = "riscv,clint0";
 195                         reg = <0x0 0x2000000 0x0 0x10000>;
 196                         reg-names = "control";
 197                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 198                                                 &cpu1intctrl 3 &cpu1intctrl 7
 199                                                 &cpu2intctrl 3 &cpu2intctrl 7
 200                                                 &cpu3intctrl 3 &cpu3intctrl 7
 201                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 202                         #interrupt-cells = <1>;
 203                 };
 204
 205                 plic: plic@c000000 {
 206                         compatible = "riscv,plic0";
 207                         reg = <0x0 0xc000000 0x0 0x4000000>;
 208                         reg-names = "control";
 209                         interrupts-extended = <&cpu0intctrl 11
 210                                                 &cpu1intctrl 11 &cpu1intctrl 9
 211                                                 &cpu2intctrl 11 &cpu2intctrl 9
 212                                                 &cpu3intctrl 11 &cpu3intctrl 9
 213                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 214                         interrupt-controller;
 215                         #interrupt-cells = <1>;
 216                         riscv,max-priority = <7>;
 217                         riscv,ndev = <136>;
 218                 };
 219
 220                 clkgen: clock-controller {
 221                         compatible = "starfive,jh7110-clkgen";
 222                         reg = <0x0 0x13020000 0x0 0x10000>,
 223                                 <0x0 0x10230000 0x0 0x10000>,
 224                                 <0x0 0x17000000 0x0 0x10000>;
 225                         reg-names = "sys", "stg", "aon";
 226                         clocks = <&osc>, <&gmac1_rmii_refin>,
 227                                 <&gmac1_rgmii_rxin>,
 228                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 229                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 230                                 <&tdm_ext>, <&mclk_ext>,
 231                                 <&jtag_tck_inner>, <&bist_apb>,
 232                                 <&stg_apb>, <&clk_rtc>,
 233                                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 234                         clock-names = "osc", "gmac1_rmii_refin",
 235                                 "gmac1_rgmii_rxin",
 236                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 237                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 238                                 "tdm_ext", "mclk_ext",
 239                                 "jtag_tck_inner", "bist_apb",
 240                                 "stg_apb", "clk_rtc",
 241                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 242                         #clock-cells = <1>;
 243                         status = "okay";
 244                 };
 245
 246                 clkvout: clock-controller@295C0000 {
 247                         compatible = "starfive,jh7110-clk-vout";
 248                         reg = <0x0 0x295C0000 0x0 0x10000>;
 249                         reg-names = "vout";
 250                         clocks = <&hdmitx0_pixelclk>,
 251                                 <&mipitx_dphy_rxesc>,
 252                                 <&mipitx_dphy_txbytehs>;
 253                         clock-names = "hdmitx0_pixelclk",
 254                                 "mipitx_dphy_rxesc",
 255                                 "mipitx_dphy_txbytehs";
 256                         #clock-cells = <1>;
 257                         status = "disabled";
 258                 };
 259
 260                 clkisp: clock-controller@19810000 {
 261                         compatible = "starfive,jh7110-clk-isp";
 262                         reg = <0x0 0x19810000 0x0 0x10000>;
 263                         reg-names = "isp";
 264                         #clock-cells = <1>;
 265                         status = "disabled";
 266                 };
 267
 268                 qspi: qspi@13010000 {
 269                         compatible = "cadence,qspi","cdns,qspi-nor";
 270                         #address-cells = <1>;
 271                         #size-cells = <0>;
 272                         reg = <0x0 0x13010000 0x0 0x10000
 273                                 0x0 0x21000000 0x0 0x400000>;
 274                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 275                         clock-names = "clk_ref";
 276                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 277                                         <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 278                                         <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 279                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 280                         cdns,fifo-depth = <256>;
 281                         cdns,fifo-width = <4>;
 282                         spi-max-frequency = <250000000>;
 283
 284                         nor_flash: nor-flash@0 {
 285                                 compatible = "jedec,spi-nor";
 286                                 reg=<0>;
 287                                 spi-max-frequency = <100000000>;
 288                                 cdns,tshsl-ns = <1>;
 289                                 cdns,tsd2d-ns = <1>;
 290                                 cdns,tchsh-ns = <1>;
 291                                 cdns,tslch-ns = <1>;
 292                         };
 293                 };
 294
 295                 otp: otp@17050000 {
 296                         compatible = "starfive,jh7110-otp";
 297                         reg = <0x0 0x17050000 0x0 0x10000>;
 298                         clock-frequency = <4000000>;
 299                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 300                         clock-names = "apb";
 301                 };
 302
 303                 USB30: usb@10100000 {
 304                         compatible = "cdns,usb3";
 305                         reg = <0x0 0x10100000 0x0 0x10000>,
 306                                 <0x0 0x10110000 0x0 0x10000>,
 307                                 <0x0 0x10120000 0x0 0x10000>;
 308                         reg-names = "otg", "xhci", "dev";
 309                         phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 310                         clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
 311                                 <&clkgen JH7110_USB0_CLK_LPM>,
 312                                 <&clkgen JH7110_USB0_CLK_STB>,
 313                                 <&clkgen JH7110_USB0_CLK_USB_APB>,
 314                                 <&clkgen JH7110_USB0_CLK_AXI>,
 315                                 <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 316                         clock-names = "app","lpm","stb","apb","axi","utmi";
 317                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 318                                         <&rstgen RSTN_U0_CDN_USB_APB>,
 319                                         <&rstgen RSTN_U0_CDN_USB_AXI>,
 320                                         <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 321                         reset-names = "rst_pwrup","rst_apb","rst_axi","rst_utmi";
 322                 };
 323
 324                 timer: timer@13050000 {
 325                         compatible = "starfive,si5-timers";
 326                         reg = <0x0 0x13050000 0x0 0x10000>;
 327                         interrupts = <69>, <70>, <71> ,<72>;
 328                         interrupt-names = "timer0", "timer1",
 329                                           "timer2", "timer3";
 330                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 331                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 332                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 333                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 334                                  <&clkgen JH7110_TIMER_CLK_APB>;
 335                         clock-names = "timer0", "timer1",
 336                                       "timer2", "timer3", "apb_clk";
 337                         clock-frequency = <2000000>;
 338                         status = "okay";
 339                 };
 340
 341                 wdog: wdog@13070000 {
 342                         compatible = "starfive,dskit-wdt";
 343                         reg = <0x0 0x13070000 0x0 0x10000>;
 344                         interrupts = <68>;
 345                         interrupt-names = "wdog";
 346                         clock-frequency = <2000000>;
 347                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 348                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 349                         clock-names = "core_clk", "apb_clk";
 350                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 351                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 352                         reset-names = "rst_apb", "rst_core";
 353                         timeout-sec = <15>;
 354                         status = "okay";
 355                 };
 356
 357                 rtc: rtc@17040000 {
 358                         compatible = "starfive,rtc_hms";
 359                         reg = <0x0 0x17040000 0x0 0x10000>;
 360                         interrupts = <10>, <11>, <12>;
 361                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 362                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 363                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 364                         clock-names = "pclk", "cal_clk";
 365                         resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
 366                                  <&rstgen RSTN_U0_RTC_HMS_CAL>,
 367                                  <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
 368                         reset-names = "rst_apb", "rst_cal", "rst_osc";
 369                         rtc,cal-clock-freq = <1000000>;
 370                         status = "okay";
 371                 };
 372
 373                 pmu: pmu@17030000 {
 374                         compatible = "starfive,jh7110-pmu";
 375                         reg = <0x0 0x17030000 0x0 0x10000>;
 376                         interrupts = <111>;
 377                         status = "okay";
 378                 };
 379
 380                 uart0: serial@10000000 {
 381                         compatible = "snps,dw-apb-uart";
 382                         reg = <0x0 0x10000000 0x0 0x10000>;
 383                         reg-io-width = <4>;
 384                         reg-shift = <2>;
 385                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 386                                         <&clkgen JH7110_UART0_CLK_APB>;
 387                         clock-names = "baudclk", "apb_pclk";
 388                         resets = <&rstgen RSTN_U0_DW_UART_APB>;
 389                         interrupts = <32>;
 390                         status = "disabled";
 391                 };
 392
 393                 uart1: serial@10010000 {
 394                         compatible = "snps,dw-apb-uart";
 395                         reg = <0x0 0x10010000 0x0 0x10000>;
 396                         reg-io-width = <4>;
 397                         reg-shift = <2>;
 398                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 399                                         <&clkgen JH7110_UART1_CLK_APB>;
 400                         clock-names = "baudclk", "apb_pclk";
 401                         resets = <&rstgen RSTN_U1_DW_UART_APB>;
 402                         interrupts = <33>;
 403                         status = "disabled";
 404                 };
 405
 406                 uart2: serial@10020000 {
 407                         compatible = "snps,dw-apb-uart";
 408                         reg = <0x0 0x10020000 0x0 0x10000>;
 409                         reg-io-width = <4>;
 410                         reg-shift = <2>;
 411                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 412                                         <&clkgen JH7110_UART2_CLK_APB>;
 413                         clock-names = "baudclk", "apb_pclk";
 414                         resets = <&rstgen RSTN_U2_DW_UART_APB>;
 415                         interrupts = <34>;
 416                         status = "disabled";
 417                 };
 418
 419                 uart3: serial@12000000 {
 420                         compatible = "snps,dw-apb-uart";
 421                         reg = <0x0 0x12000000 0x0 0x10000>;
 422                         reg-io-width = <4>;
 423                         reg-shift = <2>;
 424                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 425                                         <&clkgen JH7110_UART3_CLK_APB>;
 426                         clock-names = "baudclk", "apb_pclk";
 427                         resets = <&rstgen RSTN_U3_DW_UART_APB>;
 428                         interrupts = <45>;
 429                         status = "disabled";
 430                 };
 431
 432                 uart4: serial@12010000 {
 433                         compatible = "snps,dw-apb-uart";
 434                         reg = <0x0 0x12010000 0x0 0x10000>;
 435                         reg-io-width = <4>;
 436                         reg-shift = <2>;
 437                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 438                                         <&clkgen JH7110_UART4_CLK_APB>;
 439                         clock-names = "baudclk", "apb_pclk";
 440                         resets = <&rstgen RSTN_U4_DW_UART_APB>;
 441                         interrupts = <46>;
 442                         status = "disabled";
 443                 };
 444
 445                 uart5: serial@12020000 {
 446                         compatible = "snps,dw-apb-uart";
 447                         reg = <0x0 0x12020000 0x0 0x10000>;
 448                         reg-io-width = <4>;
 449                         reg-shift = <2>;
 450                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 451                                         <&clkgen JH7110_UART5_CLK_APB>;
 452                         clock-names = "baudclk", "apb_pclk";
 453                         resets = <&rstgen RSTN_U5_DW_UART_APB>;
 454                         interrupts = <47>;
 455                         status = "disabled";
 456                 };
 457
 458                 dma: dma-controller@16050000 {
 459                         compatible = "starfive,axi-dma";
 460                         reg = <0x0 0x16050000 0x0 0x10000>;
 461                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 462                                 <&clkgen JH7110_DMA1P_CLK_AHB>;
 463                         clock-names = "core-clk", "cfgr-clk";
 464                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 465                                 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 466                         reset-names = "rst_axi",
 467                                 "rst_ahb";
 468                         interrupts = <73>;
 469                         #dma-cells = <2>;
 470                         dma-channels = <4>;
 471                         snps,dma-masters = <1>;
 472                         snps,data-width = <3>;
 473                         snps,num-hs-if = <56>;
 474                         snps,block-size = <65536 65536 65536 65536>;
 475                         snps,priority = <0 1 2 3>;
 476                         snps,axi-max-burst-len = <16>;
 477                         status = "disabled";
 478                 };
 479
 480                 gpio: gpio@13040000 {
 481                         compatible = "starfive_jh7110-sys-pinctrl";
 482                         reg = <0x0 0x13040000 0x0 0x10000>;
 483                         reg-names = "control";
 484                         interrupts = <91>;
 485                         interrupt-controller;
 486                         #gpio-cells = <2>;
 487                         ngpios = <64>;
 488                         status = "okay";
 489                 };
 490
 491                 gpioa: gpio@17020000 {
 492                         compatible = "starfive_jh7110-aon-pinctrl";
 493                         reg = <0x0 0x17020000 0x0 0x10000>;
 494                         reg-names = "control";
 495                         interrupts = <90>;
 496                         interrupt-controller;
 497                         #gpio-cells = <2>;
 498                         ngpios = <4>;
 499                         status = "okay";
 500                 };
 501
 502                 trng: trng@1600C000 {
 503                         compatible = "starfive,trng";
 504                         reg = <0x0 0x1600C000 0x0 0x4000>;
 505                         clocks = <&clkgen JH7110_SEC_HCLK>,
 506                                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
 507                         clock-names = "hclk", "miscahb_clk";
 508                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 509                         interrupts = <30>;
 510                         status = "disabled";
 511                 };
 512
 513                 i2c6: i2c@12060000 {
 514                         compatible = "snps,designware-i2c";
 515                         reg = <0x0 0x12060000 0x0 0x10000>;
 516                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 517                                  <&clkgen JH7110_I2C6_CLK_APB>;
 518                         clock-names = "ref", "pclk";
 519                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 520                         interrupts = <51>;
 521                         #address-cells = <1>;
 522                         #size-cells = <0>;
 523                         status = "disabled";
 524                 };
 525
 526                 i2c0: i2c@10030000 {
 527                         compatible = "snps,designware-i2c";
 528                         reg = <0x0 0x10030000 0x0 0x10000>;
 529                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 530                                  <&clkgen JH7110_I2C0_CLK_APB>;
 531                         clock-names = "ref", "pclk";
 532                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 533                         interrupts = <35>;
 534                         #address-cells = <1>;
 535                         #size-cells = <0>;
 536                         status = "disabled";
 537                 };
 538
 539                 i2c1: i2c@10040000 {
 540                         compatible = "snps,designware-i2c";
 541                         reg = <0x0 0x10040000 0x0 0x10000>;
 542                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 543                                  <&clkgen JH7110_I2C1_CLK_APB>;
 544                         clock-names = "ref", "pclk";
 545                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 546                         interrupts = <36>;
 547                         #address-cells = <1>;
 548                         #size-cells = <0>;
 549                         status = "disabled";
 550                 };
 551
 552                 /* unremovable emmc as mmcblk0 */
 553                 sdio0: sdio0@16010000 {
 554                         compatible = "snps,dw-mshc";
 555                         reg = <0x0 0x16010000 0x0 0x10000>;
 556                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 557                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 558                         clock-names = "biu","ciu";
 559                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 560                         reset-names = "reset";
 561                         interrupts = <74>;
 562                         fifo-depth = <32>;
 563                         fifo-watermark-aligned;
 564                         data-addr = <0>;
 565                         status = "disabled";
 566                 };
 567
 568                 sdio1: sdio1@16020000 {
 569                         compatible = "snps,dw-mshc";
 570                         reg = <0x0 0x16020000 0x0 0x10000>;
 571                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 572                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 573                         clock-names = "biu","ciu";
 574                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 575                         reset-names = "reset";
 576                         interrupts = <75>;
 577                         fifo-depth = <32>;
 578                         fifo-watermark-aligned;
 579                         data-addr = <0>;
 580                         status = "disabled";
 581                 };
 582
 583                 vin_sysctl: vin_sysctl@19800000 {
 584                         compatible = "starfive,stf-vin";
 585                         reg = <0x0 0x19800000 0x0 0x10000>,
 586                                 <0x0 0x19810000 0x0 0x10000>,
 587                                 <0x0 0x19820000 0x0 0x10000>,
 588                                 <0x0 0x19830000 0x0 0x10000>,
 589                                 <0x0 0x19840000 0x0 0x10000>,
 590                                 <0x0 0x19870000 0x0 0x30000>,
 591                                 <0x0 0x198a0000 0x0 0x30000>,
 592                                 <0x0 0x11800000 0x0 0x10000>,
 593                                 <0x0 0x11840000 0x0 0x10000>,
 594                                 <0x0 0x11858000 0x0 0x10000>,
 595                                 <0x0 0x17030000 0x0 0x10000>,
 596                                 <0x0 0x13020000 0x0 0x10000>;
 597                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad", "pmu", "syscrg";
 598                         interrupts = <92 87 86>;
 599                         status = "disabled";
 600                 };
 601
 602                 jpu: jpu@11900000 {
 603                         compatible = "starfive,jpu";
 604                         reg = <0x0 0x13090000 0x0 0x300>;
 605                         interrupts = <14>;
 606                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 607                                 <&clkgen JH7110_CODAJ12_CLK_CORE>,
 608                                 <&clkgen JH7110_CODAJ12_CLK_APB>;
 609                         clock-names = "axi_clk", "core_clk", "apb_clk";
 610                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 611                                 <&rstgen RSTN_U0_CODAJ12_CORE>,
 612                                 <&rstgen RSTN_U0_CODAJ12_APB>;
 613                         reset-names = "rst_axi", "rst_core", "rst_apb";
 614                         status = "disabled";
 615                 };
 616
 617                 vpu_dec: vpu_dec@130A0000 {
 618                         compatible = "starfive,vdec";
 619                         reg = <0x0 0x130A0000 0x0 0x10000>;
 620                         interrupts = <13>;
 621                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 622                                 <&clkgen JH7110_WAVE511_CLK_BPU>,
 623                                 <&clkgen JH7110_WAVE511_CLK_VCE>,
 624                                 <&clkgen JH7110_WAVE511_CLK_APB>,
 625                                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 626                         clock-names = "axi_clk",
 627                                 "bpu_clk",
 628                                 "vce_clk",
 629                                 "apb_clk",
 630                                 "noc_bus";
 631                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 632                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 633                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 634                                 <&rstgen RSTN_U0_WAVE511_APB>,
 635                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 636                         reset-names = "rst_axi",
 637                                 "rst_bpu",
 638                                 "rst_vce",
 639                                 "rst_apb",
 640                                 "rst_sram";
 641                         starfive,vdec_noc_ctrl;
 642                         status = "disabled";
 643                 };
 644
 645                 vpu_enc: vpu_enc@130B0000 {
 646                         compatible = "starfive,venc";
 647                         reg = <0x0 0x130B0000 0x0 0x10000>;
 648                         interrupts = <15>;
 649                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 650                                 <&clkgen JH7110_WAVE420L_CLK_BPU>,
 651                                 <&clkgen JH7110_WAVE420L_CLK_VCE>,
 652                                 <&clkgen JH7110_WAVE420L_CLK_APB>,
 653                                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 654                         clock-names = "axi_clk",
 655                                 "bpu_clk",
 656                                 "vce_clk",
 657                                 "apb_clk",
 658                                 "noc_bus";
 659                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 660                                 <&rstgen RSTN_U0_WAVE420L_BPU>,
 661                                 <&rstgen RSTN_U0_WAVE420L_VCE>,
 662                                 <&rstgen RSTN_U0_WAVE420L_APB>,
 663                                 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 664                         reset-names = "rst_axi",
 665                                 "rst_bpu",
 666                                 "rst_vce",
 667                                 "rst_apb",
 668                                 "rst_sram";
 669                         starfive,venc_noc_ctrl;
 670                         status = "disabled";
 671                 };
 672
 673                 rstgen: reset-controller {
 674                         compatible = "starfive,jh7110-reset";
 675                         reg = <0x0 0x13020000 0x0 0x10000>,
 676                                 <0x0 0x10230000 0x0 0x10000>,
 677                                 <0x0 0x17000000 0x0 0x10000>,
 678                                 <0x0 0x19810000 0x0 0x10000>,
 679                                 <0x0 0x295C0000 0x0 0x10000>;
 680                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 681                         #reset-cells = <1>;
 682                         status = "okay";
 683                 };
 684
 685                 stmmac_axi_setup: stmmac-axi-config {
 686                         snps,wr_osr_lmt = <0xf>;
 687                         snps,rd_osr_lmt = <0xf>;
 688                         snps,blen = <256 128 64 32 0 0 0>;
 689                 };
 690
 691                 gmac0: ethernet@16030000 {
 692                         compatible = "starfive,jh7110-eqos-5.20";
 693                         reg = <0x0 0x16030000 0x0 0x10000>;
 694                         clock-names = "gtx",
 695                                 "tx",
 696                                 "ptp_ref",
 697                                 "stmmaceth",
 698                                 "pclk";
 699                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 700                                 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 701                                 <&clkgen JH7110_GMAC0_PTP>,
 702                                 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 703                                 <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
 704                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 705                                         <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 706                         reset-names = "ahb", "stmmaceth";
 707                         interrupts = <7>, <6>, <5> ;
 708                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 709                         max-frame-size = <9000>;
 710                         phy-mode = "rgmii-id";
 711                         snps,multicast-filter-bins = <256>;
 712                         snps,perfect-filter-entries = <128>;
 713                         rx-fifo-depth = <262144>;
 714                         tx-fifo-depth = <131072>;
 715                         snps,fixed-burst;
 716                         snps,no-pbl-x8;
 717                         snps,force_thresh_dma_mode;
 718                         snps,axi-config = <&stmmac_axi_setup>;
 719                         snps,tso;
 720                         snps,en-tx-lpi-clockgating;
 721                         snps,en-lpi;
 722                         snps,write-requests = <2>;
 723                         snps,read-requests = <16>;
 724                         snps,burst-map = <0x7>;
 725                         snps,txpbl = <16>;
 726                         snps,rxpbl = <16>;
 727                         status = "disabled";
 728                 };
 729
 730                 gmac1: ethernet@16040000 {
 731                         compatible = "starfive,jh7110-eqos-5.20";
 732                         reg = <0x0 0x16040000 0x0 0x10000>;
 733                         clock-names = "gtx",
 734                                 "tx",
 735                                 "ptp_ref",
 736                                 "stmmaceth",
 737                                 "pclk";
 738                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 739                                 <&clkgen JH7110_GMAC5_CLK_TX>,
 740                                 <&clkgen JH7110_GMAC5_CLK_PTP>,
 741                                 <&clkgen JH7110_GMAC5_CLK_AHB>,
 742                                 <&clkgen JH7110_GMAC5_CLK_AXI>;
 743                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
 744                                         <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 745                         reset-names = "ahb", "stmmaceth";
 746                         interrupts = <78>, <77>, <76> ;
 747                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 748                         max-frame-size = <9000>;
 749                         phy-mode = "rgmii-id";
 750                         snps,multicast-filter-bins = <256>;
 751                         snps,perfect-filter-entries = <128>;
 752                         rx-fifo-depth = <262144>;
 753                         tx-fifo-depth = <131072>;
 754                         snps,fixed-burst;
 755                         snps,no-pbl-x8;
 756                         snps,force_thresh_dma_mode;
 757                         snps,axi-config = <&stmmac_axi_setup>;
 758                         snps,tso;
 759                         snps,en-tx-lpi-clockgating;
 760                         snps,en-lpi;
 761                         snps,write-requests = <2>;
 762                         snps,read-requests = <16>;
 763                         snps,burst-map = <0x7>;
 764                         snps,txpbl = <16>;
 765                         snps,rxpbl = <16>;
 766                         status = "disabled";
 767                 };
 768
 769                 gpu: gpu@18000000 {
 770                         compatible = "img-gpu";
 771                         reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
 772                         clocks = <&gpu_core_clk>, <&gpu_sys_clk>;
 773                         clock-names = "gpu_core_clk","gpu_sys_clk";
 774                         interrupts = <82>;
 775                         current-clock = <8000000>;
 776                         status = "disabled";
 777                 };
 778
 779                 can0: can@130d0000 {
 780                         compatible = "ipms,can";
 781                         reg = <0x0 0x130d0000 0x0 0x1000>;
 782                         interrupts = <112>;
 783                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
 784                                 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
 785                                 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
 786                         clock-names = "apb_clk",
 787                                         "core_clk",
 788                                         "timer_clk";
 789                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
 790                                 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
 791                                 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
 792                         reset-names = "rst_apb",
 793                                         "rst_core",
 794                                         "rst_timer";
 795                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
 796                         syscon,can_or_canfd = <0>;
 797                         status = "disabled";
 798                 };
 799
 800                 can1: can@130e0000 {
 801                         compatible = "ipms,can";
 802                         reg = <0x0 0x130e0000 0x0 0x1000>;
 803                         interrupts = <113>;
 804                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
 805                                 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
 806                                 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
 807                         clock-names = "apb_clk",
 808                                         "core_clk",
 809                                         "timer_clk";
 810                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
 811                                 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
 812                                 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
 813                         reset-names = "rst_apb",
 814                                         "rst_core",
 815                                         "rst_timer";
 816                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
 817                         syscon,can_or_canfd = <0>;
 818                         status = "disabled";
 819                 };
 820
 821                 tdm: tdm@10090000 {
 822                         compatible = "starfive,tdm";
 823                         reg = <0x0 0x10090000 0x0 0x1000>;
 824                         reg-names = "tdm";
 825                         clocks = <&audioclk>;
 826                         clock-names = "audioclk";
 827                         dmas = <&dma 20 1>, <&dma 21 1>;
 828                         dma-names = "rx","tx";
 829                         #sound-dai-cells = <0>;
 830                         status = "disabled";
 831                 };
 832
 833                 spdif0: spdif0@100a0000 {
 834                         compatible = "starfive,sf-spdif";
 835                         reg = <0x0 0x100a0000 0x0 0x1000>;
 836                         clocks = <&audioclk>;
 837                         clock-names = "audioclk";
 838                         interrupts = <84>;
 839                         interrupt-names = "tx";
 840                         #sound-dai-cells = <0>;
 841                         status = "disabled";
 842                 };
 843
 844                 pwmdac: pwmdac@100b0000 {
 845                         compatible = "sf,pwmdac";
 846                         reg = <0x0 0x100b0000 0x0 0x1000>;
 847                         clocks = <&apb0clk>;
 848                         dmas = <&dma 22 1>;
 849                         dma-names = "tx";
 850                         #sound-dai-cells = <0>;
 851                         status = "disabled";
 852                 };
 853
 854                 i2stx: i2stx@100c0000 {
 855                         compatible = "snps,designware-i2stx";
 856                         reg = <0x0 0x100c0000 0x0 0x1000>;
 857                         clocks = <&apb0clk>;
 858                         clock-names = "i2sclk";
 859                         interrupt-names = "tx";
 860                         #sound-dai-cells = <0>;
 861                         dmas = <&dma 28 1>;
 862                         dma-names = "rx";
 863                         status = "disabled";
 864                 };
 865
 866                 pdm: pdm@100d0000 {
 867                         compatible = "starfive,sf-pdm";
 868                         reg = <0x0 0x100d0000 0x0 0x1000>;
 869                         reg-names = "pdm";
 870                         clocks = <&audioclk>;
 871                         clock-names = "audioclk";
 872                         #sound-dai-cells = <0>;
 873                         status = "disabled";
 874                 };
 875
 876                 i2srx_3ch: i2srx-3ch@100e0000 {
 877                         compatible = "snps,designware-i2srx";
 878                         reg = <0x0 0x100e0000 0x0 0x1000>;
 879                         clocks = <&apb0clk>;
 880                         clock-names = "i2sclk";
 881                         interrupts = <42>;
 882                         interrupt-names = "rx";
 883                         #sound-dai-cells = <0>;
 884                         status = "disabled";
 885                 };
 886
 887                 i2stx_4ch0: i2stx-4ch0@120b0000 {
 888                         compatible = "snps,designware-i2stx-4ch0";
 889                         reg = <0x0 0x120b0000 0x0 0x1000>;
 890                         clocks = <&apb0clk>;
 891                         clock-names = "i2sclk";
 892                         interrupts = <58>;
 893                         interrupt-names = "tx";
 894                         #sound-dai-cells = <0>;
 895                         status = "disabled";
 896                 };
 897
 898                 i2stx_4ch1: i2sdac1@120c0000 {
 899                         compatible = "snps,designware-i2stx-4ch1";
 900                         reg = <0x0 0x120c0000 0x0 0x1000>;
 901                         clocks = <&apb0clk>;
 902                         clock-names = "i2sclk";
 903                         interrupts = <59>;
 904                         interrupt-names = "tx";
 905                         #sound-dai-cells = <0>;
 906                         status = "disabled";
 907                 };
 908
 909                 ptc: pwm@120d0000 {
 910                         compatible = "starfive,pwm0";
 911                         reg = <0x0 0x120d0000 0x0 0x10000>;
 912                         reg-names = "control";
 913                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
 914                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
 915                         starfive,approx-period = <2000000>;
 916                         #pwm-cells=<3>;
 917                         starfive,npwm = <8>;
 918                         status = "disabled";
 919                 };
 920
 921                 spdif_transmitter: spdif_transmitter {
 922                         compatible = "linux,spdif-dit";
 923                         #sound-dai-cells = <0>;
 924                         status = "disabled";
 925                 };
 926
 927                 spdif_receiver: spdif_receiver {
 928                         compatible = "linux,spdif-dir";
 929                         #sound-dai-cells = <0>;
 930                         status = "disabled";
 931                 };
 932
 933                 pwmdac_codec: pwmdac-transmitter {
 934                         compatible = "linux,pwmdac-dit";
 935                         #sound-dai-cells = <0>;
 936                         status = "disabled";
 937                 };
 938
 939                 dmic_codec: dmic_codec {
 940                         compatible = "dmic-codec";
 941                         #sound-dai-cells = <0>;
 942                         status = "disabled";
 943                 };
 944
 945                 spi0: spi0@10060000 {
 946                         compatible = "arm,pl022", "arm,primecell";
 947                         reg = <0x0 0x10060000 0x0 0x10000>;
 948                         clocks = <&ahb1clk>;
 949                         clock-names = "apb_pclk";
 950                         interrupts = <38>;
 951                         dmas = <&dma 14 1>, <&dma 15 1>;
 952                         dma-names = "rx","tx";
 953                         arm,primecell-periphid = <0x00041022>;
 954                         num-cs = <1>;
 955                         #address-cells = <1>;
 956                         #size-cells = <0>;
 957                         status = "disabled";
 958                 };
 959
 960                 pcie0: pcie0@2B000000 {
 961                         compatible = "plda,pci-xpressrich3-axi";
 962                         reg = <0x0 0x2B000000 0x0 0x1000000
 963                                0x9 0x40000000 0x0 0x10000000>;
 964                         reg-names = "reg", "config";
 965                         interrupts = <56>;
 966                         interrupt-controller;
 967                         interrupt-names = "msi";
 968                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 969                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
 970                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
 971                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
 972                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
 973                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
 974                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
 975                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
 976                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
 977                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
 978                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 979                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
 980                                       "rst_brg", "rst_core", "rst_apb";
 981                         clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
 982                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
 983                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 984                         clock-names =  "tl", "axi_mst0", "apb";
 985                         #interrupt-cells = <1>;
 986                         device_type = "pci";
 987                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
 988                         bus-range = <0x0 0xff>;
 989                         msi-parent = <&plic>;
 990                         #address-cells = <3>;
 991                         #size-cells = <2>;
 992                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
 993                         status = "disabled";
 994                 };
 995
 996                 pcie1:pcie1@2C000000 {
 997                         compatible = "plda,pci-xpressrich3-axi";
 998                         reg = <0x0 0x2C000000 0x0 0x1000000
 999                                0x9 0xc0000000 0x0 0x10000000>;
1000                         reg-names = "reg", "config";
1001                         device_type = "pci";
1002                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1003                         bus-range = <0x0 0xff>;
1004                         #address-cells = <3>;
1005                         #size-cells = <2>;
1006                         #interrupt-cells = <1>;
1007                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
1008                         msi-parent = <&plic>;
1009                         interrupts = <57>;
1010                         interrupt-controller;
1011                         interrupt-names = "msi";
1012                         interrupt-parent = <&plic>;
1013                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1014                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1015                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1016                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1017                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1018                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1019                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1020                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1021                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1022                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1023                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1024                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1025                                       "rst_brg", "rst_core", "rst_apb";
1026                         clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
1027                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1028                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1029                         clock-names =  "tl", "axi_mst0", "apb";
1030                         status = "disabled";
1031                 };
1032
1033                 mailbox_contrl0: mailbox@0 {
1034                         compatible = "starfive,mail_box";
1035                         reg = <0x0 0x13060000 0x0 0x0001000>;
1036                         interrupts = <26 27>;
1037                         #mbox-cells = <2>;
1038                         status = "disabled";
1039                 };
1040
1041                 mailbox_client0: mailbox_client@0 {
1042                         compatible = "starfive,mailbox-test";
1043                         mbox-names = "rx", "tx";
1044                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1045                         status = "disabled";
1046                 };
1047
1048                 display: display-subsystem {
1049                         compatible = "verisilicon,display-subsystem";
1050                         ports = <&dc_out_dpi0>;
1051                         status = "disabled";
1052                 };
1053
1054                 encoder: display-encoder {
1055                         compatible = "starfive,display-encoder";
1056                         status = "disabled";
1057                 };
1058
1059                 dc8200@29400000 {
1060                         compatible = "verisilicon,dc8200";
1061                         reg = <0x0 0x29400000 0x0 0x100>,<0x0 0x29400800 0x0 0x2000>;
1062                         interrupts = <95>;
1063
1064                         port {
1065                                 #address-cells = <1>;
1066                                 #size-cells = <0>;
1067                                 dc_out_dpi0: endpoint@0 {
1068                                         /*reg = <0>;
1069                                         remote-endpoint = <&hdmi_input>;*/
1070                                 };
1071                                 dc_out_dpi1: endpoint@1 {
1072                                         /*reg = <1>;
1073                                         remote-endpoint = <&vd_input>;*/
1074                                 };
1075                         };
1076                 };
1077
1078                 sound_pwmdac: snd-card_pwmdac {
1079                         compatible = "simple-audio-card";
1080                         simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
1081                         simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
1082                         simple-audio-card,frame-master = <&pwmdac_dailink_master>;
1083                         simple-audio-card,format = "left_j";
1084                         status = "disabled";
1085
1086                         pwmdac_dailink_master: simple-audio-card,cpu {
1087                                 sound-dai = <&pwmdac>;
1088                         };
1089
1090                         simple-audio-card,codec {
1091                                 sound-dai = <&pwmdac_codec>;
1092                         };
1093                 };
1094         };
1095 };