1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110-clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
13 #include <dt-bindings/power/jh7110-power.h>
16 compatible = "starfive,jh7110";
25 compatible = "sifive,u74-mc", "riscv";
27 d-cache-block-size = <64>;
29 d-cache-size = <8192>;
33 i-cache-block-size = <64>;
35 i-cache-size = <16384>;
38 mmu-type = "riscv,sv39";
39 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
40 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
41 next-level-cache = <&cachectrl>;
42 riscv,isa = "rv64imac";
46 cpu0intctrl: interrupt-controller {
47 #interrupt-cells = <1>;
48 compatible = "riscv,cpu-intc";
54 compatible = "sifive,u74-mc", "riscv";
56 d-cache-block-size = <64>;
58 d-cache-size = <32768>;
62 i-cache-block-size = <64>;
64 i-cache-size = <32768>;
67 mmu-type = "riscv,sv39";
68 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
69 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
70 next-level-cache = <&cachectrl>;
71 riscv,isa = "rv64imafdc";
75 cpu1intctrl: interrupt-controller {
76 #interrupt-cells = <1>;
77 compatible = "riscv,cpu-intc";
83 compatible = "sifive,u74-mc", "riscv";
85 d-cache-block-size = <64>;
87 d-cache-size = <32768>;
91 i-cache-block-size = <64>;
93 i-cache-size = <32768>;
96 mmu-type = "riscv,sv39";
97 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
98 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
99 next-level-cache = <&cachectrl>;
100 riscv,isa = "rv64imafdc";
104 cpu2intctrl: interrupt-controller {
105 #interrupt-cells = <1>;
106 compatible = "riscv,cpu-intc";
107 interrupt-controller;
112 compatible = "sifive,u74-mc", "riscv";
114 d-cache-block-size = <64>;
116 d-cache-size = <32768>;
120 i-cache-block-size = <64>;
122 i-cache-size = <32768>;
125 mmu-type = "riscv,sv39";
126 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
127 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
128 next-level-cache = <&cachectrl>;
129 riscv,isa = "rv64imafdc";
133 cpu3intctrl: interrupt-controller {
134 #interrupt-cells = <1>;
135 compatible = "riscv,cpu-intc";
136 interrupt-controller;
141 compatible = "sifive,u74-mc", "riscv";
143 d-cache-block-size = <64>;
145 d-cache-size = <32768>;
149 i-cache-block-size = <64>;
151 i-cache-size = <32768>;
154 mmu-type = "riscv,sv39";
155 cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
156 &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
157 next-level-cache = <&cachectrl>;
158 riscv,isa = "rv64imafdc";
162 cpu4intctrl: interrupt-controller {
163 #interrupt-cells = <1>;
164 compatible = "riscv,cpu-intc";
165 interrupt-controller;
171 CPU_RET_0_0: cpu-retentive-0-0 {
172 compatible = "riscv,idle-state";
173 riscv,sbi-suspend-param = <0x10000000>;
174 entry-latency-us = <20>;
175 exit-latency-us = <40>;
176 min-residency-us = <80>;
179 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
180 compatible = "riscv,idle-state";
181 riscv,sbi-suspend-param = <0x90000000>;
182 entry-latency-us = <250>;
183 exit-latency-us = <500>;
184 min-residency-us = <950>;
187 CLUSTER_RET_0: cluster-retentive-0 {
188 compatible = "riscv,idle-state";
189 riscv,sbi-suspend-param = <0x11000000>;
191 entry-latency-us = <50>;
192 exit-latency-us = <100>;
193 min-residency-us = <250>;
194 wakeup-latency-us = <130>;
197 CLUSTER_NONRET_0: cluster-nonretentive-0 {
198 compatible = "riscv,idle-state";
199 riscv,sbi-suspend-param = <0x91000000>;
201 entry-latency-us = <600>;
202 exit-latency-us = <1100>;
203 min-residency-us = <2700>;
204 wakeup-latency-us = <1500>;
209 compatible = "simple-bus";
210 interrupt-parent = <&plic>;
211 #address-cells = <2>;
216 cachectrl: cache-controller@2010000 {
217 compatible = "sifive,fu740-c000-ccache", "cache";
218 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
219 reg-names = "control", "sideband";
220 interrupts = <1 3 4 2>;
221 cache-block-size = <64>;
224 cache-size = <2097152>;
228 aon_syscon: aon_syscon@17010000 {
229 compatible = "syscon";
230 reg = <0x0 0x17010000 0x0 0x1000>;
233 stg_syscon: stg_syscon@10240000 {
234 compatible = "syscon";
235 reg = <0x0 0x10240000 0x0 0x1000>;
238 sys_syscon: sys_syscon@13030000 {
239 compatible = "syscon";
240 reg = <0x0 0x13030000 0x0 0x1000>;
243 clint: clint@2000000 {
244 compatible = "riscv,clint0";
245 reg = <0x0 0x2000000 0x0 0x10000>;
246 reg-names = "control";
247 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
248 &cpu1intctrl 3 &cpu1intctrl 7
249 &cpu2intctrl 3 &cpu2intctrl 7
250 &cpu3intctrl 3 &cpu3intctrl 7
251 &cpu4intctrl 3 &cpu4intctrl 7>;
252 #interrupt-cells = <1>;
256 compatible = "riscv,plic0";
257 reg = <0x0 0xc000000 0x0 0x4000000>;
258 reg-names = "control";
259 interrupts-extended = <&cpu0intctrl 11
260 &cpu1intctrl 11 &cpu1intctrl 9
261 &cpu2intctrl 11 &cpu2intctrl 9
262 &cpu3intctrl 11 &cpu3intctrl 9
263 &cpu4intctrl 11 &cpu4intctrl 9>;
264 interrupt-controller;
265 #interrupt-cells = <1>;
266 riscv,max-priority = <7>;
270 clkgen: clock-controller {
271 compatible = "starfive,jh7110-clkgen";
272 reg = <0x0 0x13020000 0x0 0x10000>,
273 <0x0 0x10230000 0x0 0x10000>,
274 <0x0 0x17000000 0x0 0x10000>;
275 reg-names = "sys", "stg", "aon";
276 clocks = <&osc>, <&gmac1_rmii_refin>,
278 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
279 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
280 <&tdm_ext>, <&mclk_ext>,
281 <&jtag_tck_inner>, <&bist_apb>,
282 <&stg_apb>, <&clk_rtc>,
283 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
284 clock-names = "osc", "gmac1_rmii_refin",
286 "i2stx_bclk_ext", "i2stx_lrck_ext",
287 "i2srx_bclk_ext", "i2srx_lrck_ext",
288 "tdm_ext", "mclk_ext",
289 "jtag_tck_inner", "bist_apb",
290 "stg_apb", "clk_rtc",
291 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
293 starfive,sys-syscon = <&sys_syscon 0x18 0x1c
294 0x20 0x24 0x28 0x2c 0x30 0x34>;
298 clkvout: clock-controller@295C0000 {
299 compatible = "starfive,jh7110-clk-vout";
300 reg = <0x0 0x295C0000 0x0 0x10000>;
302 clocks = <&hdmitx0_pixelclk>,
303 <&mipitx_dphy_rxesc>,
304 <&mipitx_dphy_txbytehs>,
305 <&clkgen JH7110_VOUT_SRC>,
306 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
307 clock-names = "hdmitx0_pixelclk",
309 "mipitx_dphy_txbytehs",
312 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
313 reset-names = "vout_src";
315 power-domains = <&pwrc JH7110_PD_VOUT>;
319 clkisp: clock-controller@19810000 {
320 compatible = "starfive,jh7110-clk-isp";
321 reg = <0x0 0x19810000 0x0 0x10000>;
324 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
325 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
326 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
327 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
328 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
329 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
330 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
331 "u0_sft7110_noc_bus_clk_isp_axi";
332 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
333 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
334 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
335 reset-names = "rst_isp_top_n", "rst_isp_top_axi",
337 power-domains = <&pwrc JH7110_PD_ISP>;
342 compatible = "cdns,qspi-nor";
343 #address-cells = <1>;
345 reg = <0x0 0x13010000 0x0 0x10000
346 0x0 0x21000000 0x0 0x400000>;
347 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
348 clock-names = "clk_ref";
349 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
350 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
351 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
352 resets-names = "rst_apb", "rst_ahb", "rst_ref";
353 cdns,fifo-depth = <256>;
354 cdns,fifo-width = <4>;
355 spi-max-frequency = <250000000>;
357 nor_flash: nor-flash@0 {
358 compatible = "jedec,spi-nor";
360 spi-max-frequency = <100000000>;
369 compatible = "starfive,jh7110-otp";
370 reg = <0x0 0x17050000 0x0 0x10000>;
371 clock-frequency = <4000000>;
372 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
377 compatible = "starfive,jh7110-cdns3";
378 reg = <0x0 0x10210000 0x0 0x1000>;
379 clocks = <&clkgen JH7110_USB_125M>,
380 <&clkgen JH7110_USB0_CLK_APP_125>,
381 <&clkgen JH7110_USB0_CLK_LPM>,
382 <&clkgen JH7110_USB0_CLK_STB>,
383 <&clkgen JH7110_USB0_CLK_USB_APB>,
384 <&clkgen JH7110_USB0_CLK_AXI>,
385 <&clkgen JH7110_USB0_CLK_UTMI_APB>,
386 <&clkgen JH7110_PCIE0_CLK_APB>;
387 clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
388 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
389 <&rstgen RSTN_U0_CDN_USB_APB>,
390 <&rstgen RSTN_U0_CDN_USB_AXI>,
391 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
392 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
393 reset-names = "pwrup","apb","axi","utmi", "phy";
394 starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
395 starfive,sys-syscon = <&sys_syscon 0x18>;
397 #address-cells = <2>;
399 #interrupt-cells = <1>;
401 usbdrd_cdns3: usb@10100000 {
402 compatible = "cdns,usb3";
403 reg = <0x0 0x10100000 0x0 0x10000>,
404 <0x0 0x10110000 0x0 0x10000>,
405 <0x0 0x10120000 0x0 0x10000>;
406 reg-names = "otg", "xhci", "dev";
407 interrupts = <100>, <109>, <110>;
408 interrupt-names = "host", "peripheral", "otg";
409 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
410 maximum-speed = "super-speed";
414 timer: timer@13050000 {
415 compatible = "starfive,timers";
416 reg = <0x0 0x13050000 0x0 0x10000>;
417 interrupts = <69>, <70>, <71> ,<72>;
418 interrupt-names = "timer0", "timer1",
420 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
421 <&clkgen JH7110_TIMER_CLK_TIMER1>,
422 <&clkgen JH7110_TIMER_CLK_TIMER2>,
423 <&clkgen JH7110_TIMER_CLK_TIMER3>,
424 <&clkgen JH7110_TIMER_CLK_APB>;
425 clock-names = "timer0", "timer1",
426 "timer2", "timer3", "apb_clk";
427 resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
428 <&rstgen RSTN_U0_TIMER_TIMER1>,
429 <&rstgen RSTN_U0_TIMER_TIMER2>,
430 <&rstgen RSTN_U0_TIMER_TIMER3>,
431 <&rstgen RSTN_U0_TIMER_APB>;
432 reset-names = "timer0", "timer1",
433 "timer2", "timer3", "apb_rst";
434 clock-frequency = <24000000>;
438 wdog: wdog@13070000 {
439 compatible = "starfive,dskit-wdt";
440 reg = <0x0 0x13070000 0x0 0x10000>;
442 interrupt-names = "wdog";
443 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
444 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
445 clock-names = "core_clk", "apb_clk";
446 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
447 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
448 reset-names = "rst_apb", "rst_core";
454 compatible = "starfive,rtc_hms";
455 reg = <0x0 0x17040000 0x0 0x10000>;
456 interrupts = <10>, <11>, <12>;
457 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
458 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
459 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
460 clock-names = "pclk", "cal_clk";
461 resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
462 <&rstgen RSTN_U0_RTC_HMS_CAL>,
463 <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
464 reset-names = "rst_apb", "rst_cal", "rst_osc";
465 rtc,cal-clock-freq = <1000000>;
469 pwrc: power-controller@17030000 {
470 compatible = "starfive,jh7110-pmu";
471 reg = <0x0 0x17030000 0x0 0x10000>;
473 #power-domain-cells = <1>;
477 uart0: serial@10000000 {
478 compatible = "snps,dw-apb-uart";
479 reg = <0x0 0x10000000 0x0 0x10000>;
482 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
483 <&clkgen JH7110_UART0_CLK_APB>;
484 clock-names = "baudclk", "apb_pclk";
485 resets = <&rstgen RSTN_U0_DW_UART_APB>,
486 <&rstgen RSTN_U0_DW_UART_CORE>;
491 uart1: serial@10010000 {
492 compatible = "snps,dw-apb-uart";
493 reg = <0x0 0x10010000 0x0 0x10000>;
496 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
497 <&clkgen JH7110_UART1_CLK_APB>;
498 clock-names = "baudclk", "apb_pclk";
499 resets = <&rstgen RSTN_U1_DW_UART_APB>,
500 <&rstgen RSTN_U1_DW_UART_CORE>;
505 uart2: serial@10020000 {
506 compatible = "snps,dw-apb-uart";
507 reg = <0x0 0x10020000 0x0 0x10000>;
510 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
511 <&clkgen JH7110_UART2_CLK_APB>;
512 clock-names = "baudclk", "apb_pclk";
513 resets = <&rstgen RSTN_U2_DW_UART_APB>,
514 <&rstgen RSTN_U2_DW_UART_CORE>;
519 uart3: serial@12000000 {
520 compatible = "snps,dw-apb-uart";
521 reg = <0x0 0x12000000 0x0 0x10000>;
524 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
525 <&clkgen JH7110_UART3_CLK_APB>;
526 clock-names = "baudclk", "apb_pclk";
527 resets = <&rstgen RSTN_U3_DW_UART_APB>,
528 <&rstgen RSTN_U3_DW_UART_CORE>;
533 uart4: serial@12010000 {
534 compatible = "snps,dw-apb-uart";
535 reg = <0x0 0x12010000 0x0 0x10000>;
538 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
539 <&clkgen JH7110_UART4_CLK_APB>;
540 clock-names = "baudclk", "apb_pclk";
541 resets = <&rstgen RSTN_U4_DW_UART_APB>,
542 <&rstgen RSTN_U4_DW_UART_CORE>;
547 uart5: serial@12020000 {
548 compatible = "snps,dw-apb-uart";
549 reg = <0x0 0x12020000 0x0 0x10000>;
552 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
553 <&clkgen JH7110_UART5_CLK_APB>;
554 clock-names = "baudclk", "apb_pclk";
555 resets = <&rstgen RSTN_U5_DW_UART_APB>,
556 <&rstgen RSTN_U5_DW_UART_CORE>;
561 dma: dma-controller@16050000 {
562 compatible = "starfive,axi-dma";
563 reg = <0x0 0x16050000 0x0 0x10000>;
564 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
565 <&clkgen JH7110_DMA1P_CLK_AHB>;
566 clock-names = "core-clk", "cfgr-clk";
567 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
568 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
569 reset-names = "rst_axi", "rst_ahb";
573 snps,dma-masters = <1>;
574 snps,data-width = <3>;
575 snps,num-hs-if = <56>;
576 snps,block-size = <65536 65536 65536 65536>;
577 snps,priority = <0 1 2 3>;
578 snps,axi-max-burst-len = <16>;
582 gpio: gpio@13040000 {
583 compatible = "starfive,jh7110-sys-pinctrl";
584 reg = <0x0 0x13040000 0x0 0x10000>;
585 reg-names = "control";
586 clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
587 resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
589 interrupt-controller;
595 gpioa: gpio@17020000 {
596 compatible = "starfive,jh7110-aon-pinctrl";
597 reg = <0x0 0x17020000 0x0 0x10000>;
598 reg-names = "control";
599 resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
601 interrupt-controller;
607 sfctemp: tmon@120e0000 {
608 compatible = "starfive,jh7110-temp";
609 reg = <0x0 0x120e0000 0x0 0x10000>;
611 clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
612 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
613 clock-names = "sense", "bus";
614 resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
615 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
616 reset-names = "sense", "bus";
617 #thermal-sensor-cells = <0>;
623 polling-delay-passive = <250>;
624 polling-delay = <15000>;
626 thermal-sensors = <&sfctemp>;
632 cpu_alert0: cpu_alert0 {
634 temperature = <75000>;
641 temperature = <90000>;
649 trng: trng@1600C000 {
650 compatible = "starfive,trng";
651 reg = <0x0 0x1600C000 0x0 0x4000>;
652 clocks = <&clkgen JH7110_SEC_HCLK>,
653 <&clkgen JH7110_SEC_MISCAHB_CLK>;
654 clock-names = "hclk", "miscahb_clk";
655 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
660 sec_dma: sec_dma@16008000 {
661 /*compatible = "arm,pl080", "arm,primecell";*/
662 compatible = "starfive,pl080";
663 reg = <0x0 0x16008000 0x0 0x4000>;
664 reg-names = "sec_dma";
666 clocks = <&clkgen JH7110_SEC_HCLK>,
667 <&clkgen JH7110_SEC_MISCAHB_CLK>;
668 clock-names = "sec_hclk","sec_ahb";
669 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
670 reset-names = "sec_hre";
671 lli-bus-interface-ahb1;
672 mem-bus-interface-ahb1;
673 memcpy-burst-size = <256>;
674 memcpy-bus-width = <32>;
679 crypto: crypto@16000000 {
680 compatible = "starfive,jh7110-sec";
681 reg = <0x0 0x16000000 0x0 0x4000>,
682 <0x0 0x16008000 0x0 0x4000>;
683 reg-names = "secreg","secdma";
684 interrupts = <28>, <29>;
685 interrupt-names = "secirq", "dmairq";
686 clocks = <&clkgen JH7110_SEC_HCLK>,
687 <&clkgen JH7110_SEC_MISCAHB_CLK>;
688 clock-names = "sec_hclk","sec_ahb";
689 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
690 reset-names = "sec_hre";
691 enable-side-channel-mitigation = "true";
693 dmas = <&sec_dma 1 2>,
695 dma-names = "sec_m","sec_p";
700 compatible = "snps,designware-i2c";
701 reg = <0x0 0x10030000 0x0 0x10000>;
702 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
703 <&clkgen JH7110_I2C0_CLK_APB>;
704 clock-names = "ref", "pclk";
705 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
707 #address-cells = <1>;
713 compatible = "snps,designware-i2c";
714 reg = <0x0 0x10040000 0x0 0x10000>;
715 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
716 <&clkgen JH7110_I2C1_CLK_APB>;
717 clock-names = "ref", "pclk";
718 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
720 #address-cells = <1>;
726 compatible = "snps,designware-i2c";
727 reg = <0x0 0x10050000 0x0 0x10000>;
728 clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
729 <&clkgen JH7110_I2C2_CLK_APB>;
730 clock-names = "ref", "pclk";
731 resets = <&rstgen RSTN_U2_DW_I2C_APB>;
733 #address-cells = <1>;
739 compatible = "snps,designware-i2c";
740 reg = <0x0 0x12030000 0x0 0x10000>;
741 clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
742 <&clkgen JH7110_I2C3_CLK_APB>;
743 clock-names = "ref", "pclk";
744 resets = <&rstgen RSTN_U3_DW_I2C_APB>;
746 #address-cells = <1>;
752 compatible = "snps,designware-i2c";
753 reg = <0x0 0x12040000 0x0 0x10000>;
754 clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
755 <&clkgen JH7110_I2C4_CLK_APB>;
756 clock-names = "ref", "pclk";
757 resets = <&rstgen RSTN_U4_DW_I2C_APB>;
759 #address-cells = <1>;
765 compatible = "snps,designware-i2c";
766 reg = <0x0 0x12050000 0x0 0x10000>;
767 clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
768 <&clkgen JH7110_I2C5_CLK_APB>;
769 clock-names = "ref", "pclk";
770 resets = <&rstgen RSTN_U5_DW_I2C_APB>;
772 #address-cells = <1>;
778 compatible = "snps,designware-i2c";
779 reg = <0x0 0x12060000 0x0 0x10000>;
780 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
781 <&clkgen JH7110_I2C6_CLK_APB>;
782 clock-names = "ref", "pclk";
783 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
785 #address-cells = <1>;
790 /* unremovable emmc as mmcblk0 */
791 sdio0: sdio0@16010000 {
792 compatible = "snps,dw-mshc";
793 reg = <0x0 0x16010000 0x0 0x10000>;
794 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
795 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
796 clock-names = "biu","ciu";
797 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
798 reset-names = "reset";
801 fifo-watermark-aligned;
806 sdio1: sdio1@16020000 {
807 compatible = "snps,dw-mshc";
808 reg = <0x0 0x16020000 0x0 0x10000>;
809 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
810 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
811 clock-names = "biu","ciu";
812 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
813 reset-names = "reset";
816 fifo-watermark-aligned;
821 vin_sysctl: vin_sysctl@19800000 {
822 compatible = "starfive,stf-vin";
823 reg = <0x0 0x19800000 0x0 0x10000>,
824 <0x0 0x19810000 0x0 0x10000>,
825 <0x0 0x19820000 0x0 0x10000>,
826 <0x0 0x19840000 0x0 0x10000>,
827 <0x0 0x19870000 0x0 0x30000>,
828 <0x0 0x11840000 0x0 0x10000>,
829 <0x0 0x17030000 0x0 0x10000>,
830 <0x0 0x13020000 0x0 0x10000>;
831 reg-names = "csi2rx", "vclk", "vrst", "sctrl",
832 "isp", "trst", "pmu", "syscrg";
833 clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
834 <&clkisp JH7110_U0_VIN_PCLK>,
835 <&clkisp JH7110_U0_VIN_SYS_CLK>,
836 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
837 <&clkisp JH7110_DVP_INV>,
838 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
839 <&clkisp JH7110_MIPI_RX0_PXL>,
840 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
841 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
842 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
843 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
844 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
845 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
846 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
847 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
848 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
849 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
850 clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
851 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
852 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
853 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
854 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
855 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
856 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
857 resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
858 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
859 <&rstgen RSTN_U0_VIN_N_PCLK>,
860 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
861 <&rstgen RSTN_U0_VIN_P_AXIRD>,
862 <&rstgen RSTN_U0_VIN_P_AXIWR>,
863 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
864 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
865 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
866 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
867 <&rstgen RSTN_U0_M31DPHY_HW>,
868 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
869 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
870 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
871 reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
872 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
873 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
874 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
875 "rst_isp_top_n", "rst_isp_top_axi";
876 starfive,aon-syscon = <&aon_syscon 0x00>;
877 power-domains = <&pwrc JH7110_PD_ISP>;
878 /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
879 interrupts = <92 87 88 89 90>;
884 compatible = "starfive,jpu";
885 reg = <0x0 0x13090000 0x0 0x300>;
887 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
888 <&clkgen JH7110_CODAJ12_CLK_CORE>,
889 <&clkgen JH7110_CODAJ12_CLK_APB>,
890 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
891 clock-names = "axi_clk", "core_clk",
892 "apb_clk", "noc_bus";
893 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
894 <&rstgen RSTN_U0_CODAJ12_CORE>,
895 <&rstgen RSTN_U0_CODAJ12_APB>;
896 reset-names = "rst_axi", "rst_core", "rst_apb";
897 power-domains = <&pwrc JH7110_PD_VDEC>;
901 vpu_dec: vpu_dec@130A0000 {
902 compatible = "starfive,vdec";
903 reg = <0x0 0x130A0000 0x0 0x10000>;
905 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
906 <&clkgen JH7110_WAVE511_CLK_BPU>,
907 <&clkgen JH7110_WAVE511_CLK_VCE>,
908 <&clkgen JH7110_WAVE511_CLK_APB>,
909 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
910 clock-names = "axi_clk", "bpu_clk", "vce_clk",
911 "apb_clk", "noc_bus";
912 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
913 <&rstgen RSTN_U0_WAVE511_BPU>,
914 <&rstgen RSTN_U0_WAVE511_VCE>,
915 <&rstgen RSTN_U0_WAVE511_APB>,
916 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
917 reset-names = "rst_axi", "rst_bpu", "rst_vce",
918 "rst_apb", "rst_sram";
919 starfive,vdec_noc_ctrl;
920 power-domains = <&pwrc JH7110_PD_VDEC>;
924 vpu_enc: vpu_enc@130B0000 {
925 compatible = "starfive,venc";
926 reg = <0x0 0x130B0000 0x0 0x10000>;
928 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
929 <&clkgen JH7110_WAVE420L_CLK_BPU>,
930 <&clkgen JH7110_WAVE420L_CLK_VCE>,
931 <&clkgen JH7110_WAVE420L_CLK_APB>,
932 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
933 clock-names = "axi_clk", "bpu_clk", "vce_clk",
934 "apb_clk", "noc_bus";
935 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
936 <&rstgen RSTN_U0_WAVE420L_BPU>,
937 <&rstgen RSTN_U0_WAVE420L_VCE>,
938 <&rstgen RSTN_U0_WAVE420L_APB>,
939 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
940 reset-names = "rst_axi", "rst_bpu", "rst_vce",
941 "rst_apb", "rst_sram";
942 starfive,venc_noc_ctrl;
943 power-domains = <&pwrc JH7110_PD_VENC>;
947 rstgen: reset-controller {
948 compatible = "starfive,jh7110-reset";
949 reg = <0x0 0x13020000 0x0 0x10000>,
950 <0x0 0x10230000 0x0 0x10000>,
951 <0x0 0x17000000 0x0 0x10000>,
952 <0x0 0x19810000 0x0 0x10000>,
953 <0x0 0x295C0000 0x0 0x10000>;
954 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
959 stmmac_axi_setup: stmmac-axi-config {
960 snps,wr_osr_lmt = <0xf>;
961 snps,rd_osr_lmt = <0xf>;
962 snps,blen = <256 128 64 32 0 0 0>;
965 gmac0: ethernet@16030000 {
966 compatible = "starfive,jh7110-eqos-5.20";
967 reg = <0x0 0x16030000 0x0 0x10000>;
974 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
975 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
976 <&clkgen JH7110_GMAC0_PTP>,
977 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
978 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
979 <&clkgen JH7110_GMAC0_GTXC>;
980 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
981 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
982 reset-names = "ahb", "stmmaceth";
983 interrupts = <7>, <6>, <5> ;
984 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
985 max-frame-size = <9000>;
986 phy-mode = "rgmii-id";
987 snps,multicast-filter-bins = <64>;
988 snps,perfect-filter-entries = <128>;
989 rx-fifo-depth = <2048>;
990 tx-fifo-depth = <2048>;
993 snps,force_thresh_dma_mode;
994 snps,axi-config = <&stmmac_axi_setup>;
996 snps,en-tx-lpi-clockgating;
998 snps,write-requests = <4>;
999 snps,read-requests = <4>;
1000 snps,burst-map = <0x7>;
1003 status = "disabled";
1006 gmac1: ethernet@16040000 {
1007 compatible = "starfive,jh7110-eqos-5.20";
1008 reg = <0x0 0x16040000 0x0 0x10000>;
1009 clock-names = "gtx",
1015 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1016 <&clkgen JH7110_GMAC5_CLK_TX>,
1017 <&clkgen JH7110_GMAC5_CLK_PTP>,
1018 <&clkgen JH7110_GMAC5_CLK_AHB>,
1019 <&clkgen JH7110_GMAC5_CLK_AXI>,
1020 <&clkgen JH7110_GMAC1_GTXC>;
1021 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1022 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1023 reset-names = "ahb", "stmmaceth";
1024 interrupts = <78>, <77>, <76> ;
1025 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1026 max-frame-size = <9000>;
1027 phy-mode = "rgmii-id";
1028 snps,multicast-filter-bins = <64>;
1029 snps,perfect-filter-entries = <128>;
1030 rx-fifo-depth = <2048>;
1031 tx-fifo-depth = <2048>;
1034 snps,force_thresh_dma_mode;
1035 snps,axi-config = <&stmmac_axi_setup>;
1037 snps,en-tx-lpi-clockgating;
1039 snps,write-requests = <4>;
1040 snps,read-requests = <4>;
1041 snps,burst-map = <0x7>;
1044 status = "disabled";
1048 compatible = "img-gpu";
1049 reg = <0x0 0x18000000 0x0 0x100000>,
1050 <0x0 0x130C000 0x0 0x10000>;
1051 clocks = <&clkgen JH7110_GPU_CLK_APB>,
1052 <&clkgen JH7110_GPU_RTC_TOGGLE>,
1053 <&clkgen JH7110_GPU_CORE_CLK>,
1054 <&clkgen JH7110_GPU_SYS_CLK>,
1055 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1056 clock-names = "clk_apb", "clk_rtc", "clk_core",
1057 "clk_sys", "clk_axi";
1058 resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1059 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1060 reset-names = "rst_apb", "rst_doma";
1061 power-domains = <&pwrc JH7110_PD_GPUA>;
1063 current-clock = <8000000>;
1064 status = "disabled";
1067 can0: can@130d0000 {
1068 compatible = "ipms,can";
1069 reg = <0x0 0x130d0000 0x0 0x1000>;
1071 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1072 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1073 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1074 clock-names = "apb_clk", "core_clk", "timer_clk";
1075 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1076 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1077 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1078 reset-names = "rst_apb", "rst_core", "rst_timer";
1079 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1080 syscon,can_or_canfd = <0>;
1081 status = "disabled";
1084 can1: can@130e0000 {
1085 compatible = "ipms,can";
1086 reg = <0x0 0x130e0000 0x0 0x1000>;
1088 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1089 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1090 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1091 clock-names = "apb_clk", "core_clk", "timer_clk";
1092 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1093 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1094 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1095 reset-names = "rst_apb", "rst_core", "rst_timer";
1096 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1097 syscon,can_or_canfd = <0>;
1098 status = "disabled";
1102 compatible = "starfive,sf-tdm";
1103 reg = <0x0 0x10090000 0x0 0x1000>;
1105 clocks = <&clkgen JH7110_AHB0>,
1106 <&clkgen JH7110_TDM_CLK_AHB>,
1107 <&clkgen JH7110_APB0>,
1108 <&clkgen JH7110_TDM_CLK_APB>,
1109 <&clkgen JH7110_TDM_INTERNAL>,
1111 <&clkgen JH7110_TDM_CLK_TDM>,
1112 <&clkgen JH7110_MCLK_INNER>;
1113 clock-names = "clk_ahb0", "clk_tdm_ahb",
1114 "clk_apb0", "clk_tdm_apb",
1115 "clk_tdm_internal", "clk_tdm_ext",
1116 "clk_tdm", "mclk_inner";
1117 resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1118 <&rstgen RSTN_U0_TDM16SLOT_APB>,
1119 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1120 reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1121 dmas = <&dma 20 1>, <&dma 21 1>;
1122 dma-names = "rx","tx";
1123 #sound-dai-cells = <0>;
1124 status = "disabled";
1127 spdif0: spdif0@100a0000 {
1128 compatible = "starfive,sf-spdif";
1129 reg = <0x0 0x100a0000 0x0 0x1000>;
1130 clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1131 <&clkgen JH7110_SPDIF_CLK_CORE>,
1132 <&clkgen JH7110_APB0>,
1133 <&clkgen JH7110_AUDIO_ROOT>,
1134 <&clkgen JH7110_MCLK_INNER>;
1135 clock-names = "spdif-apb", "spdif-core", "apb0",
1136 "audroot", "mclk_inner";
1137 resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1138 reset-names = "rst_apb";
1140 interrupt-names = "tx";
1141 #sound-dai-cells = <0>;
1142 status = "disabled";
1145 pwmdac: pwmdac@100b0000 {
1146 compatible = "starfive,pwmdac";
1147 reg = <0x0 0x100b0000 0x0 0x1000>;
1148 clocks = <&clkgen JH7110_APB0>,
1149 <&clkgen JH7110_PWMDAC_CLK_APB>,
1150 <&clkgen JH7110_PWMDAC_CLK_CORE>;
1151 clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1152 resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1153 reset-names = "rst-apb";
1156 #sound-dai-cells = <0>;
1157 status = "disabled";
1160 i2stx: i2stx@100c0000 {
1161 compatible = "snps,designware-i2stx";
1162 reg = <0x0 0x100c0000 0x0 0x1000>;
1163 interrupt-names = "tx";
1164 #sound-dai-cells = <0>;
1167 status = "disabled";
1171 compatible = "starfive,sf-pdm";
1172 reg = <0x0 0x100d0000 0x0 0x1000>;
1174 clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1175 <&clkgen JH7110_APB0>,
1176 <&clkgen JH7110_PDM_CLK_APB>,
1177 <&clkgen JH7110_MCLK_INNER>,
1178 <&clkgen JH7110_MCLK>,
1179 <&clkgen JH7110_MCLK_OUT>;
1180 clock-names = "pdm_mclk", "clk_apb0",
1181 "pdm_apb", "mclk_inner",
1182 "clk_mclk", "mclk_out";
1183 resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1184 <&rstgen RSTN_U0_PDM_4MIC_APB>;
1185 reset-names = "pdm_dmic", "pdm_apb";
1186 #sound-dai-cells = <0>;
1189 i2srx_mst: i2srx_mst@100e0000 {
1190 compatible = "snps,i2srx-master";
1191 reg = <0x0 0x100e0000 0x0 0x1000>;
1192 clocks = <&clkgen JH7110_APB0>,
1193 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1194 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1195 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1196 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1197 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1198 clock-names = "apb0", "i2srx_apb",
1199 "i2srx_bclk_mst", "i2srx_lrck_mst",
1200 "i2srx_bclk", "i2srx_lrck";
1201 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1202 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1203 reset-names = "rst_apb_rx", "rst_bclk_rx";
1206 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1207 #sound-dai-cells = <0>;
1208 status = "disabled";
1211 i2srx_3ch: i2srx_3ch@100e0000 {
1212 compatible = "snps,designware-i2srx";
1213 reg = <0x0 0x100e0000 0x0 0x1000>;
1214 clocks = <&clkgen JH7110_APB0>,
1215 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1216 <&clkgen JH7110_AUDIO_ROOT>,
1217 <&clkgen JH7110_MCLK_INNER>,
1218 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1219 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1220 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1221 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1222 clock-names = "apb0", "3ch-apb",
1223 "audioroot", "mclk-inner",
1224 "bclk_mst", "3ch-lrck",
1225 "rx-bclk", "rx-lrck";
1226 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1227 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1228 reset-names = "rst_apb_rx", "rst_bclk_rx";
1231 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1232 #sound-dai-cells = <0>;
1233 status = "disabled";
1236 i2stx_4ch0: i2stx_4ch0@120b0000 {
1237 compatible = "snps,designware-i2stx-4ch0";
1238 reg = <0x0 0x120b0000 0x0 0x1000>;
1239 clocks = <&clkgen JH7110_MCLK_INNER>,
1240 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1241 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1242 <&clkgen JH7110_MCLK>,
1243 <&clkgen JH7110_I2STX0_4CHBCLK>,
1244 <&clkgen JH7110_I2STX0_4CHLRCK>;
1245 clock-names = "inner", "bclk-mst",
1248 resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1249 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1250 reset-names = "rst_apb0", "rst_bclk0";
1253 #sound-dai-cells = <0>;
1254 status = "disabled";
1257 i2stx_4ch1: i2stx_4ch1@120c0000 {
1258 compatible = "snps,designware-i2stx-4ch1";
1259 reg = <0x0 0x120c0000 0x0 0x1000>;
1260 clocks = <&clkgen JH7110_AUDIO_ROOT>,
1261 <&clkgen JH7110_MCLK_INNER>,
1262 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1263 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1264 <&clkgen JH7110_MCLK>,
1265 <&clkgen JH7110_I2STX1_4CHBCLK>,
1266 <&clkgen JH7110_I2STX1_4CHLRCK>,
1267 <&clkgen JH7110_MCLK_OUT>,
1268 <&clkgen JH7110_APB0>,
1269 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1273 clock-names = "audroot", "mclk_inner", "bclk_mst",
1274 "lrck_mst", "mclk", "4chbclk",
1275 "4chlrck", "mclk_out",
1277 "mclk_ext", "bclk_ext", "lrck_ext";
1279 resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1280 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1281 reset-names = "rst_apb1", "rst_bclk1";
1284 #sound-dai-cells = <0>;
1285 status = "disabled";
1289 compatible = "starfive,pwm";
1290 reg = <0x0 0x120d0000 0x0 0x10000>;
1291 reg-names = "control";
1292 clocks = <&clkgen JH7110_PWM_CLK_APB>;
1293 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1294 starfive,approx-freq = <2000000>;
1296 starfive,npwm = <8>;
1297 status = "disabled";
1300 spdif_transmitter: spdif_transmitter {
1301 compatible = "linux,spdif-dit";
1302 #sound-dai-cells = <0>;
1303 status = "disabled";
1306 spdif_receiver: spdif_receiver {
1307 compatible = "linux,spdif-dir";
1308 #sound-dai-cells = <0>;
1309 status = "disabled";
1312 pwmdac_codec: pwmdac-transmitter {
1313 compatible = "linux,pwmdac-dit";
1314 #sound-dai-cells = <0>;
1315 status = "disabled";
1318 dmic_codec: dmic_codec {
1319 compatible = "dmic-codec";
1320 #sound-dai-cells = <0>;
1321 status = "disabled";
1324 spi0: spi@10060000 {
1325 compatible = "arm,pl022", "arm,primecell";
1326 reg = <0x0 0x10060000 0x0 0x10000>;
1327 clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1328 clock-names = "apb_pclk";
1329 resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1330 reset-names = "rst_apb";
1332 /* shortage of dma channel that not be used */
1333 /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1334 /*dma-names = "rx","tx";*/
1335 arm,primecell-periphid = <0x00041022>;
1337 #address-cells = <1>;
1339 status = "disabled";
1342 spi1: spi@10070000 {
1343 compatible = "arm,pl022", "arm,primecell";
1344 reg = <0x0 0x10070000 0x0 0x10000>;
1345 clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1346 clock-names = "apb_pclk";
1347 resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1348 reset-names = "rst_apb";
1350 /* shortage of dma channel that not be used */
1351 /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1352 /*dma-names = "rx","tx";*/
1353 arm,primecell-periphid = <0x00041022>;
1355 #address-cells = <1>;
1357 status = "disabled";
1360 spi2: spi@10080000 {
1361 compatible = "arm,pl022", "arm,primecell";
1362 reg = <0x0 0x10080000 0x0 0x10000>;
1363 clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1364 clock-names = "apb_pclk";
1365 resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1366 reset-names = "rst_apb";
1368 /* shortage of dma channel that not be used */
1369 /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1370 /*dma-names = "rx","tx";*/
1371 arm,primecell-periphid = <0x00041022>;
1373 #address-cells = <1>;
1375 status = "disabled";
1378 spi3: spi@12070000 {
1379 compatible = "arm,pl022", "arm,primecell";
1380 reg = <0x0 0x12070000 0x0 0x10000>;
1381 clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1382 clock-names = "apb_pclk";
1383 resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1384 reset-names = "rst_apb";
1386 /* shortage of dma channel that not be used */
1387 /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1388 /*dma-names = "rx","tx";*/
1389 arm,primecell-periphid = <0x00041022>;
1391 #address-cells = <1>;
1393 status = "disabled";
1396 spi4: spi@12080000 {
1397 compatible = "arm,pl022", "arm,primecell";
1398 reg = <0x0 0x12080000 0x0 0x10000>;
1399 clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1400 clock-names = "apb_pclk";
1401 resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1402 reset-names = "rst_apb";
1404 /* shortage of dma channel that not be used */
1405 /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1406 /*dma-names = "rx","tx";*/
1407 arm,primecell-periphid = <0x00041022>;
1409 #address-cells = <1>;
1411 status = "disabled";
1414 spi5: spi@12090000 {
1415 compatible = "arm,pl022", "arm,primecell";
1416 reg = <0x0 0x12090000 0x0 0x10000>;
1417 clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1418 clock-names = "apb_pclk";
1419 resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1420 reset-names = "rst_apb";
1422 /* shortage of dma channel that not be used */
1423 /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1424 /*dma-names = "rx","tx";*/
1425 arm,primecell-periphid = <0x00041022>;
1427 #address-cells = <1>;
1429 status = "disabled";
1432 spi6: spi@120A0000 {
1433 compatible = "arm,pl022", "arm,primecell";
1434 reg = <0x0 0x120A0000 0x0 0x10000>;
1435 clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1436 clock-names = "apb_pclk";
1437 resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1438 reset-names = "rst_apb";
1440 /* shortage of dma channel that not be used */
1441 /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1442 /*dma-names = "rx","tx";*/
1443 arm,primecell-periphid = <0x00041022>;
1445 #address-cells = <1>;
1447 status = "disabled";
1450 pcie0: pcie@2B000000 {
1451 compatible = "plda,pci-xpressrich3-axi";
1452 #address-cells = <3>;
1454 #interrupt-cells = <1>;
1455 reg = <0x0 0x2B000000 0x0 0x1000000
1456 0x9 0x40000000 0x0 0x10000000>;
1457 reg-names = "reg", "config";
1458 device_type = "pci";
1459 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1460 bus-range = <0x0 0xff>;
1461 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>;
1462 msi-parent = <&plic>;
1464 interrupt-controller;
1465 interrupt-names = "msi";
1466 interrupt-parent = <&plic>;
1467 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1468 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1469 <0x0 0x0 0x0 0x2 &plic 0x2>,
1470 <0x0 0x0 0x0 0x3 &plic 0x3>,
1471 <0x0 0x0 0x0 0x4 &plic 0x4>;
1472 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1473 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1474 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1475 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1476 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1477 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1478 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1479 "rst_brg", "rst_core", "rst_apb";
1480 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1481 <&clkgen JH7110_PCIE0_CLK_TL>,
1482 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1483 <&clkgen JH7110_PCIE0_CLK_APB>;
1484 clock-names = "noc", "tl", "axi_mst0", "apb";
1485 status = "disabled";
1488 pcie1: pcie@2C000000 {
1489 compatible = "plda,pci-xpressrich3-axi";
1490 #address-cells = <3>;
1492 #interrupt-cells = <1>;
1493 reg = <0x0 0x2C000000 0x0 0x1000000
1494 0x9 0xc0000000 0x0 0x10000000>;
1495 reg-names = "reg", "config";
1496 device_type = "pci";
1497 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1498 bus-range = <0x0 0xff>;
1499 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>;
1500 msi-parent = <&plic>;
1502 interrupt-controller;
1503 interrupt-names = "msi";
1504 interrupt-parent = <&plic>;
1505 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1506 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1507 <0x0 0x0 0x0 0x2 &plic 0x2>,
1508 <0x0 0x0 0x0 0x3 &plic 0x3>,
1509 <0x0 0x0 0x0 0x4 &plic 0x4>;
1510 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1511 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1512 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1513 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1514 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1515 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1516 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1517 "rst_brg", "rst_core", "rst_apb";
1518 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1519 <&clkgen JH7110_PCIE1_CLK_TL>,
1520 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1521 <&clkgen JH7110_PCIE1_CLK_APB>;
1522 clock-names = "noc", "tl", "axi_mst0", "apb";
1523 status = "disabled";
1526 mailbox_contrl0: mailbox@0 {
1527 compatible = "starfive,mail_box";
1528 reg = <0x0 0x13060000 0x0 0x0001000>;
1529 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1530 clock-names = "clk_apb";
1531 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1532 reset-names = "mbx_rre";
1533 interrupts = <26 27>;
1535 status = "disabled";
1538 mailbox_client0: mailbox_client@0 {
1539 compatible = "starfive,mailbox-test";
1540 mbox-names = "rx", "tx";
1541 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1542 status = "disabled";
1545 display: display-subsystem {
1546 compatible = "verisilicon,display-subsystem";
1547 ports = <&dc_out_dpi0>;
1548 status = "disabled";
1551 dssctrl: dssctrl@295B0000 {
1552 compatible = "verisilicon,dss-ctrl", "syscon";
1553 reg = <0 0x295B0000 0 0x90>;
1556 tda988x_pin: tda988x_pin {
1557 compatible = "starfive,tda998x_rgb_pin";
1558 status = "disabled";
1561 hdmi_output: hdmi-output {
1562 compatible = "verisilicon,hdmi-encoder";
1563 //verisilicon,dss-syscon = <&dssctrl>;
1564 //verisilicon,mux-mask = <0x70 0x380>;
1565 //verisilicon,mux-val = <0x40 0x280>;
1566 status = "disabled";
1569 dc8200: dc8200@29400000 {
1570 compatible = "verisilicon,dc8200";
1571 verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1572 reg = <0x0 0x29400000 0x0 0x100>,
1573 <0x0 0x29400800 0x0 0x2000>,
1574 <0x0 0x17030000 0x0 0x1000>;
1576 status = "disabled";
1577 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1578 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1579 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1580 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1581 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1582 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1583 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1584 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1585 <&clkgen JH7110_VOUT_SRC>,
1586 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1587 <&clkgen JH7110_AHB1>,
1588 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1589 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1590 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1591 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1592 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1593 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1594 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1595 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1596 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1597 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1598 <&hdmitx0_pixelclk>,
1599 <&clkvout JH7110_DC8200_PIX0>,
1600 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1601 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1602 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1603 "noc_disp","noc_isp","noc_stg","vout_src",
1604 "top_vout_axi","ahb1","top_vout_ahb",
1605 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1606 "axi_clk","core_clk","vout_ahb",
1607 "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1608 "dc8200_pix0_out","dc8200_pix1_out";
1609 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1610 <&rstgen RSTN_U0_DC8200_AXI>,
1611 <&rstgen RSTN_U0_DC8200_AHB>,
1612 <&rstgen RSTN_U0_DC8200_CORE>,
1613 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1614 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1615 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1616 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1617 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1618 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1619 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1620 "rst_noc_disp","rst_noc_stg";
1621 power-domains = <&pwrc JH7110_PD_VOUT>;
1624 encoder: display-encoder {
1625 compatible = "verisilicon,dsi-encoder";
1626 status = "disabled";
1629 mipi_dphy: mipi-dphy@295e0000{
1630 compatible = "starfive,jh7100-mipi-dphy-tx";
1631 reg = <0x0 0x295e0000 0x0 0x10000>;
1632 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1633 clock-names = "dphy_txesc";
1634 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1635 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1636 reset-names = "dphy_sys", "dphy_txbytehs";
1638 status = "disabled";
1641 mipi_dsi: mipi@295d0000 {
1642 compatible = "cdns,dsi";
1643 reg = <0x0 0x295d0000 0x0 0x10000>;
1646 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1647 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1648 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1649 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1650 clock-names = "sys", "apb", "txesc", "dpi";
1651 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1652 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1653 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1654 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1655 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1656 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1657 reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1658 "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1659 phys = <&mipi_dphy>;
1661 status = "disabled";
1664 dsi_out_port: endpoint@0 {
1665 remote-endpoint = <&panel_dsi_port>;
1667 dsi_in_port: endpoint@1 {
1668 remote-endpoint = <&mipi_out>;
1672 mipi_panel: panel@0 {
1673 /*compatible = "";*/
1678 hdmi: hdmi@29590000 {
1679 compatible = "rockchip,rk3036-inno-hdmi";
1680 reg = <0x0 0x29590000 0x0 0x4000>;
1682 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1683 /*clocks = <&cru PCLK_HDMI>;*/
1684 /*clock-names = "pclk";*/
1685 /*pinctrl-names = "default";*/
1686 /*pinctrl-0 = <&hdmi_ctl>;*/
1687 status = "disabled";
1688 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1689 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1690 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1691 <&hdmitx0_pixelclk>;
1692 clock-names = "sysclk", "mclk","bclk","pclk";
1693 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1694 reset-names = "hdmi_tx";
1698 compatible = "simple-audio-card";
1699 simple-audio-card,name = "Starfive-Multi-Sound-Card";
1700 #address-cells = <1>;
1705 compatible = "starfive,e24";
1706 reg = <0x0 0xc0110000 0x0 0x00001000>,
1707 <0x0 0xc0111000 0x0 0x0001f000>;
1708 reg-names = "ecmd", "espace";
1709 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1710 <&clkgen JH7110_E2_CLK_CORE>,
1711 <&clkgen JH7110_E2_CLK_DBG>;
1712 clock-names = "clk_rtc", "clk_core", "clk_dbg";
1713 resets = <&rstgen RSTN_U0_E24_CORE>;
1714 reset-names = "e24_core";
1715 starfive,stg-syscon = <&stg_syscon>;
1716 interrupt-parent = <&plic>;
1717 firmware-name = "e24_elf";
1719 mbox-names = "tx", "rx";
1720 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1721 #address-cells = <1>;
1723 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1724 status = "disabled";
1729 compatible = "cdns,xrp";
1730 reg = <0x0 0x10230000 0x0 0x00010000
1731 0x0 0x10240000 0x0 0x00010000>;
1732 memory-region = <&xrp_reserved>;
1733 clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1734 clock-names = "core_clk";
1735 resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1736 <&rstgen RSTN_U0_HIFI4_AXI>;
1737 reset-names = "rst_core","rst_axi";
1738 starfive,stg-syscon = <&stg_syscon>;
1739 firmware-name = "hifi4_elf";
1740 #address-cells = <1>;
1742 ranges = <0x40000000 0x0 0x20000000 0x040000
1743 0xf0000000 0x0 0xf0000000 0x03000000>;
1744 status = "disabled";