1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110-clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
13 #include <dt-bindings/power/jh7110-power.h>
16 compatible = "starfive,jh7110";
25 compatible = "sifive,u74-mc", "riscv";
27 d-cache-block-size = <64>;
29 d-cache-size = <8192>;
33 i-cache-block-size = <64>;
35 i-cache-size = <16384>;
38 mmu-type = "riscv,sv39";
39 next-level-cache = <&cachectrl>;
40 riscv,isa = "rv64imac";
44 cpu0intctrl: interrupt-controller {
45 #interrupt-cells = <1>;
46 compatible = "riscv,cpu-intc";
52 compatible = "sifive,u74-mc", "riscv";
54 d-cache-block-size = <64>;
56 d-cache-size = <32768>;
60 i-cache-block-size = <64>;
62 i-cache-size = <32768>;
65 mmu-type = "riscv,sv39";
66 next-level-cache = <&cachectrl>;
67 riscv,isa = "rv64imafdc";
71 cpu1intctrl: interrupt-controller {
72 #interrupt-cells = <1>;
73 compatible = "riscv,cpu-intc";
79 compatible = "sifive,u74-mc", "riscv";
81 d-cache-block-size = <64>;
83 d-cache-size = <32768>;
87 i-cache-block-size = <64>;
89 i-cache-size = <32768>;
92 mmu-type = "riscv,sv39";
93 next-level-cache = <&cachectrl>;
94 riscv,isa = "rv64imafdc";
98 cpu2intctrl: interrupt-controller {
99 #interrupt-cells = <1>;
100 compatible = "riscv,cpu-intc";
101 interrupt-controller;
106 compatible = "sifive,u74-mc", "riscv";
108 d-cache-block-size = <64>;
110 d-cache-size = <32768>;
114 i-cache-block-size = <64>;
116 i-cache-size = <32768>;
119 mmu-type = "riscv,sv39";
120 next-level-cache = <&cachectrl>;
121 riscv,isa = "rv64imafdc";
125 cpu3intctrl: interrupt-controller {
126 #interrupt-cells = <1>;
127 compatible = "riscv,cpu-intc";
128 interrupt-controller;
133 compatible = "sifive,u74-mc", "riscv";
135 d-cache-block-size = <64>;
137 d-cache-size = <32768>;
141 i-cache-block-size = <64>;
143 i-cache-size = <32768>;
146 mmu-type = "riscv,sv39";
147 next-level-cache = <&cachectrl>;
148 riscv,isa = "rv64imafdc";
152 cpu4intctrl: interrupt-controller {
153 #interrupt-cells = <1>;
154 compatible = "riscv,cpu-intc";
155 interrupt-controller;
161 compatible = "simple-bus";
162 interrupt-parent = <&plic>;
163 #address-cells = <2>;
168 cachectrl: cache-controller@2010000 {
169 compatible = "sifive,fu740-c000-ccache", "cache";
170 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
171 reg-names = "control", "sideband";
172 interrupts = <1 3 4 2>;
173 cache-block-size = <64>;
176 cache-size = <2097152>;
180 aon_syscon: aon_syscon@17010000 {
181 compatible = "syscon";
182 reg = <0x0 0x17010000 0x0 0x1000>;
185 stg_syscon: stg_syscon@10240000 {
186 compatible = "syscon";
187 reg = <0x0 0x10240000 0x0 0x1000>;
190 sys_syscon: sys_syscon@13030000 {
191 compatible = "syscon";
192 reg = <0x0 0x13030000 0x0 0x1000>;
195 clint: clint@2000000 {
196 compatible = "riscv,clint0";
197 reg = <0x0 0x2000000 0x0 0x10000>;
198 reg-names = "control";
199 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
200 &cpu1intctrl 3 &cpu1intctrl 7
201 &cpu2intctrl 3 &cpu2intctrl 7
202 &cpu3intctrl 3 &cpu3intctrl 7
203 &cpu4intctrl 3 &cpu4intctrl 7>;
204 #interrupt-cells = <1>;
208 compatible = "riscv,plic0";
209 reg = <0x0 0xc000000 0x0 0x4000000>;
210 reg-names = "control";
211 interrupts-extended = <&cpu0intctrl 11
212 &cpu1intctrl 11 &cpu1intctrl 9
213 &cpu2intctrl 11 &cpu2intctrl 9
214 &cpu3intctrl 11 &cpu3intctrl 9
215 &cpu4intctrl 11 &cpu4intctrl 9>;
216 interrupt-controller;
217 #interrupt-cells = <1>;
218 riscv,max-priority = <7>;
222 clkgen: clock-controller {
223 compatible = "starfive,jh7110-clkgen";
224 reg = <0x0 0x13020000 0x0 0x10000>,
225 <0x0 0x10230000 0x0 0x10000>,
226 <0x0 0x17000000 0x0 0x10000>;
227 reg-names = "sys", "stg", "aon";
228 clocks = <&osc>, <&gmac1_rmii_refin>,
230 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
231 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
232 <&tdm_ext>, <&mclk_ext>,
233 <&jtag_tck_inner>, <&bist_apb>,
234 <&stg_apb>, <&clk_rtc>,
235 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
236 clock-names = "osc", "gmac1_rmii_refin",
238 "i2stx_bclk_ext", "i2stx_lrck_ext",
239 "i2srx_bclk_ext", "i2srx_lrck_ext",
240 "tdm_ext", "mclk_ext",
241 "jtag_tck_inner", "bist_apb",
242 "stg_apb", "clk_rtc",
243 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
248 clkvout: clock-controller@295C0000 {
249 compatible = "starfive,jh7110-clk-vout";
250 reg = <0x0 0x295C0000 0x0 0x10000>;
252 clocks = <&hdmitx0_pixelclk>,
253 <&mipitx_dphy_rxesc>,
254 <&mipitx_dphy_txbytehs>,
255 <&clkgen JH7110_VOUT_SRC>,
256 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
257 clock-names = "hdmitx0_pixelclk",
259 "mipitx_dphy_txbytehs",
262 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
263 reset-names = "vout_src";
265 power-domains = <&pwrc JH7110_PD_VOUT>;
269 clkisp: clock-controller@19810000 {
270 compatible = "starfive,jh7110-clk-isp";
271 reg = <0x0 0x19810000 0x0 0x10000>;
274 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
275 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
276 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
277 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
278 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
279 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
280 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
281 "u0_sft7110_noc_bus_clk_isp_axi";
282 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
283 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
284 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
285 reset-names = "rst_isp_top_n", "rst_isp_top_axi",
287 power-domains = <&pwrc JH7110_PD_ISP>;
292 compatible = "cdns,qspi-nor";
293 #address-cells = <1>;
295 reg = <0x0 0x13010000 0x0 0x10000
296 0x0 0x21000000 0x0 0x400000>;
297 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
298 clock-names = "clk_ref";
299 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
300 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
301 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
302 resets-names = "rst_apb", "rst_ahb", "rst_ref";
303 cdns,fifo-depth = <256>;
304 cdns,fifo-width = <4>;
305 spi-max-frequency = <250000000>;
307 nor_flash: nor-flash@0 {
308 compatible = "jedec,spi-nor";
310 spi-max-frequency = <100000000>;
319 compatible = "starfive,jh7110-otp";
320 reg = <0x0 0x17050000 0x0 0x10000>;
321 clock-frequency = <4000000>;
322 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
327 compatible = "starfive,jh7110-cdns3";
328 clocks = <&clkgen JH7110_USB_125M>,
329 <&clkgen JH7110_USB0_CLK_APP_125>,
330 <&clkgen JH7110_USB0_CLK_LPM>,
331 <&clkgen JH7110_USB0_CLK_STB>,
332 <&clkgen JH7110_USB0_CLK_USB_APB>,
333 <&clkgen JH7110_USB0_CLK_AXI>,
334 <&clkgen JH7110_USB0_CLK_UTMI_APB>;
335 clock-names = "125m","app","lpm","stb","apb","axi","utmi";
336 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
337 <&rstgen RSTN_U0_CDN_USB_APB>,
338 <&rstgen RSTN_U0_CDN_USB_AXI>,
339 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
340 reset-names = "pwrup","apb","axi","utmi";
341 starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
342 starfive,sys-syscon = <&sys_syscon 0x18>;
344 #address-cells = <2>;
346 #interrupt-cells = <1>;
348 usbdrd_cdns3: usb@10100000 {
349 compatible = "cdns,usb3";
350 reg = <0x0 0x10100000 0x0 0x10000>,
351 <0x0 0x10110000 0x0 0x10000>,
352 <0x0 0x10120000 0x0 0x10000>;
353 reg-names = "otg", "xhci", "dev";
354 interrupts = <100>, <109>, <110>;
355 interrupt-names = "host", "peripheral", "otg";
356 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
357 maximum-speed = "super-speed";
361 timer: timer@13050000 {
362 compatible = "starfive,si5-timers";
363 reg = <0x0 0x13050000 0x0 0x10000>;
364 interrupts = <69>, <70>, <71> ,<72>;
365 interrupt-names = "timer0", "timer1",
367 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
368 <&clkgen JH7110_TIMER_CLK_TIMER1>,
369 <&clkgen JH7110_TIMER_CLK_TIMER2>,
370 <&clkgen JH7110_TIMER_CLK_TIMER3>,
371 <&clkgen JH7110_TIMER_CLK_APB>;
372 clock-names = "timer0", "timer1",
373 "timer2", "timer3", "apb_clk";
374 clock-frequency = <24000000>;
378 wdog: wdog@13070000 {
379 compatible = "starfive,dskit-wdt";
380 reg = <0x0 0x13070000 0x0 0x10000>;
382 interrupt-names = "wdog";
383 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
384 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
385 clock-names = "core_clk", "apb_clk";
386 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
387 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
388 reset-names = "rst_apb", "rst_core";
394 compatible = "starfive,rtc_hms";
395 reg = <0x0 0x17040000 0x0 0x10000>;
396 interrupts = <10>, <11>, <12>;
397 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
398 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
399 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
400 clock-names = "pclk", "cal_clk";
401 resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
402 <&rstgen RSTN_U0_RTC_HMS_CAL>,
403 <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
404 reset-names = "rst_apb", "rst_cal", "rst_osc";
405 rtc,cal-clock-freq = <1000000>;
409 pwrc: power-controller@17030000 {
410 compatible = "starfive,jh7110-pmu";
411 reg = <0x0 0x17030000 0x0 0x10000>;
413 #power-domain-cells = <1>;
417 uart0: serial@10000000 {
418 compatible = "snps,dw-apb-uart";
419 reg = <0x0 0x10000000 0x0 0x10000>;
422 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
423 <&clkgen JH7110_UART0_CLK_APB>;
424 clock-names = "baudclk", "apb_pclk";
425 resets = <&rstgen RSTN_U0_DW_UART_APB>,
426 <&rstgen RSTN_U0_DW_UART_CORE>;
431 uart1: serial@10010000 {
432 compatible = "snps,dw-apb-uart";
433 reg = <0x0 0x10010000 0x0 0x10000>;
436 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
437 <&clkgen JH7110_UART1_CLK_APB>;
438 clock-names = "baudclk", "apb_pclk";
439 resets = <&rstgen RSTN_U1_DW_UART_APB>,
440 <&rstgen RSTN_U1_DW_UART_CORE>;
445 uart2: serial@10020000 {
446 compatible = "snps,dw-apb-uart";
447 reg = <0x0 0x10020000 0x0 0x10000>;
450 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
451 <&clkgen JH7110_UART2_CLK_APB>;
452 clock-names = "baudclk", "apb_pclk";
453 resets = <&rstgen RSTN_U2_DW_UART_APB>,
454 <&rstgen RSTN_U2_DW_UART_CORE>;
459 uart3: serial@12000000 {
460 compatible = "snps,dw-apb-uart";
461 reg = <0x0 0x12000000 0x0 0x10000>;
464 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
465 <&clkgen JH7110_UART3_CLK_APB>;
466 clock-names = "baudclk", "apb_pclk";
467 resets = <&rstgen RSTN_U3_DW_UART_APB>,
468 <&rstgen RSTN_U3_DW_UART_CORE>;
473 uart4: serial@12010000 {
474 compatible = "snps,dw-apb-uart";
475 reg = <0x0 0x12010000 0x0 0x10000>;
478 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
479 <&clkgen JH7110_UART4_CLK_APB>;
480 clock-names = "baudclk", "apb_pclk";
481 resets = <&rstgen RSTN_U4_DW_UART_APB>,
482 <&rstgen RSTN_U4_DW_UART_CORE>;
487 uart5: serial@12020000 {
488 compatible = "snps,dw-apb-uart";
489 reg = <0x0 0x12020000 0x0 0x10000>;
492 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
493 <&clkgen JH7110_UART5_CLK_APB>;
494 clock-names = "baudclk", "apb_pclk";
495 resets = <&rstgen RSTN_U5_DW_UART_APB>,
496 <&rstgen RSTN_U5_DW_UART_CORE>;
501 dma: dma-controller@16050000 {
502 compatible = "starfive,axi-dma";
503 reg = <0x0 0x16050000 0x0 0x10000>;
504 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
505 <&clkgen JH7110_DMA1P_CLK_AHB>;
506 clock-names = "core-clk", "cfgr-clk";
507 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
508 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
509 reset-names = "rst_axi", "rst_ahb";
513 snps,dma-masters = <1>;
514 snps,data-width = <3>;
515 snps,num-hs-if = <56>;
516 snps,block-size = <65536 65536 65536 65536>;
517 snps,priority = <0 1 2 3>;
518 snps,axi-max-burst-len = <16>;
522 gpio: gpio@13040000 {
523 compatible = "starfive,jh7110-sys-pinctrl";
524 reg = <0x0 0x13040000 0x0 0x10000>;
525 reg-names = "control";
526 clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
527 resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
529 interrupt-controller;
535 gpioa: gpio@17020000 {
536 compatible = "starfive,jh7110-aon-pinctrl";
537 reg = <0x0 0x17020000 0x0 0x10000>;
538 reg-names = "control";
539 resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
541 interrupt-controller;
547 sfctemp: tmon@120e0000 {
548 compatible = "starfive,jh7110-temp";
549 reg = <0x0 0x120e0000 0x0 0x10000>;
551 clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
552 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
553 clock-names = "sense", "bus";
554 resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
555 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
556 reset-names = "sense", "bus";
557 #thermal-sensor-cells = <0>;
563 polling-delay-passive = <250>;
564 polling-delay = <15000>;
566 thermal-sensors = <&sfctemp>;
572 cpu_alert0: cpu_alert0 {
574 temperature = <75000>;
581 temperature = <90000>;
589 trng: trng@1600C000 {
590 compatible = "starfive,trng";
591 reg = <0x0 0x1600C000 0x0 0x4000>;
592 clocks = <&clkgen JH7110_SEC_HCLK>,
593 <&clkgen JH7110_SEC_MISCAHB_CLK>;
594 clock-names = "hclk", "miscahb_clk";
595 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
600 sec_dma: sec_dma@16008000 {
601 /*compatible = "arm,pl080", "arm,primecell";*/
602 compatible = "starfive,pl080";
603 reg = <0x0 0x16008000 0x0 0x4000>;
604 reg-names = "sec_dma";
606 clocks = <&clkgen JH7110_SEC_HCLK>,
607 <&clkgen JH7110_SEC_MISCAHB_CLK>;
608 clock-names = "sec_hclk","sec_ahb";
609 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
610 reset-names = "sec_hre";
611 lli-bus-interface-ahb1;
612 mem-bus-interface-ahb1;
613 memcpy-burst-size = <256>;
614 memcpy-bus-width = <32>;
619 crypto: crypto@16000000 {
620 compatible = "starfive,jh7110-sec";
621 reg = <0x0 0x16000000 0x0 0x4000>,
622 <0x0 0x16008000 0x0 0x4000>;
623 reg-names = "secreg","secdma";
624 interrupts = <28>, <29>;
625 interrupt-names = "secirq", "dmairq";
626 clocks = <&clkgen JH7110_SEC_HCLK>,
627 <&clkgen JH7110_SEC_MISCAHB_CLK>;
628 clock-names = "sec_hclk","sec_ahb";
629 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
630 reset-names = "sec_hre";
632 dmas = <&sec_dma 1 2>,
634 dma-names = "sec_m","sec_p";
639 compatible = "snps,designware-i2c";
640 reg = <0x0 0x10030000 0x0 0x10000>;
641 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
642 <&clkgen JH7110_I2C0_CLK_APB>;
643 clock-names = "ref", "pclk";
644 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
646 #address-cells = <1>;
652 compatible = "snps,designware-i2c";
653 reg = <0x0 0x10040000 0x0 0x10000>;
654 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
655 <&clkgen JH7110_I2C1_CLK_APB>;
656 clock-names = "ref", "pclk";
657 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
659 #address-cells = <1>;
665 compatible = "snps,designware-i2c";
666 reg = <0x0 0x10050000 0x0 0x10000>;
667 clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
668 <&clkgen JH7110_I2C2_CLK_APB>;
669 clock-names = "ref", "pclk";
670 resets = <&rstgen RSTN_U2_DW_I2C_APB>;
672 #address-cells = <1>;
678 compatible = "snps,designware-i2c";
679 reg = <0x0 0x12030000 0x0 0x10000>;
680 clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
681 <&clkgen JH7110_I2C3_CLK_APB>;
682 clock-names = "ref", "pclk";
683 resets = <&rstgen RSTN_U3_DW_I2C_APB>;
685 #address-cells = <1>;
691 compatible = "snps,designware-i2c";
692 reg = <0x0 0x12040000 0x0 0x10000>;
693 clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
694 <&clkgen JH7110_I2C4_CLK_APB>;
695 clock-names = "ref", "pclk";
696 resets = <&rstgen RSTN_U4_DW_I2C_APB>;
698 #address-cells = <1>;
704 compatible = "snps,designware-i2c";
705 reg = <0x0 0x12050000 0x0 0x10000>;
706 clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
707 <&clkgen JH7110_I2C5_CLK_APB>;
708 clock-names = "ref", "pclk";
709 resets = <&rstgen RSTN_U5_DW_I2C_APB>;
711 #address-cells = <1>;
717 compatible = "snps,designware-i2c";
718 reg = <0x0 0x12060000 0x0 0x10000>;
719 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
720 <&clkgen JH7110_I2C6_CLK_APB>;
721 clock-names = "ref", "pclk";
722 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
724 #address-cells = <1>;
729 /* unremovable emmc as mmcblk0 */
730 sdio0: sdio0@16010000 {
731 compatible = "snps,dw-mshc";
732 reg = <0x0 0x16010000 0x0 0x10000>;
733 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
734 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
735 clock-names = "biu","ciu";
736 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
737 reset-names = "reset";
740 fifo-watermark-aligned;
745 sdio1: sdio1@16020000 {
746 compatible = "snps,dw-mshc";
747 reg = <0x0 0x16020000 0x0 0x10000>;
748 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
749 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
750 clock-names = "biu","ciu";
751 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
752 reset-names = "reset";
755 fifo-watermark-aligned;
760 vin_sysctl: vin_sysctl@19800000 {
761 compatible = "starfive,stf-vin";
762 reg = <0x0 0x19800000 0x0 0x10000>,
763 <0x0 0x19810000 0x0 0x10000>,
764 <0x0 0x19820000 0x0 0x10000>,
765 <0x0 0x19830000 0x0 0x10000>,
766 <0x0 0x19840000 0x0 0x10000>,
767 <0x0 0x19870000 0x0 0x30000>,
768 <0x0 0x11840000 0x0 0x10000>,
769 <0x0 0x17030000 0x0 0x10000>,
770 <0x0 0x13020000 0x0 0x10000>;
771 reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
772 "isp", "trst", "pmu", "syscrg";
773 clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
774 <&clkisp JH7110_U0_VIN_PCLK>,
775 <&clkisp JH7110_U0_VIN_SYS_CLK>,
776 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
777 <&clkisp JH7110_DVP_INV>,
778 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
779 <&clkisp JH7110_MIPI_RX0_PXL>,
780 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
781 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
782 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
783 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
784 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
785 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
786 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
787 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
788 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
789 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
790 clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
791 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
792 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
793 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
794 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
795 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
796 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
797 resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
798 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
799 <&rstgen RSTN_U0_VIN_N_PCLK>,
800 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
801 <&rstgen RSTN_U0_VIN_P_AXIRD>,
802 <&rstgen RSTN_U0_VIN_P_AXIWR>,
803 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
804 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
805 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
806 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
807 <&rstgen RSTN_U0_M31DPHY_HW>,
808 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
809 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
810 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
811 reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
812 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
813 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
814 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
815 "rst_isp_top_n", "rst_isp_top_axi";
816 power-domains = <&pwrc JH7110_PD_ISP>;
817 /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
818 interrupts = <92 87 88 89 90>;
823 compatible = "starfive,jpu";
824 reg = <0x0 0x13090000 0x0 0x300>;
826 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
827 <&clkgen JH7110_CODAJ12_CLK_CORE>,
828 <&clkgen JH7110_CODAJ12_CLK_APB>,
829 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
830 clock-names = "axi_clk", "core_clk",
831 "apb_clk", "noc_bus";
832 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
833 <&rstgen RSTN_U0_CODAJ12_CORE>,
834 <&rstgen RSTN_U0_CODAJ12_APB>;
835 reset-names = "rst_axi", "rst_core", "rst_apb";
839 vpu_dec: vpu_dec@130A0000 {
840 compatible = "starfive,vdec";
841 reg = <0x0 0x130A0000 0x0 0x10000>;
843 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
844 <&clkgen JH7110_WAVE511_CLK_BPU>,
845 <&clkgen JH7110_WAVE511_CLK_VCE>,
846 <&clkgen JH7110_WAVE511_CLK_APB>,
847 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
848 clock-names = "axi_clk", "bpu_clk", "vce_clk",
849 "apb_clk", "noc_bus";
850 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
851 <&rstgen RSTN_U0_WAVE511_BPU>,
852 <&rstgen RSTN_U0_WAVE511_VCE>,
853 <&rstgen RSTN_U0_WAVE511_APB>,
854 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
855 reset-names = "rst_axi", "rst_bpu", "rst_vce",
856 "rst_apb", "rst_sram";
857 starfive,vdec_noc_ctrl;
861 vpu_enc: vpu_enc@130B0000 {
862 compatible = "starfive,venc";
863 reg = <0x0 0x130B0000 0x0 0x10000>;
865 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
866 <&clkgen JH7110_WAVE420L_CLK_BPU>,
867 <&clkgen JH7110_WAVE420L_CLK_VCE>,
868 <&clkgen JH7110_WAVE420L_CLK_APB>,
869 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
870 clock-names = "axi_clk", "bpu_clk", "vce_clk",
871 "apb_clk", "noc_bus";
872 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
873 <&rstgen RSTN_U0_WAVE420L_BPU>,
874 <&rstgen RSTN_U0_WAVE420L_VCE>,
875 <&rstgen RSTN_U0_WAVE420L_APB>,
876 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
877 reset-names = "rst_axi", "rst_bpu", "rst_vce",
878 "rst_apb", "rst_sram";
879 starfive,venc_noc_ctrl;
883 rstgen: reset-controller {
884 compatible = "starfive,jh7110-reset";
885 reg = <0x0 0x13020000 0x0 0x10000>,
886 <0x0 0x10230000 0x0 0x10000>,
887 <0x0 0x17000000 0x0 0x10000>,
888 <0x0 0x19810000 0x0 0x10000>,
889 <0x0 0x295C0000 0x0 0x10000>;
890 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
895 stmmac_axi_setup: stmmac-axi-config {
896 snps,wr_osr_lmt = <0xf>;
897 snps,rd_osr_lmt = <0xf>;
898 snps,blen = <256 128 64 32 0 0 0>;
901 gmac0: ethernet@16030000 {
902 compatible = "starfive,jh7110-eqos-5.20";
903 reg = <0x0 0x16030000 0x0 0x10000>;
910 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
911 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
912 <&clkgen JH7110_GMAC0_PTP>,
913 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
914 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
915 <&clkgen JH7110_GMAC0_GTXC>;
916 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
917 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
918 reset-names = "ahb", "stmmaceth";
919 interrupts = <7>, <6>, <5> ;
920 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
921 max-frame-size = <9000>;
922 phy-mode = "rgmii-id";
923 snps,multicast-filter-bins = <64>;
924 snps,perfect-filter-entries = <128>;
925 rx-fifo-depth = <2048>;
926 tx-fifo-depth = <2048>;
929 snps,force_thresh_dma_mode;
930 snps,axi-config = <&stmmac_axi_setup>;
932 snps,en-tx-lpi-clockgating;
934 snps,write-requests = <4>;
935 snps,read-requests = <4>;
936 snps,burst-map = <0x7>;
942 gmac1: ethernet@16040000 {
943 compatible = "starfive,jh7110-eqos-5.20";
944 reg = <0x0 0x16040000 0x0 0x10000>;
951 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
952 <&clkgen JH7110_GMAC5_CLK_TX>,
953 <&clkgen JH7110_GMAC5_CLK_PTP>,
954 <&clkgen JH7110_GMAC5_CLK_AHB>,
955 <&clkgen JH7110_GMAC5_CLK_AXI>,
956 <&clkgen JH7110_GMAC1_GTXC>;
957 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
958 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
959 reset-names = "ahb", "stmmaceth";
960 interrupts = <78>, <77>, <76> ;
961 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
962 max-frame-size = <9000>;
963 phy-mode = "rgmii-id";
964 snps,multicast-filter-bins = <64>;
965 snps,perfect-filter-entries = <128>;
966 rx-fifo-depth = <2048>;
967 tx-fifo-depth = <2048>;
970 snps,force_thresh_dma_mode;
971 snps,axi-config = <&stmmac_axi_setup>;
973 snps,en-tx-lpi-clockgating;
975 snps,write-requests = <4>;
976 snps,read-requests = <4>;
977 snps,burst-map = <0x7>;
984 compatible = "img-gpu";
985 reg = <0x0 0x18000000 0x0 0x100000>,
986 <0x0 0x130C000 0x0 0x10000>;
987 clocks = <&clkgen JH7110_GPU_CLK_APB>,
988 <&clkgen JH7110_GPU_RTC_TOGGLE>,
989 <&clkgen JH7110_GPU_CORE_CLK>,
990 <&clkgen JH7110_GPU_SYS_CLK>,
991 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
992 clock-names = "clk_apb", "clk_rtc", "clk_core",
993 "clk_sys", "clk_axi";
994 resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
995 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
996 reset-names = "rst_apb", "rst_doma";
998 current-clock = <8000000>;
1002 can0: can@130d0000 {
1003 compatible = "ipms,can";
1004 reg = <0x0 0x130d0000 0x0 0x1000>;
1006 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1007 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1008 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1009 clock-names = "apb_clk", "core_clk", "timer_clk";
1010 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1011 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1012 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1013 reset-names = "rst_apb", "rst_core", "rst_timer";
1014 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1015 syscon,can_or_canfd = <0>;
1016 status = "disabled";
1019 can1: can@130e0000 {
1020 compatible = "ipms,can";
1021 reg = <0x0 0x130e0000 0x0 0x1000>;
1023 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1024 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1025 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1026 clock-names = "apb_clk", "core_clk", "timer_clk";
1027 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1028 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1029 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1030 reset-names = "rst_apb", "rst_core", "rst_timer";
1031 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1032 syscon,can_or_canfd = <0>;
1033 status = "disabled";
1037 compatible = "starfive,sf-tdm";
1038 reg = <0x0 0x10090000 0x0 0x1000>;
1040 clocks = <&clkgen JH7110_AHB0>,
1041 <&clkgen JH7110_TDM_CLK_AHB>,
1042 <&clkgen JH7110_APB0>,
1043 <&clkgen JH7110_TDM_CLK_APB>,
1044 <&clkgen JH7110_TDM_INTERNAL>,
1046 <&clkgen JH7110_TDM_CLK_TDM>,
1047 <&clkgen JH7110_MCLK_INNER>;
1048 clock-names = "clk_ahb0", "clk_tdm_ahb",
1049 "clk_apb0", "clk_tdm_apb",
1050 "clk_tdm_internal", "clk_tdm_ext",
1051 "clk_tdm", "mclk_inner";
1052 resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1053 <&rstgen RSTN_U0_TDM16SLOT_APB>,
1054 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1055 reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1056 dmas = <&dma 20 1>, <&dma 21 1>;
1057 dma-names = "rx","tx";
1058 #sound-dai-cells = <0>;
1059 status = "disabled";
1062 spdif0: spdif0@100a0000 {
1063 compatible = "starfive,sf-spdif";
1064 reg = <0x0 0x100a0000 0x0 0x1000>;
1065 clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1066 <&clkgen JH7110_SPDIF_CLK_CORE>,
1067 <&clkgen JH7110_APB0>,
1068 <&clkgen JH7110_AUDIO_ROOT>,
1069 <&clkgen JH7110_MCLK_INNER>;
1070 clock-names = "spdif-apb", "spdif-core", "apb0",
1071 "audroot", "mclk_inner";
1072 resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1073 reset-names = "rst_apb";
1075 interrupt-names = "tx";
1076 #sound-dai-cells = <0>;
1077 status = "disabled";
1080 pwmdac: pwmdac@100b0000 {
1081 compatible = "starfive,pwmdac";
1082 reg = <0x0 0x100b0000 0x0 0x1000>;
1083 clocks = <&clkgen JH7110_APB0>,
1084 <&clkgen JH7110_PWMDAC_CLK_APB>,
1085 <&clkgen JH7110_PWMDAC_CLK_CORE>;
1086 clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1087 resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1088 reset-names = "rst-apb";
1091 #sound-dai-cells = <0>;
1092 status = "disabled";
1095 i2stx: i2stx@100c0000 {
1096 compatible = "snps,designware-i2stx";
1097 reg = <0x0 0x100c0000 0x0 0x1000>;
1098 interrupt-names = "tx";
1099 #sound-dai-cells = <0>;
1102 status = "disabled";
1106 compatible = "starfive,sf-pdm";
1107 reg = <0x0 0x100d0000 0x0 0x1000>;
1109 clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1110 <&clkgen JH7110_APB0>,
1111 <&clkgen JH7110_PDM_CLK_APB>,
1112 <&clkgen JH7110_MCLK_INNER>,
1113 <&clkgen JH7110_MCLK>,
1114 <&clkgen JH7110_MCLK_OUT>;
1115 clock-names = "pdm_mclk", "clk_apb0",
1116 "pdm_apb", "mclk_inner",
1117 "clk_mclk", "mclk_out";
1118 resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1119 <&rstgen RSTN_U0_PDM_4MIC_APB>;
1120 reset-names = "pdm_dmic", "pdm_apb";
1121 #sound-dai-cells = <0>;
1124 i2srx_mst: i2srx_mst@100e0000 {
1125 compatible = "snps,i2srx-master";
1126 reg = <0x0 0x100e0000 0x0 0x1000>;
1127 clocks = <&clkgen JH7110_APB0>,
1128 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1129 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1130 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1131 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1132 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1133 clock-names = "apb0", "i2srx_apb",
1134 "i2srx_bclk_mst", "i2srx_lrck_mst",
1135 "i2srx_bclk", "i2srx_lrck";
1136 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1137 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1138 reset-names = "rst_apb_rx", "rst_bclk_rx";
1141 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1142 #sound-dai-cells = <0>;
1143 status = "disabled";
1146 i2srx_3ch: i2srx_3ch@100e0000 {
1147 compatible = "snps,designware-i2srx";
1148 reg = <0x0 0x100e0000 0x0 0x1000>;
1149 clocks = <&clkgen JH7110_APB0>,
1150 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1151 <&clkgen JH7110_AUDIO_ROOT>,
1152 <&clkgen JH7110_MCLK_INNER>,
1153 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1154 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1155 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1156 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1157 clock-names = "apb0", "3ch-apb",
1158 "audioroot", "mclk-inner",
1159 "bclk_mst", "3ch-lrck",
1160 "rx-bclk", "rx-lrck";
1161 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1162 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1163 reset-names = "rst_apb_rx", "rst_bclk_rx";
1166 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1167 #sound-dai-cells = <0>;
1168 status = "disabled";
1171 i2stx_4ch0: i2stx_4ch0@120b0000 {
1172 compatible = "snps,designware-i2stx-4ch0";
1173 reg = <0x0 0x120b0000 0x0 0x1000>;
1174 clocks = <&clkgen JH7110_MCLK_INNER>,
1175 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1176 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1177 <&clkgen JH7110_MCLK>,
1178 <&clkgen JH7110_I2STX0_4CHBCLK>,
1179 <&clkgen JH7110_I2STX0_4CHLRCK>;
1180 clock-names = "inner", "bclk-mst",
1183 resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1184 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1185 reset-names = "rst_apb0", "rst_bclk0";
1188 #sound-dai-cells = <0>;
1189 status = "disabled";
1192 i2stx_4ch1: i2stx_4ch1@120c0000 {
1193 compatible = "snps,designware-i2stx-4ch1";
1194 reg = <0x0 0x120c0000 0x0 0x1000>;
1195 clocks = <&clkgen JH7110_AUDIO_ROOT>,
1196 <&clkgen JH7110_MCLK_INNER>,
1197 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1198 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1199 <&clkgen JH7110_MCLK>,
1200 <&clkgen JH7110_I2STX1_4CHBCLK>,
1201 <&clkgen JH7110_I2STX1_4CHLRCK>,
1202 <&clkgen JH7110_MCLK_OUT>,
1203 <&clkgen JH7110_APB0>,
1204 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1208 clock-names = "audroot", "mclk_inner", "bclk_mst",
1209 "lrck_mst", "mclk", "4chbclk",
1210 "4chlrck", "mclk_out",
1212 "mclk_ext", "bclk_ext", "lrck_ext";
1214 resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1215 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1216 reset-names = "rst_apb1", "rst_bclk1";
1219 #sound-dai-cells = <0>;
1220 status = "disabled";
1224 compatible = "starfive,pwm0";
1225 reg = <0x0 0x120d0000 0x0 0x10000>;
1226 reg-names = "control";
1227 clocks = <&clkgen JH7110_PWM_CLK_APB>;
1228 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1229 starfive,approx-period = <2000000>;
1231 starfive,npwm = <8>;
1232 status = "disabled";
1235 spdif_transmitter: spdif_transmitter {
1236 compatible = "linux,spdif-dit";
1237 #sound-dai-cells = <0>;
1238 status = "disabled";
1241 spdif_receiver: spdif_receiver {
1242 compatible = "linux,spdif-dir";
1243 #sound-dai-cells = <0>;
1244 status = "disabled";
1247 pwmdac_codec: pwmdac-transmitter {
1248 compatible = "linux,pwmdac-dit";
1249 #sound-dai-cells = <0>;
1250 status = "disabled";
1253 dmic_codec: dmic_codec {
1254 compatible = "dmic-codec";
1255 #sound-dai-cells = <0>;
1256 status = "disabled";
1259 spi0: spi@10060000 {
1260 compatible = "arm,pl022", "arm,primecell";
1261 reg = <0x0 0x10060000 0x0 0x10000>;
1262 clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1263 clock-names = "apb_pclk";
1264 resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1265 reset-names = "rst_apb";
1267 /* shortage of dma channel that not be used */
1268 /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1269 /*dma-names = "rx","tx";*/
1270 arm,primecell-periphid = <0x00041022>;
1272 #address-cells = <1>;
1274 status = "disabled";
1277 spi1: spi@10070000 {
1278 compatible = "arm,pl022", "arm,primecell";
1279 reg = <0x0 0x10070000 0x0 0x10000>;
1280 clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1281 clock-names = "apb_pclk";
1282 resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1283 reset-names = "rst_apb";
1285 /* shortage of dma channel that not be used */
1286 /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1287 /*dma-names = "rx","tx";*/
1288 arm,primecell-periphid = <0x00041022>;
1290 #address-cells = <1>;
1292 status = "disabled";
1295 spi2: spi@10080000 {
1296 compatible = "arm,pl022", "arm,primecell";
1297 reg = <0x0 0x10080000 0x0 0x10000>;
1298 clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1299 clock-names = "apb_pclk";
1300 resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1301 reset-names = "rst_apb";
1303 /* shortage of dma channel that not be used */
1304 /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1305 /*dma-names = "rx","tx";*/
1306 arm,primecell-periphid = <0x00041022>;
1308 #address-cells = <1>;
1310 status = "disabled";
1313 spi3: spi@12070000 {
1314 compatible = "arm,pl022", "arm,primecell";
1315 reg = <0x0 0x12070000 0x0 0x10000>;
1316 clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1317 clock-names = "apb_pclk";
1318 resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1319 reset-names = "rst_apb";
1321 /* shortage of dma channel that not be used */
1322 /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1323 /*dma-names = "rx","tx";*/
1324 arm,primecell-periphid = <0x00041022>;
1326 #address-cells = <1>;
1328 status = "disabled";
1331 spi4: spi@12080000 {
1332 compatible = "arm,pl022", "arm,primecell";
1333 reg = <0x0 0x12080000 0x0 0x10000>;
1334 clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1335 clock-names = "apb_pclk";
1336 resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1337 reset-names = "rst_apb";
1339 /* shortage of dma channel that not be used */
1340 /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1341 /*dma-names = "rx","tx";*/
1342 arm,primecell-periphid = <0x00041022>;
1344 #address-cells = <1>;
1346 status = "disabled";
1349 spi5: spi@12090000 {
1350 compatible = "arm,pl022", "arm,primecell";
1351 reg = <0x0 0x12090000 0x0 0x10000>;
1352 clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1353 clock-names = "apb_pclk";
1354 resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1355 reset-names = "rst_apb";
1357 /* shortage of dma channel that not be used */
1358 /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1359 /*dma-names = "rx","tx";*/
1360 arm,primecell-periphid = <0x00041022>;
1362 #address-cells = <1>;
1364 status = "disabled";
1367 spi6: spi@120A0000 {
1368 compatible = "arm,pl022", "arm,primecell";
1369 reg = <0x0 0x120A0000 0x0 0x10000>;
1370 clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1371 clock-names = "apb_pclk";
1372 resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1373 reset-names = "rst_apb";
1375 /* shortage of dma channel that not be used */
1376 /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1377 /*dma-names = "rx","tx";*/
1378 arm,primecell-periphid = <0x00041022>;
1380 #address-cells = <1>;
1382 status = "disabled";
1385 pcie0: pcie@2B000000 {
1386 compatible = "plda,pci-xpressrich3-axi";
1387 #address-cells = <3>;
1389 #interrupt-cells = <1>;
1390 reg = <0x0 0x2B000000 0x0 0x1000000
1391 0x9 0x40000000 0x0 0x10000000>;
1392 reg-names = "reg", "config";
1393 device_type = "pci";
1394 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1395 bus-range = <0x0 0xff>;
1396 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>;
1397 msi-parent = <&plic>;
1399 interrupt-controller;
1400 interrupt-names = "msi";
1401 interrupt-parent = <&plic>;
1402 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1403 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1404 <0x0 0x0 0x0 0x2 &plic 0x2>,
1405 <0x0 0x0 0x0 0x3 &plic 0x3>,
1406 <0x0 0x0 0x0 0x4 &plic 0x4>;
1407 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1408 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1409 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1410 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1411 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1412 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1413 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1414 "rst_brg", "rst_core", "rst_apb";
1415 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1416 <&clkgen JH7110_PCIE0_CLK_TL>,
1417 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1418 <&clkgen JH7110_PCIE0_CLK_APB>;
1419 clock-names = "noc", "tl", "axi_mst0", "apb";
1420 status = "disabled";
1423 pcie1: pcie@2C000000 {
1424 compatible = "plda,pci-xpressrich3-axi";
1425 #address-cells = <3>;
1427 #interrupt-cells = <1>;
1428 reg = <0x0 0x2C000000 0x0 0x1000000
1429 0x9 0xc0000000 0x0 0x10000000>;
1430 reg-names = "reg", "config";
1431 device_type = "pci";
1432 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1433 bus-range = <0x0 0xff>;
1434 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>;
1435 msi-parent = <&plic>;
1437 interrupt-controller;
1438 interrupt-names = "msi";
1439 interrupt-parent = <&plic>;
1440 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1441 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1442 <0x0 0x0 0x0 0x2 &plic 0x2>,
1443 <0x0 0x0 0x0 0x3 &plic 0x3>,
1444 <0x0 0x0 0x0 0x4 &plic 0x4>;
1445 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1446 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1447 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1448 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1449 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1450 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1451 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1452 "rst_brg", "rst_core", "rst_apb";
1453 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1454 <&clkgen JH7110_PCIE1_CLK_TL>,
1455 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1456 <&clkgen JH7110_PCIE1_CLK_APB>;
1457 clock-names = "noc", "tl", "axi_mst0", "apb";
1458 status = "disabled";
1461 mailbox_contrl0: mailbox@0 {
1462 compatible = "starfive,mail_box";
1463 reg = <0x0 0x13060000 0x0 0x0001000>;
1464 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1465 clock-names = "clk_apb";
1466 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1467 reset-names = "mbx_rre";
1468 interrupts = <26 27>;
1470 status = "disabled";
1473 mailbox_client0: mailbox_client@0 {
1474 compatible = "starfive,mailbox-test";
1475 mbox-names = "rx", "tx";
1476 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1477 status = "disabled";
1480 display: display-subsystem {
1481 compatible = "verisilicon,display-subsystem";
1482 ports = <&dc_out_dpi0>;
1483 status = "disabled";
1486 dssctrl: dssctrl@295B0000 {
1487 compatible = "verisilicon,dss-ctrl", "syscon";
1488 reg = <0 0x295B0000 0 0x90>;
1491 tda988x_pin: tda988x_pin {
1492 compatible = "starfive,tda998x_rgb_pin";
1493 status = "disabled";
1496 hdmi_output: hdmi-output {
1497 compatible = "verisilicon,hdmi-encoder";
1498 //verisilicon,dss-syscon = <&dssctrl>;
1499 //verisilicon,mux-mask = <0x70 0x380>;
1500 //verisilicon,mux-val = <0x40 0x280>;
1501 status = "disabled";
1504 dc8200: dc8200@29400000 {
1505 compatible = "verisilicon,dc8200";
1506 verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1507 reg = <0x0 0x29400000 0x0 0x100>,
1508 <0x0 0x29400800 0x0 0x2000>,
1509 <0x0 0x17030000 0x0 0x1000>;
1511 status = "disabled";
1512 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1513 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1514 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1515 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1516 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1517 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1518 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1519 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1520 <&clkgen JH7110_VOUT_SRC>,
1521 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1522 <&clkgen JH7110_AHB1>,
1523 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1524 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1525 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1526 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1527 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1528 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1529 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1530 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1531 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1532 <&clkgen JH7110_DOM_VOUT_TOP_LCD_CLK>,
1533 <&hdmitx0_pixelclk>,
1534 <&clkvout JH7110_DC8200_PIX0>;
1535 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1536 "noc_disp","noc_isp","noc_stg","vout_src",
1537 "top_vout_axi","ahb1","top_vout_ahb",
1538 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1539 "axi_clk","core_clk","vout_ahb",
1540 "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0";
1542 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1543 <&rstgen RSTN_U0_DC8200_AXI>,
1544 <&rstgen RSTN_U0_DC8200_AHB>,
1545 <&rstgen RSTN_U0_DC8200_CORE>,
1546 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1547 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1548 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1549 <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
1550 <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
1551 <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
1552 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1553 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
1554 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
1555 <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
1556 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1557 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1558 "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
1559 "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
1560 power-domains = <&pwrc JH7110_PD_VOUT>;
1563 encoder: display-encoder {
1564 compatible = "verisilicon,dsi-encoder";
1565 status = "disabled";
1568 mipi_dphy: mipi-dphy@295e0000{
1569 compatible = "starfive,jh7100-mipi-dphy-tx";
1570 reg = <0x0 0x295e0000 0x0 0x10000>;
1571 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1572 clock-names = "dphy_txesc";
1573 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1574 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1575 reset-names = "dphy_sys", "dphy_txbytehs";
1577 status = "disabled";
1580 mipi_dsi: mipi@295d0000 {
1581 compatible = "cdns,dsi";
1582 reg = <0x0 0x295d0000 0x0 0x10000>;
1585 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1586 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1587 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1588 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1589 clock-names = "sys", "apb", "txesc", "dpi";
1590 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1591 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1592 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1593 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1594 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1595 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1596 reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1597 "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1598 phys = <&mipi_dphy>;
1600 status = "disabled";
1603 dsi_out_port: endpoint@0 {
1604 remote-endpoint = <&panel_dsi_port>;
1606 dsi_in_port: endpoint@1 {
1607 remote-endpoint = <&mipi_out>;
1611 mipi_panel: panel@0 {
1612 /*compatible = "";*/
1617 hdmi: hdmi@29590000 {
1618 compatible = "rockchip,rk3036-inno-hdmi";
1619 reg = <0x0 0x29590000 0x0 0x4000>;
1621 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1622 /*clocks = <&cru PCLK_HDMI>;*/
1623 /*clock-names = "pclk";*/
1624 /*pinctrl-names = "default";*/
1625 /*pinctrl-0 = <&hdmi_ctl>;*/
1626 status = "disabled";
1627 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1628 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1629 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1630 <&hdmitx0_pixelclk>;
1631 clock-names = "sysclk", "mclk","bclk","pclk";
1632 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1633 reset-names = "hdmi_tx";
1637 compatible = "simple-audio-card";
1638 simple-audio-card,name = "Starfive-Multi-Sound-Card";
1639 #address-cells = <1>;
1644 compatible = "starfive,e24";
1645 reg = <0x0 0xc0110000 0x0 0x00001000>,
1646 <0x0 0xc0111000 0x0 0x0001f000>;
1647 reg-names = "ecmd", "espace";
1648 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1649 <&clkgen JH7110_E2_CLK_CORE>,
1650 <&clkgen JH7110_E2_CLK_DBG>;
1651 clock-names = "clk_rtc", "clk_core", "clk_dbg";
1652 resets = <&rstgen RSTN_U0_E24_CORE>;
1653 reset-names = "e24_core";
1654 starfive,stg-syscon = <&stg_syscon>;
1655 interrupt-parent = <&plic>;
1656 firmware-name = "e24_elf";
1658 mbox-names = "tx", "rx";
1659 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1660 #address-cells = <1>;
1662 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1663 status = "disabled";
1668 compatible = "cdns,xrp";
1669 reg = <0x0 0x10230000 0x0 0x00010000
1670 0x0 0x10240000 0x0 0x00010000>;
1671 memory-region = <&xrp_reserved>;
1672 clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1673 clock-names = "core_clk";
1674 resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1675 <&rstgen RSTN_U0_HIFI4_AXI>;
1676 reset-names = "rst_core","rst_axi";
1677 starfive,stg-syscon = <&stg_syscon>;
1678 firmware-name = "hifi4_elf";
1679 #address-cells = <1>;
1681 ranges = <0x40000000 0x0 0x20000000 0x040000
1682 0xf0000000 0x0 0xf0000000 0x03000000>;
1683 status = "disabled";