arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14 #include <dt-bindings/interrupt-controller/irq.h>
  15
  16 / {
  17         compatible = "starfive,jh7110";
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         cluster0_opp: opp-table-0 {
  22                         compatible = "operating-points-v2";
  23                         opp-shared;
  24                         opp-375000000 {
  25                                         opp-hz = /bits/ 64 <375000000>;
  26                                         opp-microvolt = <800000>;
  27                         };
  28                         opp-500000000 {
  29                                         opp-hz = /bits/ 64 <500000000>;
  30                                         opp-microvolt = <800000>;
  31                         };
  32                         opp-750000000 {
  33                                         opp-hz = /bits/ 64 <750000000>;
  34                                         opp-microvolt = <800000>;
  35                         };
  36                         opp-1500000000 {
  37                                         opp-hz = /bits/ 64 <1500000000>;
  38                                         opp-microvolt = <1040000>;
  39                         };
  40         };
  41
  42         cpus {
  43                 #address-cells = <1>;
  44                 #size-cells = <0>;
  45
  46                 cpu0: cpu@0 {
  47                         compatible = "sifive,u74-mc", "riscv";
  48                         reg = <0>;
  49                         d-cache-block-size = <64>;
  50                         d-cache-sets = <64>;
  51                         d-cache-size = <8192>;
  52                         d-tlb-sets = <1>;
  53                         d-tlb-size = <40>;
  54                         device_type = "cpu";
  55                         i-cache-block-size = <64>;
  56                         i-cache-sets = <64>;
  57                         i-cache-size = <16384>;
  58                         i-tlb-sets = <1>;
  59                         i-tlb-size = <40>;
  60                         mmu-type = "riscv,sv39";
  61                         next-level-cache = <&cachectrl>;
  62                         riscv,isa = "rv64imac";
  63                         tlb-split;
  64                         status = "disabled";
  65
  66                         cpu0intctrl: interrupt-controller {
  67                                 #interrupt-cells = <1>;
  68                                 compatible = "riscv,cpu-intc";
  69                                 interrupt-controller;
  70                         };
  71                 };
  72
  73                 cpu1: cpu@1 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <1>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <32768>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <32768>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         next-level-cache = <&cachectrl>;
  89                         riscv,isa = "rv64imafdc";
  90                         tlb-split;
  91                         status = "okay";
  92                         operating-points-v2 = <&cluster0_opp>;
  93
  94                         cpu1intctrl: interrupt-controller {
  95                                 #interrupt-cells = <1>;
  96                                 compatible = "riscv,cpu-intc";
  97                                 interrupt-controller;
  98                         };
  99                 };
 100
 101                 cpu2: cpu@2 {
 102                         compatible = "sifive,u74-mc", "riscv";
 103                         reg = <2>;
 104                         d-cache-block-size = <64>;
 105                         d-cache-sets = <64>;
 106                         d-cache-size = <32768>;
 107                         d-tlb-sets = <1>;
 108                         d-tlb-size = <40>;
 109                         device_type = "cpu";
 110                         i-cache-block-size = <64>;
 111                         i-cache-sets = <64>;
 112                         i-cache-size = <32768>;
 113                         i-tlb-sets = <1>;
 114                         i-tlb-size = <40>;
 115                         mmu-type = "riscv,sv39";
 116                         next-level-cache = <&cachectrl>;
 117                         riscv,isa = "rv64imafdc";
 118                         tlb-split;
 119                         status = "okay";
 120                         operating-points-v2 = <&cluster0_opp>;
 121
 122                         cpu2intctrl: interrupt-controller {
 123                                 #interrupt-cells = <1>;
 124                                 compatible = "riscv,cpu-intc";
 125                                 interrupt-controller;
 126                         };
 127                 };
 128
 129                 cpu3: cpu@3 {
 130                         compatible = "sifive,u74-mc", "riscv";
 131                         reg = <3>;
 132                         d-cache-block-size = <64>;
 133                         d-cache-sets = <64>;
 134                         d-cache-size = <32768>;
 135                         d-tlb-sets = <1>;
 136                         d-tlb-size = <40>;
 137                         device_type = "cpu";
 138                         i-cache-block-size = <64>;
 139                         i-cache-sets = <64>;
 140                         i-cache-size = <32768>;
 141                         i-tlb-sets = <1>;
 142                         i-tlb-size = <40>;
 143                         mmu-type = "riscv,sv39";
 144                         next-level-cache = <&cachectrl>;
 145                         riscv,isa = "rv64imafdc";
 146                         tlb-split;
 147                         status = "okay";
 148                         operating-points-v2 = <&cluster0_opp>;
 149
 150                         cpu3intctrl: interrupt-controller {
 151                                 #interrupt-cells = <1>;
 152                                 compatible = "riscv,cpu-intc";
 153                                 interrupt-controller;
 154                         };
 155                 };
 156
 157                 cpu4: cpu@4 {
 158                         compatible = "sifive,u74-mc", "riscv";
 159                         reg = <4>;
 160                         d-cache-block-size = <64>;
 161                         d-cache-sets = <64>;
 162                         d-cache-size = <32768>;
 163                         d-tlb-sets = <1>;
 164                         d-tlb-size = <40>;
 165                         device_type = "cpu";
 166                         i-cache-block-size = <64>;
 167                         i-cache-sets = <64>;
 168                         i-cache-size = <32768>;
 169                         i-tlb-sets = <1>;
 170                         i-tlb-size = <40>;
 171                         mmu-type = "riscv,sv39";
 172                         next-level-cache = <&cachectrl>;
 173                         riscv,isa = "rv64imafdc";
 174                         tlb-split;
 175                         status = "okay";
 176                         operating-points-v2 = <&cluster0_opp>;
 177
 178                         cpu4intctrl: interrupt-controller {
 179                                 #interrupt-cells = <1>;
 180                                 compatible = "riscv,cpu-intc";
 181                                 interrupt-controller;
 182                         };
 183                 };
 184         };
 185
 186         soc: soc {
 187                 compatible = "simple-bus";
 188                 interrupt-parent = <&plic>;
 189                 #address-cells = <2>;
 190                 #size-cells = <2>;
 191                 #clock-cells = <1>;
 192                 ranges;
 193
 194                 cachectrl: cache-controller@2010000 {
 195                         compatible = "sifive,fu740-c000-ccache", "cache";
 196                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 197                         reg-names = "control", "sideband";
 198                         interrupts = <1 3 4 2>;
 199                         cache-block-size = <64>;
 200                         cache-level = <2>;
 201                         cache-sets = <2048>;
 202                         cache-size = <2097152>;
 203                         cache-unified;
 204                 };
 205
 206                 aon_syscon: aon_syscon@17010000 {
 207                         compatible = "syscon";
 208                         reg = <0x0 0x17010000 0x0 0x1000>;
 209                 };
 210
 211                 stg_syscon: stg_syscon@10240000 {
 212                         compatible = "syscon";
 213                         reg = <0x0 0x10240000 0x0 0x1000>;
 214                 };
 215
 216                 sys_syscon: sys_syscon@13030000 {
 217                         compatible = "syscon";
 218                         reg = <0x0 0x13030000 0x0 0x1000>;
 219                 };
 220
 221                 clint: clint@2000000 {
 222                         compatible = "riscv,clint0";
 223                         reg = <0x0 0x2000000 0x0 0x10000>;
 224                         reg-names = "control";
 225                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 226                                                 &cpu1intctrl 3 &cpu1intctrl 7
 227                                                 &cpu2intctrl 3 &cpu2intctrl 7
 228                                                 &cpu3intctrl 3 &cpu3intctrl 7
 229                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 230                         #interrupt-cells = <1>;
 231                 };
 232
 233                 plic: plic@c000000 {
 234                         compatible = "riscv,plic0";
 235                         reg = <0x0 0xc000000 0x0 0x4000000>;
 236                         reg-names = "control";
 237                         interrupts-extended = <&cpu0intctrl 11
 238                                                 &cpu1intctrl 11 &cpu1intctrl 9
 239                                                 &cpu2intctrl 11 &cpu2intctrl 9
 240                                                 &cpu3intctrl 11 &cpu3intctrl 9
 241                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 242                         interrupt-controller;
 243                         #interrupt-cells = <1>;
 244                         riscv,max-priority = <7>;
 245                         riscv,ndev = <136>;
 246                 };
 247
 248                 clkgen: clock-controller {
 249                         compatible = "starfive,jh7110-clkgen";
 250                         reg = <0x0 0x13020000 0x0 0x10000>,
 251                                 <0x0 0x10230000 0x0 0x10000>,
 252                                 <0x0 0x17000000 0x0 0x10000>;
 253                         reg-names = "sys", "stg", "aon";
 254                         clocks = <&osc>, <&gmac1_rmii_refin>,
 255                                  <&gmac1_rgmii_rxin>,
 256                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 257                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 258                                  <&tdm_ext>, <&mclk_ext>,
 259                                  <&jtag_tck_inner>, <&bist_apb>,
 260                                  <&clk_rtc>,
 261                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 262                         clock-names = "osc", "gmac1_rmii_refin",
 263                                 "gmac1_rgmii_rxin",
 264                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 265                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 266                                 "tdm_ext", "mclk_ext",
 267                                 "jtag_tck_inner", "bist_apb",
 268                                 "clk_rtc",
 269                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 270                         #clock-cells = <1>;
 271                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 272                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 273                         status = "okay";
 274                 };
 275
 276                 clkvout: clock-controller@295C0000 {
 277                         compatible = "starfive,jh7110-clk-vout";
 278                         reg = <0x0 0x295C0000 0x0 0x10000>;
 279                         reg-names = "vout";
 280                         clocks = <&hdmitx0_pixelclk>,
 281                                  <&mipitx_dphy_rxesc>,
 282                                  <&mipitx_dphy_txbytehs>,
 283                                  <&clkgen JH7110_VOUT_SRC>,
 284                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 285                         clock-names = "hdmitx0_pixelclk",
 286                                       "mipitx_dphy_rxesc",
 287                                       "mipitx_dphy_txbytehs",
 288                                       "vout_src",
 289                                       "vout_top_ahb";
 290                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 291                         reset-names = "vout_src";
 292                         #clock-cells = <1>;
 293                         power-domains = <&pwrc JH7110_PD_VOUT>;
 294                         status = "okay";
 295                 };
 296
 297                 clkisp: clock-controller@19810000 {
 298                         compatible = "starfive,jh7110-clk-isp";
 299                         reg = <0x0 0x19810000 0x0 0x10000>;
 300                         reg-names = "isp";
 301                         #clock-cells = <1>;
 302                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 303                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 304                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 305                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 306                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 307                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 308                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 309                                       "u0_sft7110_noc_bus_clk_isp_axi";
 310                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 311                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 312                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 313                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 314                                       "rst_isp_noc_bus_n";
 315                         power-domains = <&pwrc JH7110_PD_ISP>;
 316                         status = "okay";
 317                 };
 318
 319                 qspi: spi@13010000 {
 320                         compatible = "cdns,qspi-nor";
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         reg = <0x0 0x13010000 0x0 0x10000
 324                                 0x0 0x21000000 0x0 0x400000>;
 325                         interrupts = <25>;
 326                         clocks = <&clkgen JH7110_QSPI_CLK_REF>,
 327                                  <&clkgen JH7110_QSPI_CLK_APB>,
 328                                  <&clkgen JH7110_AHB1>,
 329                                  <&clkgen JH7110_QSPI_CLK_AHB>;
 330                         clock-names = "clk_ref",
 331                                       "clk_apb",
 332                                       "ahb1",
 333                                       "clk_ahb";
 334                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 335                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 336                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 337                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 338                         cdns,fifo-depth = <256>;
 339                         cdns,fifo-width = <4>;
 340                         cdns,trigger-address = <0x0>;
 341                         spi-max-frequency = <250000000>;
 342
 343                         nor_flash: nor-flash@0 {
 344                                 compatible = "jedec,spi-nor";
 345                                 reg=<0>;
 346                                 cdns,read-delay = <5>;
 347                                 spi-max-frequency = <100000000>;
 348                                 cdns,tshsl-ns = <1>;
 349                                 cdns,tsd2d-ns = <1>;
 350                                 cdns,tchsh-ns = <1>;
 351                                 cdns,tslch-ns = <1>;
 352
 353                                 partitions {
 354                                         compatible = "fixed-partitions";
 355                                         #address-cells = <1>;
 356                                         #size-cells = <1>;
 357
 358                                         spl@0 {
 359                                                 reg = <0x0 0x20000>;
 360                                         };
 361                                         uboot@100000 {
 362                                                 reg = <0x100000 0x300000>;
 363                                         };
 364                                         data@f00000 {
 365                                                 reg = <0xf00000 0x100000>;
 366                                         };
 367                                 };
 368                         };
 369                 };
 370
 371                 otp: otp@17050000 {
 372                         compatible = "starfive,jh7110-otp";
 373                         reg = <0x0 0x17050000 0x0 0x10000>;
 374                         clock-frequency = <4000000>;
 375                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 376                         clock-names = "apb";
 377                 };
 378
 379                 usbdrd30: usbdrd{
 380                         compatible = "starfive,jh7110-cdns3";
 381                         reg = <0x0 0x10210000 0x0 0x1000>,
 382                               <0x0 0x10200000 0x0 0x1000>;
 383                         clocks = <&clkgen JH7110_USB_125M>,
 384                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 385                                  <&clkgen JH7110_USB0_CLK_LPM>,
 386                                  <&clkgen JH7110_USB0_CLK_STB>,
 387                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 388                                  <&clkgen JH7110_USB0_CLK_AXI>,
 389                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 390                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 391                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 392                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 393                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 394                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 395                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 396                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 397                         reset-names = "pwrup","apb","axi","utmi", "phy";
 398                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 399                         starfive,sys-syscon = <&sys_syscon 0x18>;
 400                         status = "disabled";
 401                         #address-cells = <2>;
 402                         #size-cells = <2>;
 403                         #interrupt-cells = <1>;
 404                         ranges;
 405                         usbdrd_cdns3: usb@10100000 {
 406                                 compatible = "cdns,usb3";
 407                                 reg = <0x0 0x10100000 0x0 0x10000>,
 408                                       <0x0 0x10110000 0x0 0x10000>,
 409                                       <0x0 0x10120000 0x0 0x10000>;
 410                                 reg-names = "otg", "xhci", "dev";
 411                                 interrupts = <100>, <108>, <110>;
 412                                 interrupt-names = "host", "peripheral", "otg";
 413                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 414                                 maximum-speed = "super-speed";
 415                         };
 416                 };
 417
 418                 timer: timer@13050000 {
 419                         compatible = "starfive,jh7110-timers";
 420                         reg = <0x0 0x13050000 0x0 0x10000>;
 421                         interrupts = <69>, <70>, <71> ,<72>;
 422                         interrupt-names = "timer0", "timer1",
 423                                           "timer2", "timer3";
 424                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 425                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 426                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 427                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 428                                  <&clkgen JH7110_TIMER_CLK_APB>;
 429                         clock-names = "timer0", "timer1",
 430                                       "timer2", "timer3", "apb_clk";
 431                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 432                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 433                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 434                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 435                                  <&rstgen RSTN_U0_TIMER_APB>;
 436                         reset-names = "timer0", "timer1",
 437                                       "timer2", "timer3", "apb_rst";
 438                         clock-frequency = <24000000>;
 439                         status = "okay";
 440                 };
 441
 442                 wdog: wdog@13070000 {
 443                         compatible = "starfive,jh7110-wdt";
 444                         reg = <0x0 0x13070000 0x0 0x10000>;
 445                         interrupts = <68>;
 446                         interrupt-names = "wdog";
 447                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 448                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 449                         clock-names = "core_clk", "apb_clk";
 450                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 451                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 452                         reset-names = "rst_apb", "rst_core";
 453                         timeout-sec = <15>;
 454                         status = "okay";
 455                 };
 456
 457                 rtc: rtc@17040000 {
 458                         compatible = "starfive,jh7110-rtc";
 459                         reg = <0x0 0x17040000 0x0 0x10000>;
 460                         interrupts = <10>, <11>, <12>;
 461                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 462                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 463                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 464                         clock-names = "pclk", "cal_clk";
 465                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 466                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 467                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 468                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 469                         rtc,cal-clock-freq = <1000000>;
 470                         status = "okay";
 471                 };
 472
 473                 pwrc: power-controller@17030000 {
 474                         compatible = "starfive,jh7110-pmu";
 475                         reg = <0x0 0x17030000 0x0 0x10000>;
 476                         interrupts = <111>;
 477                         #power-domain-cells = <1>;
 478                         status = "okay";
 479                 };
 480
 481                 uart0: serial@10000000 {
 482                         compatible = "snps,dw-apb-uart";
 483                         reg = <0x0 0x10000000 0x0 0x10000>;
 484                         reg-io-width = <4>;
 485                         reg-shift = <2>;
 486                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 487                                  <&clkgen JH7110_UART0_CLK_APB>;
 488                         clock-names = "baudclk", "apb_pclk";
 489                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 490                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 491                         interrupts = <32>;
 492                         status = "disabled";
 493                 };
 494
 495                 uart1: serial@10010000 {
 496                         compatible = "snps,dw-apb-uart";
 497                         reg = <0x0 0x10010000 0x0 0x10000>;
 498                         reg-io-width = <4>;
 499                         reg-shift = <2>;
 500                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 501                                  <&clkgen JH7110_UART1_CLK_APB>;
 502                         clock-names = "baudclk", "apb_pclk";
 503                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 504                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 505                         interrupts = <33>;
 506                         status = "disabled";
 507                 };
 508
 509                 uart2: serial@10020000 {
 510                         compatible = "snps,dw-apb-uart";
 511                         reg = <0x0 0x10020000 0x0 0x10000>;
 512                         reg-io-width = <4>;
 513                         reg-shift = <2>;
 514                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 515                                  <&clkgen JH7110_UART2_CLK_APB>;
 516                         clock-names = "baudclk", "apb_pclk";
 517                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 518                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 519                         interrupts = <34>;
 520                         status = "disabled";
 521                 };
 522
 523                 uart3: serial@12000000 {
 524                         compatible = "snps,dw-apb-uart";
 525                         reg = <0x0 0x12000000 0x0 0x10000>;
 526                         reg-io-width = <4>;
 527                         reg-shift = <2>;
 528                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 529                                  <&clkgen JH7110_UART3_CLK_APB>;
 530                         clock-names = "baudclk", "apb_pclk";
 531                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 532                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 533                         interrupts = <45>;
 534                         status = "disabled";
 535                 };
 536
 537                 uart4: serial@12010000 {
 538                         compatible = "snps,dw-apb-uart";
 539                         reg = <0x0 0x12010000 0x0 0x10000>;
 540                         reg-io-width = <4>;
 541                         reg-shift = <2>;
 542                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 543                                  <&clkgen JH7110_UART4_CLK_APB>;
 544                         clock-names = "baudclk", "apb_pclk";
 545                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 546                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 547                         interrupts = <46>;
 548                         status = "disabled";
 549                 };
 550
 551                 uart5: serial@12020000 {
 552                         compatible = "snps,dw-apb-uart";
 553                         reg = <0x0 0x12020000 0x0 0x10000>;
 554                         reg-io-width = <4>;
 555                         reg-shift = <2>;
 556                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 557                                  <&clkgen JH7110_UART5_CLK_APB>;
 558                         clock-names = "baudclk", "apb_pclk";
 559                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 560                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 561                         interrupts = <47>;
 562                         status = "disabled";
 563                 };
 564
 565                 dma: dma-controller@16050000 {
 566                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 567                         reg = <0x0 0x16050000 0x0 0x10000>;
 568                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 569                                  <&clkgen JH7110_DMA1P_CLK_AHB>,
 570                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
 571                         clock-names = "core-clk", "cfgr-clk", "stg_clk";
 572                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 573                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>,
 574                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
 575                         reset-names = "rst_axi", "rst_ahb", "rst_stg";
 576                         interrupts = <73>;
 577                         #dma-cells = <2>;
 578                         dma-channels = <4>;
 579                         snps,dma-masters = <1>;
 580                         snps,data-width = <3>;
 581                         snps,num-hs-if = <56>;
 582                         snps,block-size = <65536 65536 65536 65536>;
 583                         snps,priority = <0 1 2 3>;
 584                         snps,axi-max-burst-len = <16>;
 585                         status = "disabled";
 586                 };
 587
 588                 gpio: gpio@13040000 {
 589                         compatible = "starfive,jh7110-sys-pinctrl";
 590                         reg = <0x0 0x13040000 0x0 0x10000>;
 591                         reg-names = "control";
 592                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 593                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 594                         interrupts = <86>;
 595                         interrupt-controller;
 596                         #gpio-cells = <2>;
 597                         ngpios = <64>;
 598                         status = "okay";
 599                 };
 600
 601                 gpioa: gpio@17020000 {
 602                         compatible = "starfive,jh7110-aon-pinctrl";
 603                         reg = <0x0 0x17020000 0x0 0x10000>;
 604                         reg-names = "control";
 605                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 606                         interrupts = <85>;
 607                         interrupt-controller;
 608                         #gpio-cells = <2>;
 609                         ngpios = <4>;
 610                         status = "okay";
 611                 };
 612
 613                 sfctemp: tmon@120e0000  {
 614                         compatible = "starfive,jh7110-temp";
 615                         reg = <0x0 0x120e0000 0x0 0x10000>;
 616                         interrupts = <81>;
 617                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 618                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 619                         clock-names = "sense", "bus";
 620                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 621                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 622                         reset-names = "sense", "bus";
 623                         #thermal-sensor-cells = <0>;
 624                         status = "disabled";
 625                 };
 626
 627                 thermal-zones {
 628                         cpu-thermal {
 629                                 polling-delay-passive = <250>;
 630                                 polling-delay = <15000>;
 631
 632                                 thermal-sensors = <&sfctemp>;
 633
 634                                 cooling-maps {
 635                                 };
 636
 637                                 trips {
 638                                         cpu_alert0: cpu_alert0 {
 639                                                 /* milliCelsius */
 640                                                 temperature = <75000>;
 641                                                 hysteresis = <2000>;
 642                                                 type = "passive";
 643                                         };
 644
 645                                         cpu_crit: cpu_crit {
 646                                                 /* milliCelsius */
 647                                                 temperature = <90000>;
 648                                                 hysteresis = <2000>;
 649                                                 type = "critical";
 650                                         };
 651                                 };
 652                         };
 653                 };
 654
 655                 trng: trng@1600C000 {
 656                         compatible = "starfive,jh7110-trng";
 657                         reg = <0x0 0x1600C000 0x0 0x4000>;
 658                         clocks = <&clkgen JH7110_SEC_HCLK>,
 659                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 660                         clock-names = "hclk", "ahb";
 661                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 662                         interrupts = <30>;
 663                         status = "disabled";
 664                 };
 665
 666                 sec_dma: sec_dma@16008000 {
 667                         compatible = "arm,pl080", "arm,primecell";
 668                         arm,primecell-periphid = <0x00041080>;
 669                         reg = <0x0 0x16008000 0x0 0x4000>;
 670                         reg-names = "sec_dma";
 671                         interrupts = <29>;
 672                         clocks = <&clkgen JH7110_SEC_HCLK>,
 673                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 674                         clock-names = "sec_hclk","apb_pclk";
 675                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 676                         reset-names = "sec_hre";
 677                         lli-bus-interface-ahb1;
 678                         mem-bus-interface-ahb1;
 679                         memcpy-burst-size = <256>;
 680                         memcpy-bus-width = <32>;
 681                         #dma-cells = <2>;
 682                         status = "disabled";
 683                 };
 684
 685                 crypto: crypto@16000000 {
 686                         compatible = "starfive,jh7110-sec";
 687                         reg = <0x0 0x16000000 0x0 0x4000>,
 688                               <0x0 0x16008000 0x0 0x4000>;
 689                         reg-names = "secreg","secdma";
 690                         interrupts = <28>, <29>;
 691                         interrupt-names = "secirq", "dmairq";
 692                         clocks = <&clkgen JH7110_SEC_HCLK>,
 693                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 694                         clock-names = "sec_hclk","sec_ahb";
 695                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 696                         reset-names = "sec_hre";
 697                         enable-side-channel-mitigation = "true";
 698                         enable-dma = "true";
 699                         dmas = <&sec_dma 1 2>,
 700                                <&sec_dma 0 2>;
 701                         dma-names = "sec_m","sec_p";
 702                         status = "disabled";
 703                 };
 704
 705                 i2c0: i2c@10030000 {
 706                         compatible = "snps,designware-i2c";
 707                         reg = <0x0 0x10030000 0x0 0x10000>;
 708                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 709                                  <&clkgen JH7110_I2C0_CLK_APB>;
 710                         clock-names = "ref", "pclk";
 711                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 712                         interrupts = <35>;
 713                         #address-cells = <1>;
 714                         #size-cells = <0>;
 715                         status = "disabled";
 716                 };
 717
 718                 i2c1: i2c@10040000 {
 719                         compatible = "snps,designware-i2c";
 720                         reg = <0x0 0x10040000 0x0 0x10000>;
 721                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 722                                  <&clkgen JH7110_I2C1_CLK_APB>;
 723                         clock-names = "ref", "pclk";
 724                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 725                         interrupts = <36>;
 726                         #address-cells = <1>;
 727                         #size-cells = <0>;
 728                         status = "disabled";
 729                 };
 730
 731                 i2c2: i2c@10050000 {
 732                         compatible = "snps,designware-i2c";
 733                         reg = <0x0 0x10050000 0x0 0x10000>;
 734                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 735                                  <&clkgen JH7110_I2C2_CLK_APB>;
 736                         clock-names = "ref", "pclk";
 737                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 738                         interrupts = <37>;
 739                         #address-cells = <1>;
 740                         #size-cells = <0>;
 741                         status = "disabled";
 742                 };
 743
 744                 i2c3: i2c@12030000 {
 745                         compatible = "snps,designware-i2c";
 746                         reg = <0x0 0x12030000 0x0 0x10000>;
 747                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 748                                  <&clkgen JH7110_I2C3_CLK_APB>;
 749                         clock-names = "ref", "pclk";
 750                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 751                         interrupts = <48>;
 752                         #address-cells = <1>;
 753                         #size-cells = <0>;
 754                         status = "disabled";
 755                 };
 756
 757                 i2c4: i2c@12040000 {
 758                         compatible = "snps,designware-i2c";
 759                         reg = <0x0 0x12040000 0x0 0x10000>;
 760                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 761                                  <&clkgen JH7110_I2C4_CLK_APB>;
 762                         clock-names = "ref", "pclk";
 763                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 764                         interrupts = <49>;
 765                         #address-cells = <1>;
 766                         #size-cells = <0>;
 767                         status = "disabled";
 768                 };
 769
 770                 i2c5: i2c@12050000 {
 771                         compatible = "snps,designware-i2c";
 772                         reg = <0x0 0x12050000 0x0 0x10000>;
 773                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 774                                  <&clkgen JH7110_I2C5_CLK_APB>;
 775                         clock-names = "ref", "pclk";
 776                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 777                         interrupts = <50>;
 778                         #address-cells = <1>;
 779                         #size-cells = <0>;
 780                         status = "disabled";
 781                 };
 782
 783                 i2c6: i2c@12060000 {
 784                         compatible = "snps,designware-i2c";
 785                         reg = <0x0 0x12060000 0x0 0x10000>;
 786                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 787                                  <&clkgen JH7110_I2C6_CLK_APB>;
 788                         clock-names = "ref", "pclk";
 789                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 790                         interrupts = <51>;
 791                         #address-cells = <1>;
 792                         #size-cells = <0>;
 793                         status = "disabled";
 794                 };
 795
 796                 /* unremovable emmc as mmcblk0 */
 797                 sdio0: sdio0@16010000 {
 798                         compatible = "starfive,jh7110-sdio";
 799                         reg = <0x0 0x16010000 0x0 0x10000>;
 800                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 801                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 802                         clock-names = "biu","ciu";
 803                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 804                         reset-names = "reset";
 805                         interrupts = <74>;
 806                         fifo-depth = <32>;
 807                         fifo-watermark-aligned;
 808                         data-addr = <0>;
 809                         starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
 810                         status = "disabled";
 811                 };
 812
 813                 sdio1: sdio1@16020000 {
 814                         compatible = "starfive,jh7110-sdio";
 815                         reg = <0x0 0x16020000 0x0 0x10000>;
 816                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 817                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 818                         clock-names = "biu","ciu";
 819                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 820                         reset-names = "reset";
 821                         interrupts = <75>;
 822                         fifo-depth = <32>;
 823                         fifo-watermark-aligned;
 824                         data-addr = <0>;
 825                         starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;
 826                         status = "disabled";
 827                 };
 828
 829                 vin_sysctl: vin_sysctl@19800000 {
 830                         compatible = "starfive,jh7110-vin";
 831                         reg = <0x0 0x19800000 0x0 0x10000>,
 832                                 <0x0 0x19810000 0x0 0x10000>,
 833                                 <0x0 0x19820000 0x0 0x10000>,
 834                                 <0x0 0x19840000 0x0 0x10000>,
 835                                 <0x0 0x19870000 0x0 0x30000>,
 836                                 <0x0 0x11840000 0x0 0x10000>,
 837                                 <0x0 0x17030000 0x0 0x10000>,
 838                                 <0x0 0x13020000 0x0 0x10000>;
 839                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 840                                 "isp", "trst", "pmu", "syscrg";
 841                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 842                                  <&clkisp JH7110_U0_VIN_PCLK>,
 843                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 844                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 845                                  <&clkisp JH7110_DVP_INV>,
 846                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 847                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 848                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 849                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 850                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 851                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 852                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 853                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 854                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 855                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 856                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
 857                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 858                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 859                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 860                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 861                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 862                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 863                                 "clk_ispcore_2x", "clk_isp_axi";
 864                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 865                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 866                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 867                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 868                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 869                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 870                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 871                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 872                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 873                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 874                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 875                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 876                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 877                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 878                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 879                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 880                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 881                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 882                                 "rst_isp_top_n", "rst_isp_top_axi";
 883                         starfive,aon-syscon = <&aon_syscon 0x00>;
 884                         power-domains = <&pwrc JH7110_PD_ISP>;
 885                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 886                         interrupts = <92 87 88 89 90>;
 887                         status = "disabled";
 888                 };
 889
 890                 jpu: jpu@11900000 {
 891                         compatible = "starfive,jpu";
 892                         reg = <0x0 0x13090000 0x0 0x300>;
 893                         interrupts = <14>;
 894                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 895                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 896                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 897                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 898                         clock-names = "axi_clk", "core_clk",
 899                                       "apb_clk", "noc_bus";
 900                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 901                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 902                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 903                         reset-names = "rst_axi", "rst_core", "rst_apb";
 904                         power-domains = <&pwrc JH7110_PD_VDEC>;
 905                         status = "disabled";
 906                 };
 907
 908                 vpu_dec: vpu_dec@130A0000 {
 909                         compatible = "starfive,vdec";
 910                         reg = <0x0 0x130A0000 0x0 0x10000>;
 911                         interrupts = <13>;
 912                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 913                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 914                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 915                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 916                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 917                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 918                                       "apb_clk", "noc_bus";
 919                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 920                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 921                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 922                                 <&rstgen RSTN_U0_WAVE511_APB>,
 923                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 924                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 925                                       "rst_apb", "rst_sram";
 926                         starfive,vdec_noc_ctrl;
 927                         power-domains = <&pwrc JH7110_PD_VDEC>;
 928                         status = "disabled";
 929                 };
 930
 931                 vpu_enc: vpu_enc@130B0000 {
 932                         compatible = "starfive,venc";
 933                         reg = <0x0 0x130B0000 0x0 0x10000>;
 934                         interrupts = <15>;
 935                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 936                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 937                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 938                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 939                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 940                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 941                                       "apb_clk", "noc_bus";
 942                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 943                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 944                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 945                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 946                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 947                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 948                                       "rst_apb", "rst_sram";
 949                         starfive,venc_noc_ctrl;
 950                         power-domains = <&pwrc JH7110_PD_VENC>;
 951                         status = "disabled";
 952                 };
 953
 954                 rstgen: reset-controller {
 955                         compatible = "starfive,jh7110-reset";
 956                         reg = <0x0 0x13020000 0x0 0x10000>,
 957                                 <0x0 0x10230000 0x0 0x10000>,
 958                                 <0x0 0x17000000 0x0 0x10000>,
 959                                 <0x0 0x19810000 0x0 0x10000>,
 960                                 <0x0 0x295C0000 0x0 0x10000>;
 961                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 962                         #reset-cells = <1>;
 963                         status = "okay";
 964                 };
 965
 966                 stmmac_axi_setup: stmmac-axi-config {
 967                         snps,wr_osr_lmt = <0xf>;
 968                         snps,rd_osr_lmt = <0xf>;
 969                         snps,blen = <256 128 64 32 0 0 0>;
 970                 };
 971
 972                 gmac0: ethernet@16030000 {
 973                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
 974                         reg = <0x0 0x16030000 0x0 0x10000>;
 975                         clock-names = "gtx",
 976                                 "tx",
 977                                 "ptp_ref",
 978                                 "stmmaceth",
 979                                 "pclk",
 980                                 "gtxc",
 981                                 "rmii_rtx";
 982                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 983                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 984                                  <&clkgen JH7110_GMAC0_PTP>,
 985                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 986                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 987                                  <&clkgen JH7110_GMAC0_GTXC>,
 988                                  <&clkgen JH7110_GMAC0_RMII_RTX>;
 989                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 990                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 991                         reset-names = "ahb", "stmmaceth";
 992                         interrupts = <7>, <6>, <5> ;
 993                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 994                         max-frame-size = <9000>;
 995                         phy-mode = "rgmii-id";
 996                         snps,multicast-filter-bins = <64>;
 997                         snps,perfect-filter-entries = <128>;
 998                         rx-fifo-depth = <2048>;
 999                         tx-fifo-depth = <2048>;
1000                         snps,fixed-burst;
1001                         snps,no-pbl-x8;
1002                         snps,force_thresh_dma_mode;
1003                         snps,axi-config = <&stmmac_axi_setup>;
1004                         snps,tso;
1005                         snps,en-tx-lpi-clockgating;
1006                         snps,en-lpi;
1007                         snps,write-requests = <4>;
1008                         snps,read-requests = <4>;
1009                         snps,burst-map = <0x7>;
1010                         snps,txpbl = <16>;
1011                         snps,rxpbl = <16>;
1012                         status = "disabled";
1013                 };
1014
1015                 gmac1: ethernet@16040000 {
1016                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
1017                         reg = <0x0 0x16040000 0x0 0x10000>;
1018                         clock-names = "gtx",
1019                                 "tx",
1020                                 "ptp_ref",
1021                                 "stmmaceth",
1022                                 "pclk",
1023                                 "gtxc",
1024                                 "rmii_rtx";
1025                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1026                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1027                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1028                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1029                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1030                                  <&clkgen JH7110_GMAC1_GTXC>,
1031                                  <&clkgen JH7110_GMAC1_RMII_RTX>;
1032                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1033                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1034                         reset-names = "ahb", "stmmaceth";
1035                         interrupts = <78>, <77>, <76> ;
1036                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1037                         max-frame-size = <9000>;
1038                         phy-mode = "rgmii-id";
1039                         snps,multicast-filter-bins = <64>;
1040                         snps,perfect-filter-entries = <128>;
1041                         rx-fifo-depth = <2048>;
1042                         tx-fifo-depth = <2048>;
1043                         snps,fixed-burst;
1044                         snps,no-pbl-x8;
1045                         snps,force_thresh_dma_mode;
1046                         snps,axi-config = <&stmmac_axi_setup>;
1047                         snps,tso;
1048                         snps,en-tx-lpi-clockgating;
1049                         snps,en-lpi;
1050                         snps,write-requests = <4>;
1051                         snps,read-requests = <4>;
1052                         snps,burst-map = <0x7>;
1053                         snps,txpbl = <16>;
1054                         snps,rxpbl = <16>;
1055                         status = "disabled";
1056                 };
1057
1058                 gpu: gpu@18000000 {
1059                         compatible = "img-gpu";
1060                         reg = <0x0 0x18000000 0x0 0x100000>,
1061                                 <0x0 0x130C000 0x0 0x10000>;
1062                         clocks = <&clkgen JH7110_GPU_CORE>,
1063                                  <&clkgen JH7110_GPU_CLK_APB>,
1064                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1065                                  <&clkgen JH7110_GPU_CORE_CLK>,
1066                                  <&clkgen JH7110_GPU_SYS_CLK>,
1067                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1068                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1069                                         "clk_core", "clk_sys", "clk_axi";
1070                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1071                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1072                         reset-names = "rst_apb", "rst_doma";
1073                         power-domains = <&pwrc JH7110_PD_GPUA>;
1074                         interrupts = <82>;
1075                         current-clock = <8000000>;
1076                         status = "disabled";
1077                 };
1078
1079                 can0: can@130d0000 {
1080                         compatible = "starfive,jh7110-can", "ipms,can";
1081                         reg = <0x0 0x130d0000 0x0 0x1000>;
1082                         interrupts = <112>;
1083                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1084                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1085                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1086                         clock-names = "apb_clk", "core_clk", "timer_clk";
1087                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1088                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1089                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1090                         reset-names = "rst_apb", "rst_core", "rst_timer";
1091                         frequency = <40000000>;
1092                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1093                         syscon,can_or_canfd = <0>;
1094                         status = "disabled";
1095                 };
1096
1097                 can1: can@130e0000 {
1098                         compatible = "starfive,jh7110-can", "ipms,can";
1099                         reg = <0x0 0x130e0000 0x0 0x1000>;
1100                         interrupts = <113>;
1101                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1102                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1103                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1104                         clock-names = "apb_clk", "core_clk", "timer_clk";
1105                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1106                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1107                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1108                         reset-names = "rst_apb", "rst_core", "rst_timer";
1109                         frequency = <40000000>;
1110                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1111                         syscon,can_or_canfd = <1>;
1112                         status = "disabled";
1113                 };
1114
1115                 tdm: tdm@10090000 {
1116                         compatible = "starfive,jh7110-tdm";
1117                         reg = <0x0 0x10090000 0x0 0x1000>;
1118                         reg-names = "tdm";
1119                         clocks = <&clkgen JH7110_AHB0>,
1120                                  <&clkgen JH7110_TDM_CLK_AHB>,
1121                                  <&clkgen JH7110_APB0>,
1122                                  <&clkgen JH7110_TDM_CLK_APB>,
1123                                  <&clkgen JH7110_TDM_INTERNAL>,
1124                                  <&tdm_ext>,
1125                                  <&clkgen JH7110_TDM_CLK_TDM>,
1126                                  <&clkgen JH7110_MCLK_INNER>;
1127                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1128                                       "clk_apb0", "clk_tdm_apb",
1129                                       "clk_tdm_internal", "clk_tdm_ext",
1130                                       "clk_tdm", "mclk_inner";
1131                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1132                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1133                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1134                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1135                         dmas = <&dma 20 1>, <&dma 21 1>;
1136                         dma-names = "rx","tx";
1137                         #sound-dai-cells = <0>;
1138                         status = "disabled";
1139                 };
1140
1141                 spdif0: spdif0@100a0000 {
1142                         compatible = "starfive,jh7110-spdif";
1143                         reg = <0x0 0x100a0000 0x0 0x1000>;
1144                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1145                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1146                                  <&clkgen JH7110_AUDIO_ROOT>,
1147                                  <&clkgen JH7110_MCLK_INNER>,
1148                                  <&mclk_ext>, <&clkgen JH7110_MCLK>;
1149                         clock-names = "spdif-apb", "spdif-core",
1150                                       "audroot", "mclk_inner",
1151                                       "mclk_ext", "mclk";
1152                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1153                         reset-names = "rst_apb";
1154                         interrupts = <84>;
1155                         interrupt-names = "tx";
1156                         #sound-dai-cells = <0>;
1157                         status = "disabled";
1158                 };
1159
1160                 pwmdac: pwmdac@100b0000 {
1161                         compatible = "starfive,jh7110-pwmdac";
1162                         reg = <0x0 0x100b0000 0x0 0x1000>;
1163                         clocks = <&clkgen JH7110_APB0>,
1164                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1165                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1166                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1167                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1168                         reset-names = "rst-apb";
1169                         dmas = <&dma 22 1>;
1170                         dma-names = "tx";
1171                         #sound-dai-cells = <0>;
1172                         status = "disabled";
1173                 };
1174
1175                 i2stx: i2stx@100c0000 {
1176                         compatible = "snps,designware-i2stx";
1177                         reg = <0x0 0x100c0000 0x0 0x1000>;
1178                         interrupt-names = "tx";
1179                         #sound-dai-cells = <0>;
1180                         dmas = <&dma 28 1>;
1181                         dma-names = "rx";
1182                         status = "disabled";
1183                 };
1184
1185                 pdm: pdm@100d0000 {
1186                         compatible = "starfive,jh7110-pdm";
1187                         reg = <0x0 0x100d0000 0x0 0x1000>;
1188                         reg-names = "pdm";
1189                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1190                                  <&clkgen JH7110_APB0>,
1191                                  <&clkgen JH7110_PDM_CLK_APB>,
1192                                  <&clkgen JH7110_MCLK>,
1193                                  <&mclk_ext>;
1194                         clock-names = "pdm_mclk", "clk_apb0",
1195                                       "pdm_apb", "clk_mclk",
1196                                       "mclk_ext";
1197                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1198                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1199                         reset-names = "pdm_dmic", "pdm_apb";
1200                         #sound-dai-cells = <0>;
1201                 };
1202
1203                 i2srx_mst: i2srx_mst@100e0000 {
1204                         compatible = "starfive,jh7110-i2srx-master";
1205                         reg = <0x0 0x100e0000 0x0 0x1000>;
1206                         clocks = <&clkgen JH7110_APB0>,
1207                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1208                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1209                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1210                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1211                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1212                         clock-names = "apb0", "i2srx_apb",
1213                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1214                                       "i2srx_bclk", "i2srx_lrck";
1215                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1216                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1217                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1218                         dmas = <&dma 24 1>;
1219                         dma-names = "rx";
1220                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1221                         #sound-dai-cells = <0>;
1222                         status = "disabled";
1223                 };
1224
1225                 i2srx_3ch: i2srx_3ch@100e0000 {
1226                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1227                         reg = <0x0 0x100e0000 0x0 0x1000>;
1228                         clocks = <&clkgen JH7110_APB0>,
1229                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1230                                  <&clkgen JH7110_AUDIO_ROOT>,
1231                                  <&clkgen JH7110_MCLK_INNER>,
1232                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1233                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1234                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1235                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1236                                  <&clkgen JH7110_MCLK>,
1237                                  <&i2srx_bclk_ext>,
1238                                  <&i2srx_lrck_ext>;
1239                         clock-names = "apb0", "3ch-apb",
1240                                       "audioroot", "mclk-inner",
1241                                       "bclk_mst", "3ch-lrck",
1242                                       "rx-bclk", "rx-lrck",
1243                                       "mclk", "bclk-ext",
1244                                       "lrck-ext";
1245                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1246                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1247                         dmas = <&dma 24 1>;
1248                         dma-names = "rx";
1249                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1250                         #sound-dai-cells = <0>;
1251                         status = "disabled";
1252                 };
1253
1254                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1255                         compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1256                         reg = <0x0 0x120b0000 0x0 0x1000>;
1257                         clocks = <&clkgen JH7110_MCLK_INNER>,
1258                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1259                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1260                                  <&clkgen JH7110_MCLK>,
1261                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1262                                  <&clkgen JH7110_I2STX0_4CHLRCK>,
1263                                  <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1264                                  <&mclk_ext>;
1265                         clock-names = "inner", "bclk-mst",
1266                                         "lrck-mst", "mclk",
1267                                         "bclk0", "lrck0",
1268                                         "i2s_apb", "mclk_ext";
1269                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1270                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1271                         reset-names = "rst_apb", "rst_bclk";
1272                         dmas = <&dma 47 1>;
1273                         dma-names = "tx";
1274                         #sound-dai-cells = <0>;
1275                         status = "disabled";
1276                 };
1277
1278                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1279                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1280                         reg = <0x0 0x120c0000 0x0 0x1000>;
1281                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1282                                  <&clkgen JH7110_MCLK_INNER>,
1283                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1284                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1285                                  <&clkgen JH7110_MCLK>,
1286                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1287                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1288                                  <&clkgen JH7110_MCLK_OUT>,
1289                                  <&clkgen JH7110_APB0>,
1290                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1291                                  <&mclk_ext>,
1292                                  <&i2stx_bclk_ext>,
1293                                  <&i2stx_lrck_ext>;
1294                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1295                                       "lrck_mst", "mclk", "4chbclk",
1296                                       "4chlrck", "mclk_out",
1297                                       "apb0", "clk_apb",
1298                                       "mclk_ext", "bclk_ext", "lrck_ext";
1299                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1300                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1301                         dmas = <&dma 48 1>;
1302                         dma-names = "tx";
1303                         #sound-dai-cells = <0>;
1304                         status = "disabled";
1305                 };
1306
1307                 ptc: pwm@120d0000 {
1308                         compatible = "starfive,jh7110-pwm";
1309                         reg = <0x0 0x120d0000 0x0 0x10000>;
1310                         reg-names = "control";
1311                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1312                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1313                         starfive,approx-freq = <2000000>;
1314                         #pwm-cells=<3>;
1315                         starfive,npwm = <8>;
1316                         status = "disabled";
1317                 };
1318
1319                 spdif_transmitter: spdif_transmitter {
1320                         compatible = "linux,spdif-dit";
1321                         #sound-dai-cells = <0>;
1322                         status = "disabled";
1323                 };
1324
1325                 pwmdac_codec: pwmdac-transmitter {
1326                         compatible = "starfive,jh7110-pwmdac-dit";
1327                         #sound-dai-cells = <0>;
1328                         status = "disabled";
1329                 };
1330
1331                 dmic_codec: dmic_codec {
1332                         compatible = "dmic-codec";
1333                         #sound-dai-cells = <0>;
1334                         status = "disabled";
1335                 };
1336
1337                 spi0: spi@10060000 {
1338                         compatible = "arm,pl022", "arm,primecell";
1339                         reg = <0x0 0x10060000 0x0 0x10000>;
1340                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1341                         clock-names = "apb_pclk";
1342                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1343                         reset-names = "rst_apb";
1344                         interrupts = <38>;
1345                         /* shortage of dma channel that not be used */
1346                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1347                         /*dma-names = "rx","tx";*/
1348                         arm,primecell-periphid = <0x00041022>;
1349                         num-cs = <1>;
1350                         #address-cells = <1>;
1351                         #size-cells = <0>;
1352                         status = "disabled";
1353                 };
1354
1355                 spi1: spi@10070000 {
1356                         compatible = "arm,pl022", "arm,primecell";
1357                         reg = <0x0 0x10070000 0x0 0x10000>;
1358                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1359                         clock-names = "apb_pclk";
1360                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1361                         reset-names = "rst_apb";
1362                         interrupts = <39>;
1363                         /* shortage of dma channel that not be used */
1364                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1365                         /*dma-names = "rx","tx";*/
1366                         arm,primecell-periphid = <0x00041022>;
1367                         num-cs = <1>;
1368                         #address-cells = <1>;
1369                         #size-cells = <0>;
1370                         status = "disabled";
1371                 };
1372
1373                 spi2: spi@10080000 {
1374                         compatible = "arm,pl022", "arm,primecell";
1375                         reg = <0x0 0x10080000 0x0 0x10000>;
1376                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1377                         clock-names = "apb_pclk";
1378                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1379                         reset-names = "rst_apb";
1380                         interrupts = <40>;
1381                         /* shortage of dma channel that not be used */
1382                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1383                         /*dma-names = "rx","tx";*/
1384                         arm,primecell-periphid = <0x00041022>;
1385                         num-cs = <1>;
1386                         #address-cells = <1>;
1387                         #size-cells = <0>;
1388                         status = "disabled";
1389                 };
1390
1391                 spi3: spi@12070000 {
1392                         compatible = "arm,pl022", "arm,primecell";
1393                         reg = <0x0 0x12070000 0x0 0x10000>;
1394                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1395                         clock-names = "apb_pclk";
1396                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1397                         reset-names = "rst_apb";
1398                         interrupts = <52>;
1399                         /* shortage of dma channel that not be used */
1400                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1401                         /*dma-names = "rx","tx";*/
1402                         arm,primecell-periphid = <0x00041022>;
1403                         num-cs = <1>;
1404                         #address-cells = <1>;
1405                         #size-cells = <0>;
1406                         status = "disabled";
1407                 };
1408
1409                 spi4: spi@12080000 {
1410                         compatible = "arm,pl022", "arm,primecell";
1411                         reg = <0x0 0x12080000 0x0 0x10000>;
1412                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1413                         clock-names = "apb_pclk";
1414                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1415                         reset-names = "rst_apb";
1416                         interrupts = <53>;
1417                         /* shortage of dma channel that not be used */
1418                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1419                         /*dma-names = "rx","tx";*/
1420                         arm,primecell-periphid = <0x00041022>;
1421                         num-cs = <1>;
1422                         #address-cells = <1>;
1423                         #size-cells = <0>;
1424                         status = "disabled";
1425                 };
1426
1427                 spi5: spi@12090000 {
1428                         compatible = "arm,pl022", "arm,primecell";
1429                         reg = <0x0 0x12090000 0x0 0x10000>;
1430                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1431                         clock-names = "apb_pclk";
1432                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1433                         reset-names = "rst_apb";
1434                         interrupts = <54>;
1435                         /* shortage of dma channel that not be used */
1436                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1437                         /*dma-names = "rx","tx";*/
1438                         arm,primecell-periphid = <0x00041022>;
1439                         num-cs = <1>;
1440                         #address-cells = <1>;
1441                         #size-cells = <0>;
1442                         status = "disabled";
1443                 };
1444
1445                 spi6: spi@120A0000 {
1446                         compatible = "arm,pl022", "arm,primecell";
1447                         reg = <0x0 0x120A0000 0x0 0x10000>;
1448                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1449                         clock-names = "apb_pclk";
1450                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1451                         reset-names = "rst_apb";
1452                         interrupts = <55>;
1453                         /* shortage of dma channel that not be used */
1454                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1455                         /*dma-names = "rx","tx";*/
1456                         arm,primecell-periphid = <0x00041022>;
1457                         num-cs = <1>;
1458                         #address-cells = <1>;
1459                         #size-cells = <0>;
1460                         status = "disabled";
1461                 };
1462
1463                 pcie0: pcie@2B000000 {
1464                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1465                         #address-cells = <3>;
1466                         #size-cells = <2>;
1467                         #interrupt-cells = <1>;
1468                         reg = <0x0 0x2B000000 0x0 0x1000000
1469                                0x9 0x40000000 0x0 0x10000000>;
1470                         reg-names = "reg", "config";
1471                         device_type = "pci";
1472                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1473                         bus-range = <0x0 0xff>;
1474                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1475                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1476                         msi-parent = <&plic>;
1477                         interrupts = <56>;
1478                         interrupt-controller;
1479                         interrupt-names = "msi";
1480                         interrupt-parent = <&plic>;
1481                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1482                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1483                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1484                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1485                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1486                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1487                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1488                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1489                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1490                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1491                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1492                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1493                                       "rst_brg", "rst_core", "rst_apb";
1494                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1495                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1496                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1497                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1498                         clock-names = "noc", "tl", "axi_mst0", "apb";
1499                         status = "disabled";
1500                 };
1501
1502                 pcie1: pcie@2C000000 {
1503                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1504                         #address-cells = <3>;
1505                         #size-cells = <2>;
1506                         #interrupt-cells = <1>;
1507                         reg = <0x0 0x2C000000 0x0 0x1000000
1508                                0x9 0xc0000000 0x0 0x10000000>;
1509                         reg-names = "reg", "config";
1510                         device_type = "pci";
1511                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1512                         bus-range = <0x0 0xff>;
1513                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1514                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1515                         msi-parent = <&plic>;
1516                         interrupts = <57>;
1517                         interrupt-controller;
1518                         interrupt-names = "msi";
1519                         interrupt-parent = <&plic>;
1520                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1521                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1522                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1523                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1524                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1525                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1526                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1527                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1528                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1529                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1530                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1531                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1532                                       "rst_brg", "rst_core", "rst_apb";
1533                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1534                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1535                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1536                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1537                         clock-names = "noc", "tl", "axi_mst0", "apb";
1538                         status = "disabled";
1539                 };
1540
1541                 mailbox_contrl0: mailbox@0 {
1542                         compatible = "starfive,mail_box";
1543                         reg = <0x0 0x13060000 0x0 0x0001000>;
1544                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1545                         clock-names = "clk_apb";
1546                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1547                         reset-names = "mbx_rre";
1548                         interrupts = <26 27>;
1549                         #mbox-cells = <2>;
1550                         status = "disabled";
1551                 };
1552
1553                 mailbox_client0: mailbox_client@0 {
1554                         compatible = "starfive,mailbox-test";
1555                         mbox-names = "rx", "tx";
1556                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1557                         status = "disabled";
1558                 };
1559
1560                 display: display-subsystem {
1561                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1562                         ports = <&dc_out_dpi0>;
1563                         status = "disabled";
1564                 };
1565
1566                 dssctrl: dssctrl@295B0000 {
1567                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1568                         reg = <0 0x295B0000 0 0x90>;
1569                 };
1570
1571                 tda988x_pin: tda988x_pin {
1572                         compatible = "starfive,tda998x_rgb_pin";
1573                         status = "disabled";
1574                 };
1575
1576                 rgb_output: rgb-output {
1577                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1578                         //verisilicon,dss-syscon = <&dssctrl>;
1579                         //verisilicon,mux-mask = <0x70 0x380>;
1580                         //verisilicon,mux-val = <0x40 0x280>;
1581                         status = "disabled";
1582                 };
1583
1584                 dc8200: dc8200@29400000 {
1585                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1586                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1587                         reg = <0x0 0x29400000 0x0 0x100>,
1588                               <0x0 0x29400800 0x0 0x2000>,
1589                               <0x0 0x17030000 0x0 0x1000>;
1590                         interrupts = <95>;
1591                         status = "disabled";
1592                         clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1593                         <&clkgen JH7110_VOUT_SRC>,
1594                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1595                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1596                         <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1597                         <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1598                         <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1599                         <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1600                         <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1601                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1602                         <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1603                         <&hdmitx0_pixelclk>,
1604                         <&clkvout JH7110_DC8200_PIX0>,
1605                         <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1606                         <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1607                         clock-names = "noc_disp","vout_src",
1608                            "top_vout_axi","top_vout_ahb",
1609                            "pix_clk","vout_pix1",
1610                            "axi_clk","core_clk","vout_ahb",
1611                            "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1612                            "dc8200_pix0_out","dc8200_pix1_out";
1613                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1614                                  <&rstgen RSTN_U0_DC8200_AXI>,
1615                                  <&rstgen RSTN_U0_DC8200_AHB>,
1616                                  <&rstgen RSTN_U0_DC8200_CORE>,
1617                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
1618                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1619                                         "rst_noc_disp";
1620                 };
1621
1622                 dsi_output: dsi-output {
1623                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1624                         status = "disabled";
1625                 };
1626
1627                 mipi_dphy: mipi-dphy@295e0000{
1628                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1629                         reg = <0x0 0x295e0000 0x0 0x10000>;
1630                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1631                         clock-names = "dphy_txesc";
1632                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1633                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1634                         reset-names = "dphy_sys", "dphy_txbytehs";
1635                         #phy-cells = <0>;
1636                         status = "disabled";
1637                 };
1638
1639                  mipi_dsi: mipi@295d0000 {
1640                         compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1641                         reg = <0x0 0x295d0000 0x0 0x10000>;
1642                         interrupts = <98>;
1643                         reg-names = "dsi";
1644                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1645                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1646                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1647                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1648                         clock-names = "sys", "apb", "txesc", "dpi";
1649                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1650                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1651                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1652                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1653                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1654                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1655                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1656                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1657                         phys = <&mipi_dphy>;
1658                         phy-names = "dphy";
1659                         status = "disabled";
1660
1661                 };
1662
1663                 hdmi: hdmi@29590000 {
1664                         compatible = "starfive,jh7110-hdmi","inno,hdmi";
1665                         reg = <0x0 0x29590000 0x0 0x4000>;
1666                         interrupts = <99>;
1667                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1668                         /*clocks = <&cru  PCLK_HDMI>;*/
1669                         /*clock-names = "pclk";*/
1670                         /*pinctrl-names = "default";*/
1671                         /*pinctrl-0 = <&hdmi_ctl>;*/
1672                         status = "disabled";
1673                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1674                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1675                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1676                                  <&hdmitx0_pixelclk>;
1677                         clock-names = "sysclk", "mclk","bclk","pclk";
1678                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1679                         reset-names = "hdmi_tx";
1680                         #sound-dai-cells = <0>;
1681                 };
1682
1683                 sound0: snd-card0 {
1684                         compatible = "simple-audio-card";
1685                         simple-audio-card,name = "Starfive-AC108-Sound-Card";
1686                         #address-cells = <1>;
1687                         #size-cells = <0>;
1688                 };
1689
1690                 sound1: snd-card1 {
1691                         compatible = "simple-audio-card";
1692                         simple-audio-card,name = "Starfive-HDMI-Sound-Card";
1693                         #address-cells = <1>;
1694                         #size-cells = <0>;
1695                 };
1696
1697                 sound2: snd-card2 {
1698                         compatible = "simple-audio-card";
1699                         simple-audio-card,name = "Starfive-PDM-Sound-Card";
1700                         #address-cells = <1>;
1701                         #size-cells = <0>;
1702                 };
1703
1704                 sound3: snd-card3 {
1705                         compatible = "simple-audio-card";
1706                         simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
1707                         #address-cells = <1>;
1708                         #size-cells = <0>;
1709                 };
1710
1711                 sound4: snd-card4 {
1712                         compatible = "simple-audio-card";
1713                         simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
1714                         #address-cells = <1>;
1715                         #size-cells = <0>;
1716                 };
1717
1718                 sound5: snd-card5 {
1719                         compatible = "simple-audio-card";
1720                         simple-audio-card,name = "Starfive-TDM-Sound-Card";
1721                         #address-cells = <1>;
1722                         #size-cells = <0>;
1723                 };
1724
1725                 sound6: snd-card6 {
1726                         compatible = "simple-audio-card";
1727                         simple-audio-card,name = "Starfive-WM8960-Sound-Card";
1728                         #address-cells = <1>;
1729                         #size-cells = <0>;
1730                 };
1731
1732                 co_process: e24@0 {
1733                         compatible = "starfive,e24";
1734                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1735                                 <0x0 0xc0111000 0x0 0x0001f000>;
1736                         reg-names = "ecmd", "espace";
1737                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1738                                  <&clkgen JH7110_E2_CLK_CORE>,
1739                                  <&clkgen JH7110_E2_CLK_DBG>;
1740                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1741                         resets = <&rstgen RSTN_U0_E24_CORE>;
1742                         reset-names = "e24_core";
1743                         starfive,stg-syscon = <&stg_syscon>;
1744                         interrupt-parent = <&plic>;
1745                         firmware-name = "e24_elf";
1746                         irq-mode = <1>;
1747                         mbox-names = "tx", "rx";
1748                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1749                         #address-cells = <1>;
1750                         #size-cells = <1>;
1751                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1752                         status = "disabled";
1753                         dsp@0 {};
1754                 };
1755
1756                 xrp: xrp@0 {
1757                         compatible = "cdns,xrp";
1758                         reg = <0x0  0x10230000 0x0 0x00010000
1759                                 0x0  0x10240000 0x0 0x00010000>;
1760                         memory-region = <&xrp_reserved>;
1761                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1762                         clock-names = "core_clk";
1763                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1764                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1765                         reset-names = "rst_core","rst_axi";
1766                         starfive,stg-syscon = <&stg_syscon>;
1767                         firmware-name = "hifi4_elf";
1768                         #address-cells = <1>;
1769                         #size-cells = <1>;
1770                         ranges = <0x40000000 0x0 0x20000000 0x040000
1771                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1772                         status = "disabled";
1773                         dsp@0 {
1774                         };
1775                 };
1776
1777                 starfive_cpufreq: starfive,jh7110-cpufreq {
1778                         compatible = "starfive,jh7110-cpufreq";
1779                         clocks = <&clkgen JH7110_CPU_CORE>;
1780                         clock-names = "cpu_clk";
1781                 };
1782         };
1783 };