arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cpus {
  21                 #address-cells = <1>;
  22                 #size-cells = <0>;
  23
  24                 cpu0: cpu@0 {
  25                         compatible = "sifive,u74-mc", "riscv";
  26                         reg = <0>;
  27                         d-cache-block-size = <64>;
  28                         d-cache-sets = <64>;
  29                         d-cache-size = <8192>;
  30                         d-tlb-sets = <1>;
  31                         d-tlb-size = <40>;
  32                         device_type = "cpu";
  33                         i-cache-block-size = <64>;
  34                         i-cache-sets = <64>;
  35                         i-cache-size = <16384>;
  36                         i-tlb-sets = <1>;
  37                         i-tlb-size = <40>;
  38                         mmu-type = "riscv,sv39";
  39                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  40                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  41                         next-level-cache = <&cachectrl>;
  42                         riscv,isa = "rv64imac";
  43                         tlb-split;
  44                         status = "disabled";
  45
  46                         cpu0intctrl: interrupt-controller {
  47                                 #interrupt-cells = <1>;
  48                                 compatible = "riscv,cpu-intc";
  49                                 interrupt-controller;
  50                         };
  51                 };
  52
  53                 cpu1: cpu@1 {
  54                         compatible = "sifive,u74-mc", "riscv";
  55                         reg = <1>;
  56                         d-cache-block-size = <64>;
  57                         d-cache-sets = <64>;
  58                         d-cache-size = <32768>;
  59                         d-tlb-sets = <1>;
  60                         d-tlb-size = <40>;
  61                         device_type = "cpu";
  62                         i-cache-block-size = <64>;
  63                         i-cache-sets = <64>;
  64                         i-cache-size = <32768>;
  65                         i-tlb-sets = <1>;
  66                         i-tlb-size = <40>;
  67                         mmu-type = "riscv,sv39";
  68                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  69                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  70                         next-level-cache = <&cachectrl>;
  71                         riscv,isa = "rv64imafdc";
  72                         tlb-split;
  73                         status = "okay";
  74
  75                         cpu1intctrl: interrupt-controller {
  76                                 #interrupt-cells = <1>;
  77                                 compatible = "riscv,cpu-intc";
  78                                 interrupt-controller;
  79                         };
  80                 };
  81
  82                 cpu2: cpu@2 {
  83                         compatible = "sifive,u74-mc", "riscv";
  84                         reg = <2>;
  85                         d-cache-block-size = <64>;
  86                         d-cache-sets = <64>;
  87                         d-cache-size = <32768>;
  88                         d-tlb-sets = <1>;
  89                         d-tlb-size = <40>;
  90                         device_type = "cpu";
  91                         i-cache-block-size = <64>;
  92                         i-cache-sets = <64>;
  93                         i-cache-size = <32768>;
  94                         i-tlb-sets = <1>;
  95                         i-tlb-size = <40>;
  96                         mmu-type = "riscv,sv39";
  97                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  98                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  99                         next-level-cache = <&cachectrl>;
 100                         riscv,isa = "rv64imafdc";
 101                         tlb-split;
 102                         status = "okay";
 103
 104                         cpu2intctrl: interrupt-controller {
 105                                 #interrupt-cells = <1>;
 106                                 compatible = "riscv,cpu-intc";
 107                                 interrupt-controller;
 108                         };
 109                 };
 110
 111                 cpu3: cpu@3 {
 112                         compatible = "sifive,u74-mc", "riscv";
 113                         reg = <3>;
 114                         d-cache-block-size = <64>;
 115                         d-cache-sets = <64>;
 116                         d-cache-size = <32768>;
 117                         d-tlb-sets = <1>;
 118                         d-tlb-size = <40>;
 119                         device_type = "cpu";
 120                         i-cache-block-size = <64>;
 121                         i-cache-sets = <64>;
 122                         i-cache-size = <32768>;
 123                         i-tlb-sets = <1>;
 124                         i-tlb-size = <40>;
 125                         mmu-type = "riscv,sv39";
 126                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 127                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 128                         next-level-cache = <&cachectrl>;
 129                         riscv,isa = "rv64imafdc";
 130                         tlb-split;
 131                         status = "okay";
 132
 133                         cpu3intctrl: interrupt-controller {
 134                                 #interrupt-cells = <1>;
 135                                 compatible = "riscv,cpu-intc";
 136                                 interrupt-controller;
 137                         };
 138                 };
 139
 140                 cpu4: cpu@4 {
 141                         compatible = "sifive,u74-mc", "riscv";
 142                         reg = <4>;
 143                         d-cache-block-size = <64>;
 144                         d-cache-sets = <64>;
 145                         d-cache-size = <32768>;
 146                         d-tlb-sets = <1>;
 147                         d-tlb-size = <40>;
 148                         device_type = "cpu";
 149                         i-cache-block-size = <64>;
 150                         i-cache-sets = <64>;
 151                         i-cache-size = <32768>;
 152                         i-tlb-sets = <1>;
 153                         i-tlb-size = <40>;
 154                         mmu-type = "riscv,sv39";
 155                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 156                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 157                         next-level-cache = <&cachectrl>;
 158                         riscv,isa = "rv64imafdc";
 159                         tlb-split;
 160                         status = "okay";
 161
 162                         cpu4intctrl: interrupt-controller {
 163                                 #interrupt-cells = <1>;
 164                                 compatible = "riscv,cpu-intc";
 165                                 interrupt-controller;
 166                         };
 167                 };
 168         };
 169
 170     idle-states {
 171         CPU_RET_0_0: cpu-retentive-0-0 {
 172             compatible = "riscv,idle-state";
 173             riscv,sbi-suspend-param = <0x10000000>;
 174             entry-latency-us = <20>;
 175             exit-latency-us = <40>;
 176             min-residency-us = <80>;
 177         };
 178
 179         CPU_NONRET_0_0: cpu-nonretentive-0-0 {
 180             compatible = "riscv,idle-state";
 181             riscv,sbi-suspend-param = <0x90000000>;
 182             entry-latency-us = <250>;
 183             exit-latency-us = <500>;
 184             min-residency-us = <950>;
 185         };
 186
 187         CLUSTER_RET_0: cluster-retentive-0 {
 188             compatible = "riscv,idle-state";
 189             riscv,sbi-suspend-param = <0x11000000>;
 190             local-timer-stop;
 191             entry-latency-us = <50>;
 192             exit-latency-us = <100>;
 193             min-residency-us = <250>;
 194             wakeup-latency-us = <130>;
 195         };
 196
 197         CLUSTER_NONRET_0: cluster-nonretentive-0 {
 198             compatible = "riscv,idle-state";
 199             riscv,sbi-suspend-param = <0x91000000>;
 200             local-timer-stop;
 201             entry-latency-us = <600>;
 202             exit-latency-us = <1100>;
 203             min-residency-us = <2700>;
 204             wakeup-latency-us = <1500>;
 205         };
 206         };
 207
 208         soc: soc {
 209                 compatible = "simple-bus";
 210                 interrupt-parent = <&plic>;
 211                 #address-cells = <2>;
 212                 #size-cells = <2>;
 213                 #clock-cells = <1>;
 214                 ranges;
 215
 216                 cachectrl: cache-controller@2010000 {
 217                         compatible = "sifive,fu740-c000-ccache", "cache";
 218                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 219                         reg-names = "control", "sideband";
 220                         interrupts = <1 3 4 2>;
 221                         cache-block-size = <64>;
 222                         cache-level = <2>;
 223                         cache-sets = <2048>;
 224                         cache-size = <2097152>;
 225                         cache-unified;
 226                 };
 227
 228                 aon_syscon: aon_syscon@17010000 {
 229                         compatible = "syscon";
 230                         reg = <0x0 0x17010000 0x0 0x1000>;
 231                 };
 232
 233                 stg_syscon: stg_syscon@10240000 {
 234                         compatible = "syscon";
 235                         reg = <0x0 0x10240000 0x0 0x1000>;
 236                 };
 237
 238                 sys_syscon: sys_syscon@13030000 {
 239                         compatible = "syscon";
 240                         reg = <0x0 0x13030000 0x0 0x1000>;
 241                 };
 242
 243                 clint: clint@2000000 {
 244                         compatible = "riscv,clint0";
 245                         reg = <0x0 0x2000000 0x0 0x10000>;
 246                         reg-names = "control";
 247                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 248                                                 &cpu1intctrl 3 &cpu1intctrl 7
 249                                                 &cpu2intctrl 3 &cpu2intctrl 7
 250                                                 &cpu3intctrl 3 &cpu3intctrl 7
 251                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 252                         #interrupt-cells = <1>;
 253                 };
 254
 255                 plic: plic@c000000 {
 256                         compatible = "riscv,plic0";
 257                         reg = <0x0 0xc000000 0x0 0x4000000>;
 258                         reg-names = "control";
 259                         interrupts-extended = <&cpu0intctrl 11
 260                                                 &cpu1intctrl 11 &cpu1intctrl 9
 261                                                 &cpu2intctrl 11 &cpu2intctrl 9
 262                                                 &cpu3intctrl 11 &cpu3intctrl 9
 263                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 264                         interrupt-controller;
 265                         #interrupt-cells = <1>;
 266                         riscv,max-priority = <7>;
 267                         riscv,ndev = <136>;
 268                 };
 269
 270                 clkgen: clock-controller {
 271                         compatible = "starfive,jh7110-clkgen";
 272                         reg = <0x0 0x13020000 0x0 0x10000>,
 273                                 <0x0 0x10230000 0x0 0x10000>,
 274                                 <0x0 0x17000000 0x0 0x10000>;
 275                         reg-names = "sys", "stg", "aon";
 276                         clocks = <&osc>, <&gmac1_rmii_refin>,
 277                                  <&gmac1_rgmii_rxin>,
 278                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 279                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 280                                  <&tdm_ext>, <&mclk_ext>,
 281                                  <&jtag_tck_inner>, <&bist_apb>,
 282                                  <&stg_apb>, <&clk_rtc>,
 283                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 284                         clock-names = "osc", "gmac1_rmii_refin",
 285                                 "gmac1_rgmii_rxin",
 286                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 287                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 288                                 "tdm_ext", "mclk_ext",
 289                                 "jtag_tck_inner", "bist_apb",
 290                                 "stg_apb", "clk_rtc",
 291                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 292                         #clock-cells = <1>;
 293                         status = "okay";
 294                 };
 295
 296                 clkvout: clock-controller@295C0000 {
 297                         compatible = "starfive,jh7110-clk-vout";
 298                         reg = <0x0 0x295C0000 0x0 0x10000>;
 299                         reg-names = "vout";
 300                         clocks = <&hdmitx0_pixelclk>,
 301                                  <&mipitx_dphy_rxesc>,
 302                                  <&mipitx_dphy_txbytehs>,
 303                                  <&clkgen JH7110_VOUT_SRC>,
 304                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 305                         clock-names = "hdmitx0_pixelclk",
 306                                       "mipitx_dphy_rxesc",
 307                                       "mipitx_dphy_txbytehs",
 308                                       "vout_src",
 309                                       "vout_top_ahb";
 310                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 311                         reset-names = "vout_src";
 312                         #clock-cells = <1>;
 313                         power-domains = <&pwrc JH7110_PD_VOUT>;
 314                         status = "okay";
 315                 };
 316
 317                 clkisp: clock-controller@19810000 {
 318                         compatible = "starfive,jh7110-clk-isp";
 319                         reg = <0x0 0x19810000 0x0 0x10000>;
 320                         reg-names = "isp";
 321                         #clock-cells = <1>;
 322                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 323                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 324                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 325                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 326                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 327                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 328                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 329                                       "u0_sft7110_noc_bus_clk_isp_axi";
 330                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 331                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 332                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 333                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 334                                       "rst_isp_noc_bus_n";
 335                         power-domains = <&pwrc JH7110_PD_ISP>;
 336                         status = "okay";
 337                 };
 338
 339                 qspi: spi@13010000 {
 340                         compatible = "cdns,qspi-nor";
 341                         #address-cells = <1>;
 342                         #size-cells = <0>;
 343                         reg = <0x0 0x13010000 0x0 0x10000
 344                                 0x0 0x21000000 0x0 0x400000>;
 345                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 346                         clock-names = "clk_ref";
 347                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 348                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 349                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 350                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 351                         cdns,fifo-depth = <256>;
 352                         cdns,fifo-width = <4>;
 353                         spi-max-frequency = <250000000>;
 354
 355                         nor_flash: nor-flash@0 {
 356                                 compatible = "jedec,spi-nor";
 357                                 reg=<0>;
 358                                 spi-max-frequency = <100000000>;
 359                                 cdns,tshsl-ns = <1>;
 360                                 cdns,tsd2d-ns = <1>;
 361                                 cdns,tchsh-ns = <1>;
 362                                 cdns,tslch-ns = <1>;
 363                         };
 364                 };
 365
 366                 otp: otp@17050000 {
 367                         compatible = "starfive,jh7110-otp";
 368                         reg = <0x0 0x17050000 0x0 0x10000>;
 369                         clock-frequency = <4000000>;
 370                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 371                         clock-names = "apb";
 372                 };
 373
 374                 usbdrd30: usbdrd{
 375                         compatible = "starfive,jh7110-cdns3";
 376                         clocks = <&clkgen JH7110_USB_125M>,
 377                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 378                                  <&clkgen JH7110_USB0_CLK_LPM>,
 379                                  <&clkgen JH7110_USB0_CLK_STB>,
 380                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 381                                  <&clkgen JH7110_USB0_CLK_AXI>,
 382                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 383                         clock-names = "125m","app","lpm","stb","apb","axi","utmi";
 384                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 385                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 386                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 387                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 388                         reset-names = "pwrup","apb","axi","utmi";
 389                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 390                         starfive,sys-syscon = <&sys_syscon 0x18>;
 391                         status = "disabled";
 392                         #address-cells = <2>;
 393                         #size-cells = <2>;
 394                         #interrupt-cells = <1>;
 395                         ranges;
 396                         usbdrd_cdns3: usb@10100000 {
 397                                 compatible = "cdns,usb3";
 398                                 reg = <0x0 0x10100000 0x0 0x10000>,
 399                                       <0x0 0x10110000 0x0 0x10000>,
 400                                       <0x0 0x10120000 0x0 0x10000>;
 401                                 reg-names = "otg", "xhci", "dev";
 402                                 interrupts = <100>, <109>, <110>;
 403                                 interrupt-names = "host", "peripheral", "otg";
 404                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 405                                 maximum-speed = "super-speed";
 406                         };
 407                 };
 408
 409                 timer: timer@13050000 {
 410                         compatible = "starfive,si5-timers";
 411                         reg = <0x0 0x13050000 0x0 0x10000>;
 412                         interrupts = <69>, <70>, <71> ,<72>;
 413                         interrupt-names = "timer0", "timer1",
 414                                           "timer2", "timer3";
 415                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 416                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 417                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 418                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 419                                  <&clkgen JH7110_TIMER_CLK_APB>;
 420                         clock-names = "timer0", "timer1",
 421                                       "timer2", "timer3", "apb_clk";
 422                         clock-frequency = <24000000>;
 423                         status = "okay";
 424                 };
 425
 426                 wdog: wdog@13070000 {
 427                         compatible = "starfive,dskit-wdt";
 428                         reg = <0x0 0x13070000 0x0 0x10000>;
 429                         interrupts = <68>;
 430                         interrupt-names = "wdog";
 431                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 432                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 433                         clock-names = "core_clk", "apb_clk";
 434                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 435                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 436                         reset-names = "rst_apb", "rst_core";
 437                         timeout-sec = <15>;
 438                         status = "okay";
 439                 };
 440
 441                 rtc: rtc@17040000 {
 442                         compatible = "starfive,rtc_hms";
 443                         reg = <0x0 0x17040000 0x0 0x10000>;
 444                         interrupts = <10>, <11>, <12>;
 445                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 446                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 447                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 448                         clock-names = "pclk", "cal_clk";
 449                         resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
 450                                  <&rstgen RSTN_U0_RTC_HMS_CAL>,
 451                                  <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
 452                         reset-names = "rst_apb", "rst_cal", "rst_osc";
 453                         rtc,cal-clock-freq = <1000000>;
 454                         status = "okay";
 455                 };
 456
 457                 pwrc: power-controller@17030000 {
 458                         compatible = "starfive,jh7110-pmu";
 459                         reg = <0x0 0x17030000 0x0 0x10000>;
 460                         interrupts = <111>;
 461                         #power-domain-cells = <1>;
 462                         status = "okay";
 463                 };
 464
 465                 uart0: serial@10000000 {
 466                         compatible = "snps,dw-apb-uart";
 467                         reg = <0x0 0x10000000 0x0 0x10000>;
 468                         reg-io-width = <4>;
 469                         reg-shift = <2>;
 470                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 471                                  <&clkgen JH7110_UART0_CLK_APB>;
 472                         clock-names = "baudclk", "apb_pclk";
 473                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 474                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 475                         interrupts = <32>;
 476                         status = "disabled";
 477                 };
 478
 479                 uart1: serial@10010000 {
 480                         compatible = "snps,dw-apb-uart";
 481                         reg = <0x0 0x10010000 0x0 0x10000>;
 482                         reg-io-width = <4>;
 483                         reg-shift = <2>;
 484                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 485                                  <&clkgen JH7110_UART1_CLK_APB>;
 486                         clock-names = "baudclk", "apb_pclk";
 487                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 488                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 489                         interrupts = <33>;
 490                         status = "disabled";
 491                 };
 492
 493                 uart2: serial@10020000 {
 494                         compatible = "snps,dw-apb-uart";
 495                         reg = <0x0 0x10020000 0x0 0x10000>;
 496                         reg-io-width = <4>;
 497                         reg-shift = <2>;
 498                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 499                                  <&clkgen JH7110_UART2_CLK_APB>;
 500                         clock-names = "baudclk", "apb_pclk";
 501                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 502                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 503                         interrupts = <34>;
 504                         status = "disabled";
 505                 };
 506
 507                 uart3: serial@12000000 {
 508                         compatible = "snps,dw-apb-uart";
 509                         reg = <0x0 0x12000000 0x0 0x10000>;
 510                         reg-io-width = <4>;
 511                         reg-shift = <2>;
 512                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 513                                  <&clkgen JH7110_UART3_CLK_APB>;
 514                         clock-names = "baudclk", "apb_pclk";
 515                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 516                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 517                         interrupts = <45>;
 518                         status = "disabled";
 519                 };
 520
 521                 uart4: serial@12010000 {
 522                         compatible = "snps,dw-apb-uart";
 523                         reg = <0x0 0x12010000 0x0 0x10000>;
 524                         reg-io-width = <4>;
 525                         reg-shift = <2>;
 526                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 527                                  <&clkgen JH7110_UART4_CLK_APB>;
 528                         clock-names = "baudclk", "apb_pclk";
 529                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 530                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 531                         interrupts = <46>;
 532                         status = "disabled";
 533                 };
 534
 535                 uart5: serial@12020000 {
 536                         compatible = "snps,dw-apb-uart";
 537                         reg = <0x0 0x12020000 0x0 0x10000>;
 538                         reg-io-width = <4>;
 539                         reg-shift = <2>;
 540                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 541                                  <&clkgen JH7110_UART5_CLK_APB>;
 542                         clock-names = "baudclk", "apb_pclk";
 543                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 544                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 545                         interrupts = <47>;
 546                         status = "disabled";
 547                 };
 548
 549                 dma: dma-controller@16050000 {
 550                         compatible = "starfive,axi-dma";
 551                         reg = <0x0 0x16050000 0x0 0x10000>;
 552                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 553                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 554                         clock-names = "core-clk", "cfgr-clk";
 555                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 556                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 557                         reset-names = "rst_axi", "rst_ahb";
 558                         interrupts = <73>;
 559                         #dma-cells = <2>;
 560                         dma-channels = <4>;
 561                         snps,dma-masters = <1>;
 562                         snps,data-width = <3>;
 563                         snps,num-hs-if = <56>;
 564                         snps,block-size = <65536 65536 65536 65536>;
 565                         snps,priority = <0 1 2 3>;
 566                         snps,axi-max-burst-len = <16>;
 567                         status = "disabled";
 568                 };
 569
 570                 gpio: gpio@13040000 {
 571                         compatible = "starfive,jh7110-sys-pinctrl";
 572                         reg = <0x0 0x13040000 0x0 0x10000>;
 573                         reg-names = "control";
 574                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 575                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 576                         interrupts = <86>;
 577                         interrupt-controller;
 578                         #gpio-cells = <2>;
 579                         ngpios = <64>;
 580                         status = "okay";
 581                 };
 582
 583                 gpioa: gpio@17020000 {
 584                         compatible = "starfive,jh7110-aon-pinctrl";
 585                         reg = <0x0 0x17020000 0x0 0x10000>;
 586                         reg-names = "control";
 587                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 588                         interrupts = <85>;
 589                         interrupt-controller;
 590                         #gpio-cells = <2>;
 591                         ngpios = <4>;
 592                         status = "okay";
 593                 };
 594
 595                 sfctemp: tmon@120e0000  {
 596                         compatible = "starfive,jh7110-temp";
 597                         reg = <0x0 0x120e0000 0x0 0x10000>;
 598                         interrupts = <81>;
 599                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 600                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 601                         clock-names = "sense", "bus";
 602                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 603                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 604                         reset-names = "sense", "bus";
 605                         #thermal-sensor-cells = <0>;
 606                         status = "disabled";
 607                 };
 608
 609                 thermal-zones {
 610                         cpu-thermal {
 611                                 polling-delay-passive = <250>;
 612                                 polling-delay = <15000>;
 613
 614                                 thermal-sensors = <&sfctemp>;
 615
 616                                 cooling-maps {
 617                                 };
 618
 619                                 trips {
 620                                         cpu_alert0: cpu_alert0 {
 621                                                 /* milliCelsius */
 622                                                 temperature = <75000>;
 623                                                 hysteresis = <2000>;
 624                                                 type = "passive";
 625                                         };
 626
 627                                         cpu_crit: cpu_crit {
 628                                                 /* milliCelsius */
 629                                                 temperature = <90000>;
 630                                                 hysteresis = <2000>;
 631                                                 type = "critical";
 632                                         };
 633                                 };
 634                         };
 635                 };
 636
 637                 trng: trng@1600C000 {
 638                         compatible = "starfive,trng";
 639                         reg = <0x0 0x1600C000 0x0 0x4000>;
 640                         clocks = <&clkgen JH7110_SEC_HCLK>,
 641                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 642                         clock-names = "hclk", "miscahb_clk";
 643                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 644                         interrupts = <30>;
 645                         status = "disabled";
 646                 };
 647
 648                 sec_dma: sec_dma@16008000 {
 649                         /*compatible = "arm,pl080", "arm,primecell";*/
 650                         compatible = "starfive,pl080";
 651                         reg = <0x0 0x16008000 0x0 0x4000>;
 652                         reg-names = "sec_dma";
 653                         interrupts = <29>;
 654                         clocks = <&clkgen JH7110_SEC_HCLK>,
 655                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 656                         clock-names = "sec_hclk","sec_ahb";
 657                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 658                         reset-names = "sec_hre";
 659                         lli-bus-interface-ahb1;
 660                         mem-bus-interface-ahb1;
 661                         memcpy-burst-size = <256>;
 662                         memcpy-bus-width = <32>;
 663                         #dma-cells = <2>;
 664                         status = "disabled";
 665                 };
 666
 667                 crypto: crypto@16000000 {
 668                         compatible = "starfive,jh7110-sec";
 669                         reg = <0x0 0x16000000 0x0 0x4000>,
 670                               <0x0 0x16008000 0x0 0x4000>;
 671                         reg-names = "secreg","secdma";
 672                         interrupts = <28>, <29>;
 673                         interrupt-names = "secirq", "dmairq";
 674                         clocks = <&clkgen JH7110_SEC_HCLK>,
 675                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 676                         clock-names = "sec_hclk","sec_ahb";
 677                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 678                         reset-names = "sec_hre";
 679                         enable-side-channel-mitigation = "true";
 680                         enable-dma = "true";
 681                         dmas = <&sec_dma 1 2>,
 682                                <&sec_dma 0 2>;
 683                         dma-names = "sec_m","sec_p";
 684                         status = "disabled";
 685                 };
 686
 687                 i2c0: i2c@10030000 {
 688                         compatible = "snps,designware-i2c";
 689                         reg = <0x0 0x10030000 0x0 0x10000>;
 690                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 691                                  <&clkgen JH7110_I2C0_CLK_APB>;
 692                         clock-names = "ref", "pclk";
 693                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 694                         interrupts = <35>;
 695                         #address-cells = <1>;
 696                         #size-cells = <0>;
 697                         status = "disabled";
 698                 };
 699
 700                 i2c1: i2c@10040000 {
 701                         compatible = "snps,designware-i2c";
 702                         reg = <0x0 0x10040000 0x0 0x10000>;
 703                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 704                                  <&clkgen JH7110_I2C1_CLK_APB>;
 705                         clock-names = "ref", "pclk";
 706                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 707                         interrupts = <36>;
 708                         #address-cells = <1>;
 709                         #size-cells = <0>;
 710                         status = "disabled";
 711                 };
 712
 713                 i2c2: i2c@10050000 {
 714                         compatible = "snps,designware-i2c";
 715                         reg = <0x0 0x10050000 0x0 0x10000>;
 716                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 717                                  <&clkgen JH7110_I2C2_CLK_APB>;
 718                         clock-names = "ref", "pclk";
 719                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 720                         interrupts = <37>;
 721                         #address-cells = <1>;
 722                         #size-cells = <0>;
 723                         status = "disabled";
 724                 };
 725
 726                 i2c3: i2c@12030000 {
 727                         compatible = "snps,designware-i2c";
 728                         reg = <0x0 0x12030000 0x0 0x10000>;
 729                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 730                                  <&clkgen JH7110_I2C3_CLK_APB>;
 731                         clock-names = "ref", "pclk";
 732                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 733                         interrupts = <48>;
 734                         #address-cells = <1>;
 735                         #size-cells = <0>;
 736                         status = "disabled";
 737                 };
 738
 739                 i2c4: i2c@12040000 {
 740                         compatible = "snps,designware-i2c";
 741                         reg = <0x0 0x12040000 0x0 0x10000>;
 742                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 743                                  <&clkgen JH7110_I2C4_CLK_APB>;
 744                         clock-names = "ref", "pclk";
 745                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 746                         interrupts = <49>;
 747                         #address-cells = <1>;
 748                         #size-cells = <0>;
 749                         status = "disabled";
 750                 };
 751
 752                 i2c5: i2c@12050000 {
 753                         compatible = "snps,designware-i2c";
 754                         reg = <0x0 0x12050000 0x0 0x10000>;
 755                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 756                                  <&clkgen JH7110_I2C5_CLK_APB>;
 757                         clock-names = "ref", "pclk";
 758                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 759                         interrupts = <50>;
 760                         #address-cells = <1>;
 761                         #size-cells = <0>;
 762                         status = "disabled";
 763                 };
 764
 765                 i2c6: i2c@12060000 {
 766                         compatible = "snps,designware-i2c";
 767                         reg = <0x0 0x12060000 0x0 0x10000>;
 768                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 769                                  <&clkgen JH7110_I2C6_CLK_APB>;
 770                         clock-names = "ref", "pclk";
 771                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 772                         interrupts = <51>;
 773                         #address-cells = <1>;
 774                         #size-cells = <0>;
 775                         status = "disabled";
 776                 };
 777
 778                 /* unremovable emmc as mmcblk0 */
 779                 sdio0: sdio0@16010000 {
 780                         compatible = "snps,dw-mshc";
 781                         reg = <0x0 0x16010000 0x0 0x10000>;
 782                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 783                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 784                         clock-names = "biu","ciu";
 785                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 786                         reset-names = "reset";
 787                         interrupts = <74>;
 788                         fifo-depth = <32>;
 789                         fifo-watermark-aligned;
 790                         data-addr = <0>;
 791                         status = "disabled";
 792                 };
 793
 794                 sdio1: sdio1@16020000 {
 795                         compatible = "snps,dw-mshc";
 796                         reg = <0x0 0x16020000 0x0 0x10000>;
 797                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 798                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 799                         clock-names = "biu","ciu";
 800                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 801                         reset-names = "reset";
 802                         interrupts = <75>;
 803                         fifo-depth = <32>;
 804                         fifo-watermark-aligned;
 805                         data-addr = <0>;
 806                         status = "disabled";
 807                 };
 808
 809                 vin_sysctl: vin_sysctl@19800000 {
 810                         compatible = "starfive,stf-vin";
 811                         reg = <0x0 0x19800000 0x0 0x10000>,
 812                                 <0x0 0x19810000 0x0 0x10000>,
 813                                 <0x0 0x19820000 0x0 0x10000>,
 814                                 <0x0 0x19830000 0x0 0x10000>,
 815                                 <0x0 0x19840000 0x0 0x10000>,
 816                                 <0x0 0x19870000 0x0 0x30000>,
 817                                 <0x0 0x11840000 0x0 0x10000>,
 818                                 <0x0 0x17030000 0x0 0x10000>,
 819                                 <0x0 0x13020000 0x0 0x10000>;
 820                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
 821                                 "isp", "trst", "pmu", "syscrg";
 822                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 823                                  <&clkisp JH7110_U0_VIN_PCLK>,
 824                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 825                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 826                                  <&clkisp JH7110_DVP_INV>,
 827                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 828                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 829                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 830                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 831                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 832                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 833                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 834                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 835                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 836                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 837                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 838                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 839                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 840                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 841                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 842                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 843                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 844                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 845                                 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
 846                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 847                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 848                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 849                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 850                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 851                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 852                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 853                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 854                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 855                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 856                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 857                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 858                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 859                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 860                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 861                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 862                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 863                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 864                                 "rst_isp_top_n", "rst_isp_top_axi";
 865                         starfive,aon-syscon = <&aon_syscon 0x00>;
 866                         power-domains = <&pwrc JH7110_PD_ISP>;
 867                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 868                         interrupts = <92 87 88 89 90>;
 869                         status = "disabled";
 870                 };
 871
 872                 jpu: jpu@11900000 {
 873                         compatible = "starfive,jpu";
 874                         reg = <0x0 0x13090000 0x0 0x300>;
 875                         interrupts = <14>;
 876                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 877                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 878                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 879                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 880                         clock-names = "axi_clk", "core_clk",
 881                                       "apb_clk", "noc_bus";
 882                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 883                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 884                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 885                         reset-names = "rst_axi", "rst_core", "rst_apb";
 886                         power-domains = <&pwrc JH7110_PD_VDEC>;
 887                         status = "disabled";
 888                 };
 889
 890                 vpu_dec: vpu_dec@130A0000 {
 891                         compatible = "starfive,vdec";
 892                         reg = <0x0 0x130A0000 0x0 0x10000>;
 893                         interrupts = <13>;
 894                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 895                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 896                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 897                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 898                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 899                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 900                                       "apb_clk", "noc_bus";
 901                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 902                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 903                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 904                                 <&rstgen RSTN_U0_WAVE511_APB>,
 905                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 906                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 907                                       "rst_apb", "rst_sram";
 908                         starfive,vdec_noc_ctrl;
 909                         power-domains = <&pwrc JH7110_PD_VDEC>;
 910                         status = "disabled";
 911                 };
 912
 913                 vpu_enc: vpu_enc@130B0000 {
 914                         compatible = "starfive,venc";
 915                         reg = <0x0 0x130B0000 0x0 0x10000>;
 916                         interrupts = <15>;
 917                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 918                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 919                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 920                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 921                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 922                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 923                                       "apb_clk", "noc_bus";
 924                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 925                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 926                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 927                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 928                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 929                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 930                                       "rst_apb", "rst_sram";
 931                         starfive,venc_noc_ctrl;
 932                         power-domains = <&pwrc JH7110_PD_VENC>;
 933                         status = "disabled";
 934                 };
 935
 936                 rstgen: reset-controller {
 937                         compatible = "starfive,jh7110-reset";
 938                         reg = <0x0 0x13020000 0x0 0x10000>,
 939                                 <0x0 0x10230000 0x0 0x10000>,
 940                                 <0x0 0x17000000 0x0 0x10000>,
 941                                 <0x0 0x19810000 0x0 0x10000>,
 942                                 <0x0 0x295C0000 0x0 0x10000>;
 943                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 944                         #reset-cells = <1>;
 945                         status = "okay";
 946                 };
 947
 948                 stmmac_axi_setup: stmmac-axi-config {
 949                         snps,wr_osr_lmt = <0xf>;
 950                         snps,rd_osr_lmt = <0xf>;
 951                         snps,blen = <256 128 64 32 0 0 0>;
 952                 };
 953
 954                 gmac0: ethernet@16030000 {
 955                         compatible = "starfive,jh7110-eqos-5.20";
 956                         reg = <0x0 0x16030000 0x0 0x10000>;
 957                         clock-names = "gtx",
 958                                 "tx",
 959                                 "ptp_ref",
 960                                 "stmmaceth",
 961                                 "pclk",
 962                                 "gtxc";
 963                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 964                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 965                                  <&clkgen JH7110_GMAC0_PTP>,
 966                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 967                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 968                                  <&clkgen JH7110_GMAC0_GTXC>;
 969                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 970                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 971                         reset-names = "ahb", "stmmaceth";
 972                         interrupts = <7>, <6>, <5> ;
 973                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 974                         max-frame-size = <9000>;
 975                         phy-mode = "rgmii-id";
 976                         snps,multicast-filter-bins = <64>;
 977                         snps,perfect-filter-entries = <128>;
 978                         rx-fifo-depth = <2048>;
 979                         tx-fifo-depth = <2048>;
 980                         snps,fixed-burst;
 981                         snps,no-pbl-x8;
 982                         snps,force_thresh_dma_mode;
 983                         snps,axi-config = <&stmmac_axi_setup>;
 984                         snps,tso;
 985                         snps,en-tx-lpi-clockgating;
 986                         snps,en-lpi;
 987                         snps,write-requests = <4>;
 988                         snps,read-requests = <4>;
 989                         snps,burst-map = <0x7>;
 990                         snps,txpbl = <16>;
 991                         snps,rxpbl = <16>;
 992                         status = "disabled";
 993                 };
 994
 995                 gmac1: ethernet@16040000 {
 996                         compatible = "starfive,jh7110-eqos-5.20";
 997                         reg = <0x0 0x16040000 0x0 0x10000>;
 998                         clock-names = "gtx",
 999                                 "tx",
1000                                 "ptp_ref",
1001                                 "stmmaceth",
1002                                 "pclk",
1003                                 "gtxc";
1004                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1005                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1006                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1007                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1008                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1009                                  <&clkgen JH7110_GMAC1_GTXC>;
1010                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1011                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1012                         reset-names = "ahb", "stmmaceth";
1013                         interrupts = <78>, <77>, <76> ;
1014                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1015                         max-frame-size = <9000>;
1016                         phy-mode = "rgmii-id";
1017                         snps,multicast-filter-bins = <64>;
1018                         snps,perfect-filter-entries = <128>;
1019                         rx-fifo-depth = <2048>;
1020                         tx-fifo-depth = <2048>;
1021                         snps,fixed-burst;
1022                         snps,no-pbl-x8;
1023                         snps,force_thresh_dma_mode;
1024                         snps,axi-config = <&stmmac_axi_setup>;
1025                         snps,tso;
1026                         snps,en-tx-lpi-clockgating;
1027                         snps,en-lpi;
1028                         snps,write-requests = <4>;
1029                         snps,read-requests = <4>;
1030                         snps,burst-map = <0x7>;
1031                         snps,txpbl = <16>;
1032                         snps,rxpbl = <16>;
1033                         status = "disabled";
1034                 };
1035
1036                 gpu: gpu@18000000 {
1037                         compatible = "img-gpu";
1038                         reg = <0x0 0x18000000 0x0 0x100000>,
1039                                 <0x0 0x130C000 0x0 0x10000>;
1040                         clocks = <&clkgen JH7110_GPU_CLK_APB>,
1041                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1042                                  <&clkgen JH7110_GPU_CORE_CLK>,
1043                                  <&clkgen JH7110_GPU_SYS_CLK>,
1044                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1045                         clock-names = "clk_apb", "clk_rtc", "clk_core",
1046                                         "clk_sys", "clk_axi";
1047                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1048                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1049                         reset-names = "rst_apb", "rst_doma";
1050                         power-domains = <&pwrc JH7110_PD_GPUA>;
1051                         interrupts = <82>;
1052                         current-clock = <8000000>;
1053                         status = "disabled";
1054                 };
1055
1056                 can0: can@130d0000 {
1057                         compatible = "ipms,can";
1058                         reg = <0x0 0x130d0000 0x0 0x1000>;
1059                         interrupts = <112>;
1060                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1061                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1062                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1063                         clock-names = "apb_clk", "core_clk", "timer_clk";
1064                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1065                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1066                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1067                         reset-names = "rst_apb", "rst_core", "rst_timer";
1068                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1069                         syscon,can_or_canfd = <0>;
1070                         status = "disabled";
1071                 };
1072
1073                 can1: can@130e0000 {
1074                         compatible = "ipms,can";
1075                         reg = <0x0 0x130e0000 0x0 0x1000>;
1076                         interrupts = <113>;
1077                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1078                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1079                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1080                         clock-names = "apb_clk", "core_clk", "timer_clk";
1081                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1082                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1083                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1084                         reset-names = "rst_apb", "rst_core", "rst_timer";
1085                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1086                         syscon,can_or_canfd = <0>;
1087                         status = "disabled";
1088                 };
1089
1090                 tdm: tdm@10090000 {
1091                         compatible = "starfive,sf-tdm";
1092                         reg = <0x0 0x10090000 0x0 0x1000>;
1093                         reg-names = "tdm";
1094                         clocks = <&clkgen JH7110_AHB0>,
1095                                  <&clkgen JH7110_TDM_CLK_AHB>,
1096                                  <&clkgen JH7110_APB0>,
1097                                  <&clkgen JH7110_TDM_CLK_APB>,
1098                                  <&clkgen JH7110_TDM_INTERNAL>,
1099                                  <&tdm_ext>,
1100                                  <&clkgen JH7110_TDM_CLK_TDM>,
1101                                  <&clkgen JH7110_MCLK_INNER>;
1102                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1103                                       "clk_apb0", "clk_tdm_apb",
1104                                       "clk_tdm_internal", "clk_tdm_ext",
1105                                       "clk_tdm", "mclk_inner";
1106                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1107                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1108                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1109                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1110                         dmas = <&dma 20 1>, <&dma 21 1>;
1111                         dma-names = "rx","tx";
1112                         #sound-dai-cells = <0>;
1113                         status = "disabled";
1114                 };
1115
1116                 spdif0: spdif0@100a0000 {
1117                         compatible = "starfive,sf-spdif";
1118                         reg = <0x0 0x100a0000 0x0 0x1000>;
1119                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1120                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1121                                  <&clkgen JH7110_APB0>,
1122                                  <&clkgen JH7110_AUDIO_ROOT>,
1123                                  <&clkgen JH7110_MCLK_INNER>;
1124                         clock-names = "spdif-apb", "spdif-core", "apb0",
1125                                       "audroot", "mclk_inner";
1126                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1127                         reset-names = "rst_apb";
1128                         interrupts = <84>;
1129                         interrupt-names = "tx";
1130                         #sound-dai-cells = <0>;
1131                         status = "disabled";
1132                 };
1133
1134                 pwmdac: pwmdac@100b0000 {
1135                         compatible = "starfive,pwmdac";
1136                         reg = <0x0 0x100b0000 0x0 0x1000>;
1137                         clocks = <&clkgen JH7110_APB0>,
1138                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1139                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1140                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1141                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1142                         reset-names = "rst-apb";
1143                         dmas = <&dma 22 1>;
1144                         dma-names = "tx";
1145                         #sound-dai-cells = <0>;
1146                         status = "disabled";
1147                 };
1148
1149                 i2stx: i2stx@100c0000 {
1150                         compatible = "snps,designware-i2stx";
1151                         reg = <0x0 0x100c0000 0x0 0x1000>;
1152                         interrupt-names = "tx";
1153                         #sound-dai-cells = <0>;
1154                         dmas = <&dma 28 1>;
1155                         dma-names = "rx";
1156                         status = "disabled";
1157                 };
1158
1159                 pdm: pdm@100d0000 {
1160                         compatible = "starfive,sf-pdm";
1161                         reg = <0x0 0x100d0000 0x0 0x1000>;
1162                         reg-names = "pdm";
1163                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1164                                  <&clkgen JH7110_APB0>,
1165                                  <&clkgen JH7110_PDM_CLK_APB>,
1166                                  <&clkgen JH7110_MCLK_INNER>,
1167                                  <&clkgen JH7110_MCLK>,
1168                                  <&clkgen JH7110_MCLK_OUT>;
1169                         clock-names = "pdm_mclk", "clk_apb0",
1170                                       "pdm_apb", "mclk_inner",
1171                                       "clk_mclk", "mclk_out";
1172                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1173                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1174                         reset-names = "pdm_dmic", "pdm_apb";
1175                         #sound-dai-cells = <0>;
1176                 };
1177
1178                 i2srx_mst: i2srx_mst@100e0000 {
1179                         compatible = "snps,i2srx-master";
1180                         reg = <0x0 0x100e0000 0x0 0x1000>;
1181                         clocks = <&clkgen JH7110_APB0>,
1182                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1183                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1184                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1185                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1186                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1187                         clock-names = "apb0", "i2srx_apb",
1188                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1189                                       "i2srx_bclk", "i2srx_lrck";
1190                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1191                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1192                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1193                         dmas = <&dma 24 1>;
1194                         dma-names = "rx";
1195                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1196                         #sound-dai-cells = <0>;
1197                         status = "disabled";
1198                 };
1199
1200                 i2srx_3ch: i2srx_3ch@100e0000 {
1201                         compatible = "snps,designware-i2srx";
1202                         reg = <0x0 0x100e0000 0x0 0x1000>;
1203                         clocks = <&clkgen JH7110_APB0>,
1204                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1205                                  <&clkgen JH7110_AUDIO_ROOT>,
1206                                  <&clkgen JH7110_MCLK_INNER>,
1207                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1208                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1209                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1210                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1211                         clock-names = "apb0", "3ch-apb",
1212                                         "audioroot", "mclk-inner",
1213                                         "bclk_mst", "3ch-lrck",
1214                                         "rx-bclk", "rx-lrck";
1215                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1216                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1217                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1218                         dmas = <&dma 24 1>;
1219                         dma-names = "rx";
1220                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1221                         #sound-dai-cells = <0>;
1222                         status = "disabled";
1223                 };
1224
1225                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1226                         compatible = "snps,designware-i2stx-4ch0";
1227                         reg = <0x0 0x120b0000 0x0 0x1000>;
1228                         clocks = <&clkgen JH7110_MCLK_INNER>,
1229                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1230                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1231                                  <&clkgen JH7110_MCLK>,
1232                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1233                                  <&clkgen JH7110_I2STX0_4CHLRCK>;
1234                         clock-names = "inner", "bclk-mst",
1235                                         "lrck-mst", "mclk",
1236                                         "bclk0", "lrck0";
1237                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1238                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1239                         reset-names = "rst_apb0", "rst_bclk0";
1240                         dmas = <&dma 47 1>;
1241                         dma-names = "tx";
1242                         #sound-dai-cells = <0>;
1243                         status = "disabled";
1244                 };
1245
1246                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1247                         compatible = "snps,designware-i2stx-4ch1";
1248                         reg = <0x0 0x120c0000 0x0 0x1000>;
1249                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1250                                  <&clkgen JH7110_MCLK_INNER>,
1251                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1252                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1253                                  <&clkgen JH7110_MCLK>,
1254                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1255                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1256                                  <&clkgen JH7110_MCLK_OUT>,
1257                                  <&clkgen JH7110_APB0>,
1258                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1259                                  <&mclk_ext>,
1260                                  <&i2stx_bclk_ext>,
1261                                  <&i2stx_lrck_ext>;
1262                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1263                                         "lrck_mst", "mclk", "4chbclk",
1264                                         "4chlrck", "mclk_out",
1265                                         "apb0", "clk_apb",
1266                                         "mclk_ext", "bclk_ext", "lrck_ext";
1267
1268                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1269                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1270                         reset-names = "rst_apb1", "rst_bclk1";
1271                         dmas = <&dma 48 1>;
1272                         dma-names = "tx";
1273                         #sound-dai-cells = <0>;
1274                         status = "disabled";
1275                 };
1276
1277                 ptc: pwm@120d0000 {
1278                         compatible = "starfive,pwm";
1279                         reg = <0x0 0x120d0000 0x0 0x10000>;
1280                         reg-names = "control";
1281                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1282                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1283                         starfive,approx-freq = <2000000>;
1284                         #pwm-cells=<3>;
1285                         starfive,npwm = <8>;
1286                         status = "disabled";
1287                 };
1288
1289                 spdif_transmitter: spdif_transmitter {
1290                         compatible = "linux,spdif-dit";
1291                         #sound-dai-cells = <0>;
1292                         status = "disabled";
1293                 };
1294
1295                 spdif_receiver: spdif_receiver {
1296                         compatible = "linux,spdif-dir";
1297                         #sound-dai-cells = <0>;
1298                         status = "disabled";
1299                 };
1300
1301                 pwmdac_codec: pwmdac-transmitter {
1302                         compatible = "linux,pwmdac-dit";
1303                         #sound-dai-cells = <0>;
1304                         status = "disabled";
1305                 };
1306
1307                 dmic_codec: dmic_codec {
1308                         compatible = "dmic-codec";
1309                         #sound-dai-cells = <0>;
1310                         status = "disabled";
1311                 };
1312
1313                 spi0: spi@10060000 {
1314                         compatible = "arm,pl022", "arm,primecell";
1315                         reg = <0x0 0x10060000 0x0 0x10000>;
1316                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1317                         clock-names = "apb_pclk";
1318                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1319                         reset-names = "rst_apb";
1320                         interrupts = <38>;
1321                         /* shortage of dma channel that not be used */
1322                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1323                         /*dma-names = "rx","tx";*/
1324                         arm,primecell-periphid = <0x00041022>;
1325                         num-cs = <1>;
1326                         #address-cells = <1>;
1327                         #size-cells = <0>;
1328                         status = "disabled";
1329                 };
1330
1331                 spi1: spi@10070000 {
1332                         compatible = "arm,pl022", "arm,primecell";
1333                         reg = <0x0 0x10070000 0x0 0x10000>;
1334                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1335                         clock-names = "apb_pclk";
1336                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1337                         reset-names = "rst_apb";
1338                         interrupts = <39>;
1339                         /* shortage of dma channel that not be used */
1340                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1341                         /*dma-names = "rx","tx";*/
1342                         arm,primecell-periphid = <0x00041022>;
1343                         num-cs = <1>;
1344                         #address-cells = <1>;
1345                         #size-cells = <0>;
1346                         status = "disabled";
1347                 };
1348
1349                 spi2: spi@10080000 {
1350                         compatible = "arm,pl022", "arm,primecell";
1351                         reg = <0x0 0x10080000 0x0 0x10000>;
1352                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1353                         clock-names = "apb_pclk";
1354                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1355                         reset-names = "rst_apb";
1356                         interrupts = <40>;
1357                         /* shortage of dma channel that not be used */
1358                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1359                         /*dma-names = "rx","tx";*/
1360                         arm,primecell-periphid = <0x00041022>;
1361                         num-cs = <1>;
1362                         #address-cells = <1>;
1363                         #size-cells = <0>;
1364                         status = "disabled";
1365                 };
1366
1367                 spi3: spi@12070000 {
1368                         compatible = "arm,pl022", "arm,primecell";
1369                         reg = <0x0 0x12070000 0x0 0x10000>;
1370                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1371                         clock-names = "apb_pclk";
1372                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1373                         reset-names = "rst_apb";
1374                         interrupts = <52>;
1375                         /* shortage of dma channel that not be used */
1376                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1377                         /*dma-names = "rx","tx";*/
1378                         arm,primecell-periphid = <0x00041022>;
1379                         num-cs = <1>;
1380                         #address-cells = <1>;
1381                         #size-cells = <0>;
1382                         status = "disabled";
1383                 };
1384
1385                 spi4: spi@12080000 {
1386                         compatible = "arm,pl022", "arm,primecell";
1387                         reg = <0x0 0x12080000 0x0 0x10000>;
1388                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1389                         clock-names = "apb_pclk";
1390                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1391                         reset-names = "rst_apb";
1392                         interrupts = <53>;
1393                         /* shortage of dma channel that not be used */
1394                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1395                         /*dma-names = "rx","tx";*/
1396                         arm,primecell-periphid = <0x00041022>;
1397                         num-cs = <1>;
1398                         #address-cells = <1>;
1399                         #size-cells = <0>;
1400                         status = "disabled";
1401                 };
1402
1403                 spi5: spi@12090000 {
1404                         compatible = "arm,pl022", "arm,primecell";
1405                         reg = <0x0 0x12090000 0x0 0x10000>;
1406                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1407                         clock-names = "apb_pclk";
1408                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1409                         reset-names = "rst_apb";
1410                         interrupts = <54>;
1411                         /* shortage of dma channel that not be used */
1412                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1413                         /*dma-names = "rx","tx";*/
1414                         arm,primecell-periphid = <0x00041022>;
1415                         num-cs = <1>;
1416                         #address-cells = <1>;
1417                         #size-cells = <0>;
1418                         status = "disabled";
1419                 };
1420
1421                 spi6: spi@120A0000 {
1422                         compatible = "arm,pl022", "arm,primecell";
1423                         reg = <0x0 0x120A0000 0x0 0x10000>;
1424                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1425                         clock-names = "apb_pclk";
1426                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1427                         reset-names = "rst_apb";
1428                         interrupts = <55>;
1429                         /* shortage of dma channel that not be used */
1430                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1431                         /*dma-names = "rx","tx";*/
1432                         arm,primecell-periphid = <0x00041022>;
1433                         num-cs = <1>;
1434                         #address-cells = <1>;
1435                         #size-cells = <0>;
1436                         status = "disabled";
1437                 };
1438
1439                 pcie0: pcie@2B000000 {
1440                         compatible = "plda,pci-xpressrich3-axi";
1441                         #address-cells = <3>;
1442                         #size-cells = <2>;
1443                         #interrupt-cells = <1>;
1444                         reg = <0x0 0x2B000000 0x0 0x1000000
1445                                0x9 0x40000000 0x0 0x10000000>;
1446                         reg-names = "reg", "config";
1447                         device_type = "pci";
1448                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1449                         bus-range = <0x0 0xff>;
1450                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>;
1451                         msi-parent = <&plic>;
1452                         interrupts = <56>;
1453                         interrupt-controller;
1454                         interrupt-names = "msi";
1455                         interrupt-parent = <&plic>;
1456                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1457                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1458                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1459                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1460                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1461                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1462                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1463                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1464                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1465                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1466                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1467                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1468                                       "rst_brg", "rst_core", "rst_apb";
1469                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1470                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1471                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1472                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1473                         clock-names = "noc", "tl", "axi_mst0", "apb";
1474                         status = "disabled";
1475                 };
1476
1477                 pcie1: pcie@2C000000 {
1478                         compatible = "plda,pci-xpressrich3-axi";
1479                         #address-cells = <3>;
1480                         #size-cells = <2>;
1481                         #interrupt-cells = <1>;
1482                         reg = <0x0 0x2C000000 0x0 0x1000000
1483                                0x9 0xc0000000 0x0 0x10000000>;
1484                         reg-names = "reg", "config";
1485                         device_type = "pci";
1486                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1487                         bus-range = <0x0 0xff>;
1488                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>;
1489                         msi-parent = <&plic>;
1490                         interrupts = <57>;
1491                         interrupt-controller;
1492                         interrupt-names = "msi";
1493                         interrupt-parent = <&plic>;
1494                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1495                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1496                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1497                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1498                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1499                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1500                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1501                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1502                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1503                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1504                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1505                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1506                                       "rst_brg", "rst_core", "rst_apb";
1507                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1508                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1509                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1510                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1511                         clock-names = "noc", "tl", "axi_mst0", "apb";
1512                         status = "disabled";
1513                 };
1514
1515                 mailbox_contrl0: mailbox@0 {
1516                         compatible = "starfive,mail_box";
1517                         reg = <0x0 0x13060000 0x0 0x0001000>;
1518                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1519                         clock-names = "clk_apb";
1520                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1521                         reset-names = "mbx_rre";
1522                         interrupts = <26 27>;
1523                         #mbox-cells = <2>;
1524                         status = "disabled";
1525                 };
1526
1527                 mailbox_client0: mailbox_client@0 {
1528                         compatible = "starfive,mailbox-test";
1529                         mbox-names = "rx", "tx";
1530                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1531                         status = "disabled";
1532                 };
1533
1534                 display: display-subsystem {
1535                         compatible = "verisilicon,display-subsystem";
1536                         ports = <&dc_out_dpi0>;
1537                         status = "disabled";
1538                 };
1539
1540                 dssctrl: dssctrl@295B0000 {
1541                         compatible = "verisilicon,dss-ctrl", "syscon";
1542                         reg = <0 0x295B0000 0 0x90>;
1543                 };
1544
1545                 tda988x_pin: tda988x_pin {
1546                         compatible = "starfive,tda998x_rgb_pin";
1547                         status = "disabled";
1548                 };
1549
1550                 hdmi_output: hdmi-output {
1551                         compatible = "verisilicon,hdmi-encoder";
1552                         //verisilicon,dss-syscon = <&dssctrl>;
1553                         //verisilicon,mux-mask = <0x70 0x380>;
1554                         //verisilicon,mux-val = <0x40 0x280>;
1555                         status = "disabled";
1556                 };
1557
1558                 dc8200: dc8200@29400000 {
1559                         compatible = "verisilicon,dc8200";
1560                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1561                         reg = <0x0 0x29400000 0x0 0x100>,
1562                               <0x0 0x29400800 0x0 0x2000>,
1563                               <0x0 0x17030000 0x0 0x1000>;
1564                         interrupts = <95>;
1565                         status = "disabled";
1566                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1567                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1568                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1569                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1570                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1571                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1572                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1573                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1574                                  <&clkgen JH7110_VOUT_SRC>,
1575                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1576                                  <&clkgen JH7110_AHB1>,
1577                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1578                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1579                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1580                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1581                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1582                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1583                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1584                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1585                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1586                                  <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1587                                  <&hdmitx0_pixelclk>,
1588                                  <&clkvout JH7110_DC8200_PIX0>,
1589                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1590                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1591                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1592                                         "noc_disp","noc_isp","noc_stg","vout_src",
1593                                         "top_vout_axi","ahb1","top_vout_ahb",
1594                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1595                                         "axi_clk","core_clk","vout_ahb",
1596                                         "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1597                                         "dc8200_pix0_out","dc8200_pix1_out";
1598                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1599                                  <&rstgen RSTN_U0_DC8200_AXI>,
1600                                  <&rstgen RSTN_U0_DC8200_AHB>,
1601                                  <&rstgen RSTN_U0_DC8200_CORE>,
1602                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1603                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1604                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1605                                  <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
1606                                  <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
1607                                  <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
1608                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1609                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
1610                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
1611                                  <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
1612                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1613                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1614                                         "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
1615                                         "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
1616                         power-domains = <&pwrc JH7110_PD_VOUT>;
1617                 };
1618
1619                 encoder: display-encoder {
1620                         compatible = "verisilicon,dsi-encoder";
1621                         status = "disabled";
1622                 };
1623
1624                 mipi_dphy: mipi-dphy@295e0000{
1625                         compatible = "starfive,jh7100-mipi-dphy-tx";
1626                         reg = <0x0 0x295e0000 0x0 0x10000>;
1627                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1628                         clock-names = "dphy_txesc";
1629                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1630                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1631                         reset-names = "dphy_sys", "dphy_txbytehs";
1632                         #phy-cells = <0>;
1633                         status = "disabled";
1634                 };
1635
1636                  mipi_dsi: mipi@295d0000 {
1637                         compatible = "cdns,dsi";
1638                         reg = <0x0 0x295d0000 0x0 0x10000>;
1639                         interrupts = <98>;
1640                         reg-names = "dsi";
1641                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1642                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1643                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1644                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1645                         clock-names = "sys", "apb", "txesc", "dpi";
1646                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1647                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1648                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1649                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1650                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1651                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1652                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1653                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1654                         phys = <&mipi_dphy>;
1655                         phy-names = "dphy";
1656                         status = "disabled";
1657
1658                         port {
1659                                 dsi_out_port: endpoint@0 {
1660                                         remote-endpoint = <&panel_dsi_port>;
1661                                 };
1662                                 dsi_in_port: endpoint@1 {
1663                                         remote-endpoint = <&mipi_out>;
1664                                 };
1665                         };
1666
1667                         mipi_panel: panel@0 {
1668                                 /*compatible = "";*/
1669                                 status = "okay";
1670                         };
1671                 };
1672
1673                 hdmi: hdmi@29590000 {
1674                         compatible = "rockchip,rk3036-inno-hdmi";
1675                         reg = <0x0 0x29590000 0x0 0x4000>;
1676                         interrupts = <99>;
1677                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1678                         /*clocks = <&cru  PCLK_HDMI>;*/
1679                         /*clock-names = "pclk";*/
1680                         /*pinctrl-names = "default";*/
1681                         /*pinctrl-0 = <&hdmi_ctl>;*/
1682                         status = "disabled";
1683                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1684                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1685                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1686                                  <&hdmitx0_pixelclk>;
1687                         clock-names = "sysclk", "mclk","bclk","pclk";
1688                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1689                         reset-names = "hdmi_tx";
1690                 };
1691
1692                 sound: snd-card {
1693                         compatible = "simple-audio-card";
1694                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1695                         #address-cells = <1>;
1696                         #size-cells = <0>;
1697                 };
1698
1699                 co_process: e24@0 {
1700                         compatible = "starfive,e24";
1701                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1702                                 <0x0 0xc0111000 0x0 0x0001f000>;
1703                         reg-names = "ecmd", "espace";
1704                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1705                                  <&clkgen JH7110_E2_CLK_CORE>,
1706                                  <&clkgen JH7110_E2_CLK_DBG>;
1707                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1708                         resets = <&rstgen RSTN_U0_E24_CORE>;
1709                         reset-names = "e24_core";
1710                         starfive,stg-syscon = <&stg_syscon>;
1711                         interrupt-parent = <&plic>;
1712                         firmware-name = "e24_elf";
1713                         irq-mode = <1>;
1714                         mbox-names = "tx", "rx";
1715                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1716                         #address-cells = <1>;
1717                         #size-cells = <1>;
1718                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1719                         status = "disabled";
1720                         dsp@0 {};
1721                 };
1722
1723                 xrp: xrp@0 {
1724                         compatible = "cdns,xrp";
1725                         reg = <0x0  0x10230000 0x0 0x00010000
1726                                 0x0  0x10240000 0x0 0x00010000>;
1727                         memory-region = <&xrp_reserved>;
1728                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1729                         clock-names = "core_clk";
1730                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1731                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1732                         reset-names = "rst_core","rst_axi";
1733                         starfive,stg-syscon = <&stg_syscon>;
1734                         firmware-name = "hifi4_elf";
1735                         #address-cells = <1>;
1736                         #size-cells = <1>;
1737                         ranges = <0x40000000 0x0 0x20000000 0x040000
1738                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1739                         status = "disabled";
1740                         dsp@0 {
1741                         };
1742                 };
1743         };
1744 };