1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Emil Renner Berthing <kernel@esmil.dk>
8 #include <dt-bindings/clock/starfive,jh7110-crg.h>
9 #include <dt-bindings/power/starfive,jh7110-pmu.h>
10 #include <dt-bindings/reset/starfive,jh7110-crg.h>
13 compatible = "starfive,jh7110";
22 compatible = "sifive,s7", "riscv";
24 d-cache-block-size = <64>;
26 d-cache-size = <8192>;
30 i-cache-block-size = <64>;
32 i-cache-size = <16384>;
35 mmu-type = "riscv,sv39";
36 next-level-cache = <&ccache>;
37 riscv,isa = "rv64imac_zba_zbb";
41 cpu0_intc: interrupt-controller {
42 compatible = "riscv,cpu-intc";
44 #interrupt-cells = <1>;
49 compatible = "sifive,u74-mc", "riscv";
51 d-cache-block-size = <64>;
53 d-cache-size = <32768>;
57 i-cache-block-size = <64>;
59 i-cache-size = <32768>;
62 mmu-type = "riscv,sv39";
63 next-level-cache = <&ccache>;
64 riscv,isa = "rv64imafdc_zba_zbb";
67 cpu1_intc: interrupt-controller {
68 compatible = "riscv,cpu-intc";
70 #interrupt-cells = <1>;
75 compatible = "sifive,u74-mc", "riscv";
77 d-cache-block-size = <64>;
79 d-cache-size = <32768>;
83 i-cache-block-size = <64>;
85 i-cache-size = <32768>;
88 mmu-type = "riscv,sv39";
89 next-level-cache = <&ccache>;
90 riscv,isa = "rv64imafdc_zba_zbb";
93 cpu2_intc: interrupt-controller {
94 compatible = "riscv,cpu-intc";
96 #interrupt-cells = <1>;
101 compatible = "sifive,u74-mc", "riscv";
103 d-cache-block-size = <64>;
105 d-cache-size = <32768>;
109 i-cache-block-size = <64>;
111 i-cache-size = <32768>;
114 mmu-type = "riscv,sv39";
115 next-level-cache = <&ccache>;
116 riscv,isa = "rv64imafdc_zba_zbb";
119 cpu3_intc: interrupt-controller {
120 compatible = "riscv,cpu-intc";
121 interrupt-controller;
122 #interrupt-cells = <1>;
127 compatible = "sifive,u74-mc", "riscv";
129 d-cache-block-size = <64>;
131 d-cache-size = <32768>;
135 i-cache-block-size = <64>;
137 i-cache-size = <32768>;
140 mmu-type = "riscv,sv39";
141 next-level-cache = <&ccache>;
142 riscv,isa = "rv64imafdc_zba_zbb";
145 cpu4_intc: interrupt-controller {
146 compatible = "riscv,cpu-intc";
147 interrupt-controller;
148 #interrupt-cells = <1>;
178 compatible = "fixed-clock";
179 clock-output-names = "dvp_clk";
183 gmac0_rgmii_rxin: gmac0-rgmii-rxin-clock {
184 compatible = "fixed-clock";
185 clock-output-names = "gmac0_rgmii_rxin";
189 gmac0_rmii_refin: gmac0-rmii-refin-clock {
190 compatible = "fixed-clock";
191 clock-output-names = "gmac0_rmii_refin";
195 gmac1_rgmii_rxin: gmac1-rgmii-rxin-clock {
196 compatible = "fixed-clock";
197 clock-output-names = "gmac1_rgmii_rxin";
201 gmac1_rmii_refin: gmac1-rmii-refin-clock {
202 compatible = "fixed-clock";
203 clock-output-names = "gmac1_rmii_refin";
207 hdmitx0_pixelclk: hdmitx0-pixel-clock {
208 compatible = "fixed-clock";
209 clock-output-names = "hdmitx0_pixelclk";
213 i2srx_bclk_ext: i2srx-bclk-ext-clock {
214 compatible = "fixed-clock";
215 clock-output-names = "i2srx_bclk_ext";
219 i2srx_lrck_ext: i2srx-lrck-ext-clock {
220 compatible = "fixed-clock";
221 clock-output-names = "i2srx_lrck_ext";
225 i2stx_bclk_ext: i2stx-bclk-ext-clock {
226 compatible = "fixed-clock";
227 clock-output-names = "i2stx_bclk_ext";
231 i2stx_lrck_ext: i2stx-lrck-ext-clock {
232 compatible = "fixed-clock";
233 clock-output-names = "i2stx_lrck_ext";
237 mclk_ext: mclk-ext-clock {
238 compatible = "fixed-clock";
239 clock-output-names = "mclk_ext";
244 compatible = "fixed-clock";
245 clock-output-names = "osc";
249 rtc_osc: rtc-oscillator {
250 compatible = "fixed-clock";
251 clock-output-names = "rtc_osc";
255 stmmac_axi_setup: stmmac-axi-config {
257 snps,wr_osr_lmt = <4>;
258 snps,rd_osr_lmt = <4>;
259 snps,blen = <256 128 64 32 0 0 0>;
262 tdm_ext: tdm-ext-clock {
263 compatible = "fixed-clock";
264 clock-output-names = "tdm_ext";
269 compatible = "simple-bus";
270 interrupt-parent = <&plic>;
271 #address-cells = <2>;
275 clint: timer@2000000 {
276 compatible = "starfive,jh7110-clint", "sifive,clint0";
277 reg = <0x0 0x2000000 0x0 0x10000>;
278 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
279 <&cpu1_intc 3>, <&cpu1_intc 7>,
280 <&cpu2_intc 3>, <&cpu2_intc 7>,
281 <&cpu3_intc 3>, <&cpu3_intc 7>,
282 <&cpu4_intc 3>, <&cpu4_intc 7>;
285 ccache: cache-controller@2010000 {
286 compatible = "starfive,jh7110-ccache", "sifive,ccache0", "cache";
287 reg = <0x0 0x2010000 0x0 0x4000>;
288 interrupts = <1>, <3>, <4>, <2>;
289 cache-block-size = <64>;
292 cache-size = <2097152>;
296 plic: interrupt-controller@c000000 {
297 compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
298 reg = <0x0 0xc000000 0x0 0x4000000>;
299 interrupts-extended = <&cpu0_intc 11>,
300 <&cpu1_intc 11>, <&cpu1_intc 9>,
301 <&cpu2_intc 11>, <&cpu2_intc 9>,
302 <&cpu3_intc 11>, <&cpu3_intc 9>,
303 <&cpu4_intc 11>, <&cpu4_intc 9>;
304 interrupt-controller;
305 #interrupt-cells = <1>;
306 #address-cells = <0>;
310 uart0: serial@10000000 {
311 compatible = "snps,dw-apb-uart";
312 reg = <0x0 0x10000000 0x0 0x10000>;
313 clocks = <&syscrg JH7110_SYSCLK_UART0_CORE>,
314 <&syscrg JH7110_SYSCLK_UART0_APB>;
315 clock-names = "baudclk", "apb_pclk";
316 resets = <&syscrg JH7110_SYSRST_UART0_APB>;
323 uart1: serial@10010000 {
324 compatible = "snps,dw-apb-uart";
325 reg = <0x0 0x10010000 0x0 0x10000>;
326 clocks = <&syscrg JH7110_SYSCLK_UART1_CORE>,
327 <&syscrg JH7110_SYSCLK_UART1_APB>;
328 clock-names = "baudclk", "apb_pclk";
329 resets = <&syscrg JH7110_SYSRST_UART1_APB>;
336 uart2: serial@10020000 {
337 compatible = "snps,dw-apb-uart";
338 reg = <0x0 0x10020000 0x0 0x10000>;
339 clocks = <&syscrg JH7110_SYSCLK_UART2_CORE>,
340 <&syscrg JH7110_SYSCLK_UART2_APB>;
341 clock-names = "baudclk", "apb_pclk";
342 resets = <&syscrg JH7110_SYSRST_UART2_APB>;
350 compatible = "snps,designware-i2c";
351 reg = <0x0 0x10030000 0x0 0x10000>;
352 clocks = <&syscrg JH7110_SYSCLK_I2C0_APB>;
354 resets = <&syscrg JH7110_SYSRST_I2C0_APB>;
356 #address-cells = <1>;
362 compatible = "snps,designware-i2c";
363 reg = <0x0 0x10040000 0x0 0x10000>;
364 clocks = <&syscrg JH7110_SYSCLK_I2C1_APB>;
366 resets = <&syscrg JH7110_SYSRST_I2C1_APB>;
368 #address-cells = <1>;
374 compatible = "snps,designware-i2c";
375 reg = <0x0 0x10050000 0x0 0x10000>;
376 clocks = <&syscrg JH7110_SYSCLK_I2C2_APB>;
378 resets = <&syscrg JH7110_SYSRST_I2C2_APB>;
380 #address-cells = <1>;
385 stgcrg: clock-controller@10230000 {
386 compatible = "starfive,jh7110-stgcrg";
387 reg = <0x0 0x10230000 0x0 0x10000>;
389 <&syscrg JH7110_SYSCLK_HIFI4_CORE>,
390 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
391 <&syscrg JH7110_SYSCLK_USB_125M>,
392 <&syscrg JH7110_SYSCLK_CPU_BUS>,
393 <&syscrg JH7110_SYSCLK_HIFI4_AXI>,
394 <&syscrg JH7110_SYSCLK_NOCSTG_BUS>,
395 <&syscrg JH7110_SYSCLK_APB_BUS>;
396 clock-names = "osc", "hifi4_core",
397 "stg_axiahb", "usb_125m",
398 "cpu_bus", "hifi4_axi",
399 "nocstg_bus", "apb_bus";
404 stg_syscon: syscon@10240000 {
405 compatible = "starfive,jh7110-stg-syscon", "syscon";
406 reg = <0x0 0x10240000 0x0 0x1000>;
409 uart3: serial@12000000 {
410 compatible = "snps,dw-apb-uart";
411 reg = <0x0 0x12000000 0x0 0x10000>;
412 clocks = <&syscrg JH7110_SYSCLK_UART3_CORE>,
413 <&syscrg JH7110_SYSCLK_UART3_APB>;
414 clock-names = "baudclk", "apb_pclk";
415 resets = <&syscrg JH7110_SYSRST_UART3_APB>;
422 uart4: serial@12010000 {
423 compatible = "snps,dw-apb-uart";
424 reg = <0x0 0x12010000 0x0 0x10000>;
425 clocks = <&syscrg JH7110_SYSCLK_UART4_CORE>,
426 <&syscrg JH7110_SYSCLK_UART4_APB>;
427 clock-names = "baudclk", "apb_pclk";
428 resets = <&syscrg JH7110_SYSRST_UART4_APB>;
435 uart5: serial@12020000 {
436 compatible = "snps,dw-apb-uart";
437 reg = <0x0 0x12020000 0x0 0x10000>;
438 clocks = <&syscrg JH7110_SYSCLK_UART5_CORE>,
439 <&syscrg JH7110_SYSCLK_UART5_APB>;
440 clock-names = "baudclk", "apb_pclk";
441 resets = <&syscrg JH7110_SYSRST_UART5_APB>;
449 compatible = "snps,designware-i2c";
450 reg = <0x0 0x12030000 0x0 0x10000>;
451 clocks = <&syscrg JH7110_SYSCLK_I2C3_APB>;
453 resets = <&syscrg JH7110_SYSRST_I2C3_APB>;
455 #address-cells = <1>;
461 compatible = "snps,designware-i2c";
462 reg = <0x0 0x12040000 0x0 0x10000>;
463 clocks = <&syscrg JH7110_SYSCLK_I2C4_APB>;
465 resets = <&syscrg JH7110_SYSRST_I2C4_APB>;
467 #address-cells = <1>;
473 compatible = "snps,designware-i2c";
474 reg = <0x0 0x12050000 0x0 0x10000>;
475 clocks = <&syscrg JH7110_SYSCLK_I2C5_APB>;
477 resets = <&syscrg JH7110_SYSRST_I2C5_APB>;
479 #address-cells = <1>;
485 compatible = "snps,designware-i2c";
486 reg = <0x0 0x12060000 0x0 0x10000>;
487 clocks = <&syscrg JH7110_SYSCLK_I2C6_APB>;
489 resets = <&syscrg JH7110_SYSRST_I2C6_APB>;
491 #address-cells = <1>;
497 compatible = "starfive,jh7110-pwm";
498 reg = <0x0 0x120d0000 0x0 0x10000>;
499 clocks = <&syscrg JH7110_SYSCLK_PWM_APB>;
500 resets = <&syscrg JH7110_SYSRST_PWM_APB>;
505 sfctemp: temperature-sensor@120e0000 {
506 compatible = "starfive,jh7110-temp";
507 reg = <0x0 0x120e0000 0x0 0x10000>;
508 clocks = <&syscrg JH7110_SYSCLK_TEMP_CORE>,
509 <&syscrg JH7110_SYSCLK_TEMP_APB>;
510 clock-names = "sense", "bus";
511 resets = <&syscrg JH7110_SYSRST_TEMP_CORE>,
512 <&syscrg JH7110_SYSRST_TEMP_APB>;
513 reset-names = "sense", "bus";
514 #thermal-sensor-cells = <0>;
518 compatible = "starfive,jh7110-qspi", "cdns,qspi-nor";
519 #address-cells = <1>;
521 reg = <0x0 0x13010000 0x0 0x10000
522 0x0 0x21000000 0x0 0x400000>;
524 clocks = <&syscrg JH7110_SYSCLK_QSPI_REF>;
525 resets = <&syscrg JH7110_SYSRST_QSPI_APB>,
526 <&syscrg JH7110_SYSRST_QSPI_AHB>,
527 <&syscrg JH7110_SYSRST_QSPI_REF>;
528 reset-names = "qspi", "qspi-ocp", "rstc_ref";
529 cdns,fifo-depth = <256>;
530 cdns,fifo-width = <4>;
531 cdns,trigger-address = <0x0>;
533 nor_flash: nor-flash@0 {
534 compatible = "jedec,spi-nor";
536 cdns,read-delay = <5>;
537 spi-max-frequency = <12000000>;
544 compatible = "fixed-partitions";
545 #address-cells = <1>;
552 reg = <0x100000 0x300000>;
555 reg = <0xf00000 0x100000>;
561 syscrg: clock-controller@13020000 {
562 compatible = "starfive,jh7110-syscrg";
563 reg = <0x0 0x13020000 0x0 0x10000>;
564 clocks = <&osc>, <&gmac1_rmii_refin>,
566 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
567 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
568 <&tdm_ext>, <&mclk_ext>,
569 <&pllclk JH7110_CLK_PLL0_OUT>,
570 <&pllclk JH7110_CLK_PLL1_OUT>,
571 <&pllclk JH7110_CLK_PLL2_OUT>;
572 clock-names = "osc", "gmac1_rmii_refin",
574 "i2stx_bclk_ext", "i2stx_lrck_ext",
575 "i2srx_bclk_ext", "i2srx_lrck_ext",
576 "tdm_ext", "mclk_ext",
577 "pll0_out", "pll1_out", "pll2_out";
582 sys_syscon: syscon@13030000 {
583 compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
584 reg = <0x0 0x13030000 0x0 0x1000>;
586 pllclk: pll-clock-controller {
587 compatible = "starfive,jh7110-pll";
593 sysgpio: pinctrl@13040000 {
594 compatible = "starfive,jh7110-sys-pinctrl";
595 reg = <0x0 0x13040000 0x0 0x10000>;
596 clocks = <&syscrg JH7110_SYSCLK_IOMUX_APB>;
597 resets = <&syscrg JH7110_SYSRST_IOMUX_APB>;
599 interrupt-controller;
600 #interrupt-cells = <2>;
606 compatible = "starfive,jh7110-timer";
607 reg = <0x0 0x13050000 0x0 0x10000>;
608 interrupts = <69>, <70>, <71> ,<72>;
609 clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>,
610 <&syscrg JH7110_SYSCLK_TIMER0>,
611 <&syscrg JH7110_SYSCLK_TIMER1>,
612 <&syscrg JH7110_SYSCLK_TIMER2>,
613 <&syscrg JH7110_SYSCLK_TIMER3>;
614 clock-names = "apb", "ch0", "ch1",
616 resets = <&syscrg JH7110_SYSRST_TIMER_APB>,
617 <&syscrg JH7110_SYSRST_TIMER0>,
618 <&syscrg JH7110_SYSRST_TIMER1>,
619 <&syscrg JH7110_SYSRST_TIMER2>,
620 <&syscrg JH7110_SYSRST_TIMER3>;
621 reset-names = "apb", "ch0", "ch1",
625 wdog: watchdog@13070000 {
626 compatible = "starfive,jh7110-wdt";
627 reg = <0x0 0x13070000 0x0 0x10000>;
628 clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
629 <&syscrg JH7110_SYSCLK_WDT_CORE>;
630 clock-names = "apb", "core";
631 resets = <&syscrg JH7110_SYSRST_WDT_APB>,
632 <&syscrg JH7110_SYSRST_WDT_CORE>;
635 crypto: crypto@16000000 {
636 compatible = "starfive,jh7110-crypto";
637 reg = <0x0 0x16000000 0x0 0x4000>;
638 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
639 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
640 clock-names = "hclk", "ahb";
641 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
642 dmas = <&sdma 1 2>, <&sdma 0 2>;
643 dma-names = "tx", "rx";
647 compatible = "arm,pl080", "arm,primecell";
648 arm,primecell-periphid = <0x00041080>;
649 reg = <0x0 0x16008000 0x0 0x4000>;
651 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
652 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
653 clock-names = "hclk", "apb_pclk";
654 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
655 lli-bus-interface-ahb1;
656 mem-bus-interface-ahb1;
657 memcpy-burst-size = <256>;
658 memcpy-bus-width = <32>;
663 compatible = "starfive,jh7110-trng";
664 reg = <0x0 0x1600C000 0x0 0x4000>;
665 clocks = <&stgcrg JH7110_STGCLK_SEC_AHB>,
666 <&stgcrg JH7110_STGCLK_SEC_MISC_AHB>;
667 clock-names = "hclk", "ahb";
668 resets = <&stgcrg JH7110_STGRST_SEC_AHB>;
673 compatible = "starfive,jh7110-mmc";
674 reg = <0x0 0x16010000 0x0 0x10000>;
675 clocks = <&syscrg JH7110_SYSCLK_SDIO0_AHB>,
676 <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>;
677 clock-names = "biu","ciu";
678 resets = <&syscrg JH7110_SYSRST_SDIO0_AHB>;
679 reset-names = "reset";
682 fifo-watermark-aligned;
684 starfive,sysreg = <&sys_syscon 0x14 0x1a 0x7c000000>;
689 compatible = "starfive,jh7110-mmc";
690 reg = <0x0 0x16020000 0x0 0x10000>;
691 clocks = <&syscrg JH7110_SYSCLK_SDIO1_AHB>,
692 <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>;
693 clock-names = "biu","ciu";
694 resets = <&syscrg JH7110_SYSRST_SDIO1_AHB>;
695 reset-names = "reset";
698 fifo-watermark-aligned;
700 starfive,sysreg = <&sys_syscon 0x9c 0x1 0x3e>;
704 gmac0: ethernet@16030000 {
705 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
706 reg = <0x0 0x16030000 0x0 0x10000>;
707 clocks = <&aoncrg JH7110_AONCLK_GMAC0_AXI>,
708 <&aoncrg JH7110_AONCLK_GMAC0_AHB>,
709 <&syscrg JH7110_SYSCLK_GMAC0_PTP>,
710 <&aoncrg JH7110_AONCLK_GMAC0_TX_INV>,
711 <&syscrg JH7110_SYSCLK_GMAC0_GTXC>;
712 clock-names = "stmmaceth", "pclk", "ptp_ref",
714 resets = <&aoncrg JH7110_AONRST_GMAC0_AXI>,
715 <&aoncrg JH7110_AONRST_GMAC0_AHB>;
716 reset-names = "stmmaceth", "ahb";
717 interrupts = <7>, <6>, <5>;
718 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
719 snps,multicast-filter-bins = <64>;
720 snps,perfect-filter-entries = <8>;
721 rx-fifo-depth = <2048>;
722 tx-fifo-depth = <2048>;
725 snps,force_thresh_dma_mode;
726 snps,axi-config = <&stmmac_axi_setup>;
728 snps,en-tx-lpi-clockgating;
731 starfive,syscon = <&aon_syscon 0xc 0x12>;
735 gmac1: ethernet@16040000 {
736 compatible = "starfive,jh7110-dwmac", "snps,dwmac-5.20";
737 reg = <0x0 0x16040000 0x0 0x10000>;
738 clocks = <&syscrg JH7110_SYSCLK_GMAC1_AXI>,
739 <&syscrg JH7110_SYSCLK_GMAC1_AHB>,
740 <&syscrg JH7110_SYSCLK_GMAC1_PTP>,
741 <&syscrg JH7110_SYSCLK_GMAC1_TX_INV>,
742 <&syscrg JH7110_SYSCLK_GMAC1_GTXC>;
743 clock-names = "stmmaceth", "pclk", "ptp_ref",
745 resets = <&syscrg JH7110_SYSRST_GMAC1_AXI>,
746 <&syscrg JH7110_SYSRST_GMAC1_AHB>;
747 reset-names = "stmmaceth", "ahb";
748 interrupts = <78>, <77>, <76>;
749 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
750 snps,multicast-filter-bins = <64>;
751 snps,perfect-filter-entries = <8>;
752 rx-fifo-depth = <2048>;
753 tx-fifo-depth = <2048>;
756 snps,force_thresh_dma_mode;
757 snps,axi-config = <&stmmac_axi_setup>;
759 snps,en-tx-lpi-clockgating;
762 starfive,syscon = <&sys_syscon 0x90 0x2>;
766 dma: dma-controller@16050000 {
767 compatible = "starfive,jh7110-axi-dma";
768 reg = <0x0 0x16050000 0x0 0x10000>;
769 clocks = <&stgcrg JH7110_STGCLK_DMA1P_AXI>,
770 <&stgcrg JH7110_STGCLK_DMA1P_AHB>;
771 clock-names = "core-clk", "cfgr-clk";
772 resets = <&stgcrg JH7110_STGRST_DMA1P_AXI>,
773 <&stgcrg JH7110_STGRST_DMA1P_AHB>;
777 snps,dma-masters = <1>;
778 snps,data-width = <3>;
779 snps,block-size = <65536 65536 65536 65536>;
780 snps,priority = <0 1 2 3>;
781 snps,axi-max-burst-len = <16>;
784 aoncrg: clock-controller@17000000 {
785 compatible = "starfive,jh7110-aoncrg";
786 reg = <0x0 0x17000000 0x0 0x10000>;
787 clocks = <&osc>, <&gmac0_rmii_refin>,
789 <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
790 <&syscrg JH7110_SYSCLK_APB_BUS>,
791 <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
793 clock-names = "osc", "gmac0_rmii_refin",
794 "gmac0_rgmii_rxin", "stg_axiahb",
795 "apb_bus", "gmac0_gtxclk",
801 aon_syscon: syscon@17010000 {
802 compatible = "starfive,jh7110-aon-syscon", "syscon";
803 reg = <0x0 0x17010000 0x0 0x1000>;
806 aongpio: pinctrl@17020000 {
807 compatible = "starfive,jh7110-aon-pinctrl";
808 reg = <0x0 0x17020000 0x0 0x10000>;
809 resets = <&aoncrg JH7110_AONRST_IOMUX>;
811 interrupt-controller;
812 #interrupt-cells = <2>;
817 pwrc: power-controller@17030000 {
818 compatible = "starfive,jh7110-pmu";
819 reg = <0x0 0x17030000 0x0 0x10000>;
821 #power-domain-cells = <1>;
824 ispcrg: clock-controller@19810000 {
825 compatible = "starfive,jh7110-ispcrg";
826 reg = <0x0 0x19810000 0x0 0x10000>;
827 clocks = <&syscrg JH7110_SYSCLK_ISP_TOP_CORE>,
828 <&syscrg JH7110_SYSCLK_ISP_TOP_AXI>,
829 <&syscrg JH7110_SYSCLK_NOC_BUS_ISP_AXI>,
831 clock-names = "isp_top_core", "isp_top_axi",
832 "noc_bus_isp_axi", "dvp_clk";
833 resets = <&syscrg JH7110_SYSRST_ISP_TOP>,
834 <&syscrg JH7110_SYSRST_ISP_TOP_AXI>,
835 <&syscrg JH7110_SYSRST_NOC_BUS_ISP_AXI>;
838 power-domains = <&pwrc JH7110_PD_ISP>;
841 csi_phy: phy@19820000 {
842 compatible = "starfive,jh7110-dphy-rx";
843 reg = <0x0 0x19820000 0x0 0x10000>;
844 clocks = <&ispcrg JH7110_ISPCLK_M31DPHY_CFG_IN>,
845 <&ispcrg JH7110_ISPCLK_M31DPHY_REF_IN>,
846 <&ispcrg JH7110_ISPCLK_M31DPHY_TX_ESC_LAN0>;
847 clock-names = "cfg", "ref", "tx";
848 resets = <&ispcrg JH7110_ISPRST_M31DPHY_HW>,
849 <&ispcrg JH7110_ISPRST_M31DPHY_B09_AON>;
850 starfive,aon-syscon = <&aon_syscon 0x00>;
854 voutcrg: clock-controller@295c0000 {
855 compatible = "starfive,jh7110-voutcrg";
856 reg = <0x0 0x295c0000 0x0 0x10000>;
857 clocks = <&syscrg JH7110_SYSCLK_VOUT_SRC>,
858 <&syscrg JH7110_SYSCLK_VOUT_TOP_AHB>,
859 <&syscrg JH7110_SYSCLK_VOUT_TOP_AXI>,
860 <&syscrg JH7110_SYSCLK_VOUT_TOP_HDMITX0_MCLK>,
861 <&syscrg JH7110_SYSCLK_I2STX0_BCLK>,
863 clock-names = "vout_src", "vout_top_ahb",
864 "vout_top_axi", "vout_top_hdmitx0_mclk",
865 "i2stx0_bclk", "hdmitx0_pixelclk";
866 resets = <&syscrg JH7110_SYSRST_VOUT_TOP_SRC>;
869 power-domains = <&pwrc JH7110_PD_VOUT>;