arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <880000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <880000>;
  30                         };
  31                         opp-625000000 {
  32                                         opp-hz = /bits/ 64 <625000000>;
  33                                         opp-microvolt = <880000>;
  34                         };
  35                         opp-750000000 {
  36                                         opp-hz = /bits/ 64 <750000000>;
  37                                         opp-microvolt = <880000>;
  38                         };
  39                         opp-875000000 {
  40                                         opp-hz = /bits/ 64 <875000000>;
  41                                         opp-microvolt = <880000>;
  42                         };
  43                         opp-1000000000 {
  44                                         opp-hz = /bits/ 64 <1000000000>;
  45                                         opp-microvolt = <900000>;
  46                         };
  47                         opp-1250000000 {
  48                                         opp-hz = /bits/ 64 <1250000000>;
  49                                         opp-microvolt = <950000>;
  50                         };
  51                         opp-1375000000 {
  52                                         opp-hz = /bits/ 64 <1375000000>;
  53                                         opp-microvolt = <1000000>;
  54                         };
  55                         opp-1500000000 {
  56                                         opp-hz = /bits/ 64 <1500000000>;
  57                                         opp-microvolt = <1100000>;
  58                         };
  59                         opp-1625000000 {
  60                                         opp-hz = /bits/ 64 <1625000000>;
  61                                         opp-microvolt = <1100000>;
  62                         };
  63                         opp-1750000000 {
  64                                         opp-hz = /bits/ 64 <1750000000>;
  65                                         opp-microvolt = <1200000>;
  66                         };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <0>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <8192>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <16384>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
  89                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
  90                         next-level-cache = <&cachectrl>;
  91                         riscv,isa = "rv64imac";
  92                         tlb-split;
  93                         status = "disabled";
  94
  95                         cpu0intctrl: interrupt-controller {
  96                                 #interrupt-cells = <1>;
  97                                 compatible = "riscv,cpu-intc";
  98                                 interrupt-controller;
  99                         };
 100                 };
 101
 102                 cpu1: cpu@1 {
 103                         compatible = "sifive,u74-mc", "riscv";
 104                         reg = <1>;
 105                         d-cache-block-size = <64>;
 106                         d-cache-sets = <64>;
 107                         d-cache-size = <32768>;
 108                         d-tlb-sets = <1>;
 109                         d-tlb-size = <40>;
 110                         device_type = "cpu";
 111                         i-cache-block-size = <64>;
 112                         i-cache-sets = <64>;
 113                         i-cache-size = <32768>;
 114                         i-tlb-sets = <1>;
 115                         i-tlb-size = <40>;
 116                         mmu-type = "riscv,sv39";
 117                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 118                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 119                         next-level-cache = <&cachectrl>;
 120                         riscv,isa = "rv64imafdc";
 121                         tlb-split;
 122                         status = "okay";
 123                         operating-points-v2 = <&cluster0_opp>;
 124
 125                         cpu1intctrl: interrupt-controller {
 126                                 #interrupt-cells = <1>;
 127                                 compatible = "riscv,cpu-intc";
 128                                 interrupt-controller;
 129                         };
 130                 };
 131
 132                 cpu2: cpu@2 {
 133                         compatible = "sifive,u74-mc", "riscv";
 134                         reg = <2>;
 135                         d-cache-block-size = <64>;
 136                         d-cache-sets = <64>;
 137                         d-cache-size = <32768>;
 138                         d-tlb-sets = <1>;
 139                         d-tlb-size = <40>;
 140                         device_type = "cpu";
 141                         i-cache-block-size = <64>;
 142                         i-cache-sets = <64>;
 143                         i-cache-size = <32768>;
 144                         i-tlb-sets = <1>;
 145                         i-tlb-size = <40>;
 146                         mmu-type = "riscv,sv39";
 147                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 148                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 149                         next-level-cache = <&cachectrl>;
 150                         riscv,isa = "rv64imafdc";
 151                         tlb-split;
 152                         status = "okay";
 153                         operating-points-v2 = <&cluster0_opp>;
 154
 155                         cpu2intctrl: interrupt-controller {
 156                                 #interrupt-cells = <1>;
 157                                 compatible = "riscv,cpu-intc";
 158                                 interrupt-controller;
 159                         };
 160                 };
 161
 162                 cpu3: cpu@3 {
 163                         compatible = "sifive,u74-mc", "riscv";
 164                         reg = <3>;
 165                         d-cache-block-size = <64>;
 166                         d-cache-sets = <64>;
 167                         d-cache-size = <32768>;
 168                         d-tlb-sets = <1>;
 169                         d-tlb-size = <40>;
 170                         device_type = "cpu";
 171                         i-cache-block-size = <64>;
 172                         i-cache-sets = <64>;
 173                         i-cache-size = <32768>;
 174                         i-tlb-sets = <1>;
 175                         i-tlb-size = <40>;
 176                         mmu-type = "riscv,sv39";
 177                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 178                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 179                         next-level-cache = <&cachectrl>;
 180                         riscv,isa = "rv64imafdc";
 181                         tlb-split;
 182                         status = "okay";
 183                         operating-points-v2 = <&cluster0_opp>;
 184
 185                         cpu3intctrl: interrupt-controller {
 186                                 #interrupt-cells = <1>;
 187                                 compatible = "riscv,cpu-intc";
 188                                 interrupt-controller;
 189                         };
 190                 };
 191
 192                 cpu4: cpu@4 {
 193                         compatible = "sifive,u74-mc", "riscv";
 194                         reg = <4>;
 195                         d-cache-block-size = <64>;
 196                         d-cache-sets = <64>;
 197                         d-cache-size = <32768>;
 198                         d-tlb-sets = <1>;
 199                         d-tlb-size = <40>;
 200                         device_type = "cpu";
 201                         i-cache-block-size = <64>;
 202                         i-cache-sets = <64>;
 203                         i-cache-size = <32768>;
 204                         i-tlb-sets = <1>;
 205                         i-tlb-size = <40>;
 206                         mmu-type = "riscv,sv39";
 207                         cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
 208                             &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
 209                         next-level-cache = <&cachectrl>;
 210                         riscv,isa = "rv64imafdc";
 211                         tlb-split;
 212                         status = "okay";
 213                         operating-points-v2 = <&cluster0_opp>;
 214
 215                         cpu4intctrl: interrupt-controller {
 216                                 #interrupt-cells = <1>;
 217                                 compatible = "riscv,cpu-intc";
 218                                 interrupt-controller;
 219                         };
 220                 };
 221         };
 222
 223     idle-states {
 224         CPU_RET_0_0: cpu-retentive-0-0 {
 225             compatible = "riscv,idle-state";
 226             riscv,sbi-suspend-param = <0x10000000>;
 227             entry-latency-us = <20>;
 228             exit-latency-us = <40>;
 229             min-residency-us = <80>;
 230         };
 231
 232         CPU_NONRET_0_0: cpu-nonretentive-0-0 {
 233             compatible = "riscv,idle-state";
 234             riscv,sbi-suspend-param = <0x90000000>;
 235             entry-latency-us = <250>;
 236             exit-latency-us = <500>;
 237             min-residency-us = <950>;
 238         };
 239
 240         CLUSTER_RET_0: cluster-retentive-0 {
 241             compatible = "riscv,idle-state";
 242             riscv,sbi-suspend-param = <0x11000000>;
 243             local-timer-stop;
 244             entry-latency-us = <50>;
 245             exit-latency-us = <100>;
 246             min-residency-us = <250>;
 247             wakeup-latency-us = <130>;
 248         };
 249
 250         CLUSTER_NONRET_0: cluster-nonretentive-0 {
 251             compatible = "riscv,idle-state";
 252             riscv,sbi-suspend-param = <0x91000000>;
 253             local-timer-stop;
 254             entry-latency-us = <600>;
 255             exit-latency-us = <1100>;
 256             min-residency-us = <2700>;
 257             wakeup-latency-us = <1500>;
 258         };
 259         };
 260
 261         soc: soc {
 262                 compatible = "simple-bus";
 263                 interrupt-parent = <&plic>;
 264                 #address-cells = <2>;
 265                 #size-cells = <2>;
 266                 #clock-cells = <1>;
 267                 ranges;
 268
 269                 cachectrl: cache-controller@2010000 {
 270                         compatible = "sifive,fu740-c000-ccache", "cache";
 271                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 272                         reg-names = "control", "sideband";
 273                         interrupts = <1 3 4 2>;
 274                         cache-block-size = <64>;
 275                         cache-level = <2>;
 276                         cache-sets = <2048>;
 277                         cache-size = <2097152>;
 278                         cache-unified;
 279                 };
 280
 281                 aon_syscon: aon_syscon@17010000 {
 282                         compatible = "syscon";
 283                         reg = <0x0 0x17010000 0x0 0x1000>;
 284                 };
 285
 286                 stg_syscon: stg_syscon@10240000 {
 287                         compatible = "syscon";
 288                         reg = <0x0 0x10240000 0x0 0x1000>;
 289                 };
 290
 291                 sys_syscon: sys_syscon@13030000 {
 292                         compatible = "syscon";
 293                         reg = <0x0 0x13030000 0x0 0x1000>;
 294                 };
 295
 296                 clint: clint@2000000 {
 297                         compatible = "riscv,clint0";
 298                         reg = <0x0 0x2000000 0x0 0x10000>;
 299                         reg-names = "control";
 300                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 301                                                 &cpu1intctrl 3 &cpu1intctrl 7
 302                                                 &cpu2intctrl 3 &cpu2intctrl 7
 303                                                 &cpu3intctrl 3 &cpu3intctrl 7
 304                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 305                         #interrupt-cells = <1>;
 306                 };
 307
 308                 plic: plic@c000000 {
 309                         compatible = "riscv,plic0";
 310                         reg = <0x0 0xc000000 0x0 0x4000000>;
 311                         reg-names = "control";
 312                         interrupts-extended = <&cpu0intctrl 11
 313                                                 &cpu1intctrl 11 &cpu1intctrl 9
 314                                                 &cpu2intctrl 11 &cpu2intctrl 9
 315                                                 &cpu3intctrl 11 &cpu3intctrl 9
 316                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 317                         interrupt-controller;
 318                         #interrupt-cells = <1>;
 319                         riscv,max-priority = <7>;
 320                         riscv,ndev = <136>;
 321                 };
 322
 323                 clkgen: clock-controller {
 324                         compatible = "starfive,jh7110-clkgen";
 325                         reg = <0x0 0x13020000 0x0 0x10000>,
 326                                 <0x0 0x10230000 0x0 0x10000>,
 327                                 <0x0 0x17000000 0x0 0x10000>;
 328                         reg-names = "sys", "stg", "aon";
 329                         clocks = <&osc>, <&gmac1_rmii_refin>,
 330                                  <&gmac1_rgmii_rxin>,
 331                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 332                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 333                                  <&tdm_ext>, <&mclk_ext>,
 334                                  <&jtag_tck_inner>, <&bist_apb>,
 335                                  <&clk_rtc>,
 336                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 337                         clock-names = "osc", "gmac1_rmii_refin",
 338                                 "gmac1_rgmii_rxin",
 339                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 340                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 341                                 "tdm_ext", "mclk_ext",
 342                                 "jtag_tck_inner", "bist_apb",
 343                                 "clk_rtc",
 344                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 345                         #clock-cells = <1>;
 346                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 347                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 348                         status = "okay";
 349                 };
 350
 351                 clkvout: clock-controller@295C0000 {
 352                         compatible = "starfive,jh7110-clk-vout";
 353                         reg = <0x0 0x295C0000 0x0 0x10000>;
 354                         reg-names = "vout";
 355                         clocks = <&hdmitx0_pixelclk>,
 356                                  <&mipitx_dphy_rxesc>,
 357                                  <&mipitx_dphy_txbytehs>,
 358                                  <&clkgen JH7110_VOUT_SRC>,
 359                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 360                         clock-names = "hdmitx0_pixelclk",
 361                                       "mipitx_dphy_rxesc",
 362                                       "mipitx_dphy_txbytehs",
 363                                       "vout_src",
 364                                       "vout_top_ahb";
 365                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 366                         reset-names = "vout_src";
 367                         #clock-cells = <1>;
 368                         power-domains = <&pwrc JH7110_PD_VOUT>;
 369                         status = "okay";
 370                 };
 371
 372                 clkisp: clock-controller@19810000 {
 373                         compatible = "starfive,jh7110-clk-isp";
 374                         reg = <0x0 0x19810000 0x0 0x10000>;
 375                         reg-names = "isp";
 376                         #clock-cells = <1>;
 377                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 378                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 379                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 380                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 381                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 382                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 383                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 384                                       "u0_sft7110_noc_bus_clk_isp_axi";
 385                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 386                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 387                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 388                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 389                                       "rst_isp_noc_bus_n";
 390                         power-domains = <&pwrc JH7110_PD_ISP>;
 391                         status = "okay";
 392                 };
 393
 394                 qspi: spi@13010000 {
 395                         compatible = "cdns,qspi-nor";
 396                         #address-cells = <1>;
 397                         #size-cells = <0>;
 398                         reg = <0x0 0x13010000 0x0 0x10000
 399                                 0x0 0x21000000 0x0 0x400000>;
 400                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 401                         clock-names = "clk_ref";
 402                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 403                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 404                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 405                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 406                         cdns,fifo-depth = <256>;
 407                         cdns,fifo-width = <4>;
 408                         spi-max-frequency = <250000000>;
 409
 410                         nor_flash: nor-flash@0 {
 411                                 compatible = "jedec,spi-nor";
 412                                 reg=<0>;
 413                                 spi-max-frequency = <100000000>;
 414                                 cdns,tshsl-ns = <1>;
 415                                 cdns,tsd2d-ns = <1>;
 416                                 cdns,tchsh-ns = <1>;
 417                                 cdns,tslch-ns = <1>;
 418                         };
 419                 };
 420
 421                 otp: otp@17050000 {
 422                         compatible = "starfive,jh7110-otp";
 423                         reg = <0x0 0x17050000 0x0 0x10000>;
 424                         clock-frequency = <4000000>;
 425                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 426                         clock-names = "apb";
 427                 };
 428
 429                 usbdrd30: usbdrd{
 430                         compatible = "starfive,jh7110-cdns3";
 431                         reg = <0x0 0x10210000 0x0 0x1000>,
 432                               <0x0 0x10200000 0x0 0x1000>;
 433                         clocks = <&clkgen JH7110_USB_125M>,
 434                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 435                                  <&clkgen JH7110_USB0_CLK_LPM>,
 436                                  <&clkgen JH7110_USB0_CLK_STB>,
 437                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 438                                  <&clkgen JH7110_USB0_CLK_AXI>,
 439                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 440                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 441                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 442                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 443                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 444                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 445                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 446                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 447                         reset-names = "pwrup","apb","axi","utmi", "phy";
 448                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 449                         starfive,sys-syscon = <&sys_syscon 0x18>;
 450                         status = "disabled";
 451                         #address-cells = <2>;
 452                         #size-cells = <2>;
 453                         #interrupt-cells = <1>;
 454                         ranges;
 455                         usbdrd_cdns3: usb@10100000 {
 456                                 compatible = "cdns,usb3";
 457                                 reg = <0x0 0x10100000 0x0 0x10000>,
 458                                       <0x0 0x10110000 0x0 0x10000>,
 459                                       <0x0 0x10120000 0x0 0x10000>;
 460                                 reg-names = "otg", "xhci", "dev";
 461                                 interrupts = <100>, <108>, <110>;
 462                                 interrupt-names = "host", "peripheral", "otg";
 463                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 464                                 maximum-speed = "super-speed";
 465                         };
 466                 };
 467
 468                 timer: timer@13050000 {
 469                         compatible = "starfive,timers";
 470                         reg = <0x0 0x13050000 0x0 0x10000>;
 471                         interrupts = <69>, <70>, <71> ,<72>;
 472                         interrupt-names = "timer0", "timer1",
 473                                           "timer2", "timer3";
 474                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 475                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 476                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 477                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 478                                  <&clkgen JH7110_TIMER_CLK_APB>;
 479                         clock-names = "timer0", "timer1",
 480                                       "timer2", "timer3", "apb_clk";
 481                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 482                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 483                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 484                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 485                                  <&rstgen RSTN_U0_TIMER_APB>;
 486                         reset-names = "timer0", "timer1",
 487                                       "timer2", "timer3", "apb_rst";
 488                         clock-frequency = <24000000>;
 489                         status = "okay";
 490                 };
 491
 492                 wdog: wdog@13070000 {
 493                         compatible = "starfive,dskit-wdt";
 494                         reg = <0x0 0x13070000 0x0 0x10000>;
 495                         interrupts = <68>;
 496                         interrupt-names = "wdog";
 497                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 498                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 499                         clock-names = "core_clk", "apb_clk";
 500                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 501                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 502                         reset-names = "rst_apb", "rst_core";
 503                         timeout-sec = <15>;
 504                         status = "okay";
 505                 };
 506
 507                 rtc: rtc@17040000 {
 508                         compatible = "starfive,rtc_hms";
 509                         reg = <0x0 0x17040000 0x0 0x10000>;
 510                         interrupts = <10>, <11>, <12>;
 511                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 512                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 513                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 514                         clock-names = "pclk", "cal_clk";
 515                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 516                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 517                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 518                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 519                         rtc,cal-clock-freq = <1000000>;
 520                         status = "okay";
 521                 };
 522
 523                 pwrc: power-controller@17030000 {
 524                         compatible = "starfive,jh7110-pmu";
 525                         reg = <0x0 0x17030000 0x0 0x10000>;
 526                         interrupts = <111>;
 527                         #power-domain-cells = <1>;
 528                         status = "okay";
 529                 };
 530
 531                 uart0: serial@10000000 {
 532                         compatible = "snps,dw-apb-uart";
 533                         reg = <0x0 0x10000000 0x0 0x10000>;
 534                         reg-io-width = <4>;
 535                         reg-shift = <2>;
 536                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 537                                  <&clkgen JH7110_UART0_CLK_APB>;
 538                         clock-names = "baudclk", "apb_pclk";
 539                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 540                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 541                         interrupts = <32>;
 542                         status = "disabled";
 543                 };
 544
 545                 uart1: serial@10010000 {
 546                         compatible = "snps,dw-apb-uart";
 547                         reg = <0x0 0x10010000 0x0 0x10000>;
 548                         reg-io-width = <4>;
 549                         reg-shift = <2>;
 550                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 551                                  <&clkgen JH7110_UART1_CLK_APB>;
 552                         clock-names = "baudclk", "apb_pclk";
 553                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 554                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 555                         interrupts = <33>;
 556                         status = "disabled";
 557                 };
 558
 559                 uart2: serial@10020000 {
 560                         compatible = "snps,dw-apb-uart";
 561                         reg = <0x0 0x10020000 0x0 0x10000>;
 562                         reg-io-width = <4>;
 563                         reg-shift = <2>;
 564                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 565                                  <&clkgen JH7110_UART2_CLK_APB>;
 566                         clock-names = "baudclk", "apb_pclk";
 567                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 568                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 569                         interrupts = <34>;
 570                         status = "disabled";
 571                 };
 572
 573                 uart3: serial@12000000 {
 574                         compatible = "snps,dw-apb-uart";
 575                         reg = <0x0 0x12000000 0x0 0x10000>;
 576                         reg-io-width = <4>;
 577                         reg-shift = <2>;
 578                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 579                                  <&clkgen JH7110_UART3_CLK_APB>;
 580                         clock-names = "baudclk", "apb_pclk";
 581                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 582                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 583                         interrupts = <45>;
 584                         status = "disabled";
 585                 };
 586
 587                 uart4: serial@12010000 {
 588                         compatible = "snps,dw-apb-uart";
 589                         reg = <0x0 0x12010000 0x0 0x10000>;
 590                         reg-io-width = <4>;
 591                         reg-shift = <2>;
 592                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 593                                  <&clkgen JH7110_UART4_CLK_APB>;
 594                         clock-names = "baudclk", "apb_pclk";
 595                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 596                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 597                         interrupts = <46>;
 598                         status = "disabled";
 599                 };
 600
 601                 uart5: serial@12020000 {
 602                         compatible = "snps,dw-apb-uart";
 603                         reg = <0x0 0x12020000 0x0 0x10000>;
 604                         reg-io-width = <4>;
 605                         reg-shift = <2>;
 606                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 607                                  <&clkgen JH7110_UART5_CLK_APB>;
 608                         clock-names = "baudclk", "apb_pclk";
 609                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 610                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 611                         interrupts = <47>;
 612                         status = "disabled";
 613                 };
 614
 615                 dma: dma-controller@16050000 {
 616                         compatible = "starfive,axi-dma";
 617                         reg = <0x0 0x16050000 0x0 0x10000>;
 618                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 619                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 620                         clock-names = "core-clk", "cfgr-clk";
 621                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 622                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 623                         reset-names = "rst_axi", "rst_ahb";
 624                         interrupts = <73>;
 625                         #dma-cells = <2>;
 626                         dma-channels = <4>;
 627                         snps,dma-masters = <1>;
 628                         snps,data-width = <3>;
 629                         snps,num-hs-if = <56>;
 630                         snps,block-size = <65536 65536 65536 65536>;
 631                         snps,priority = <0 1 2 3>;
 632                         snps,axi-max-burst-len = <16>;
 633                         status = "disabled";
 634                 };
 635
 636                 gpio: gpio@13040000 {
 637                         compatible = "starfive,jh7110-sys-pinctrl";
 638                         reg = <0x0 0x13040000 0x0 0x10000>;
 639                         reg-names = "control";
 640                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 641                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 642                         interrupts = <86>;
 643                         interrupt-controller;
 644                         #gpio-cells = <2>;
 645                         ngpios = <64>;
 646                         status = "okay";
 647                 };
 648
 649                 gpioa: gpio@17020000 {
 650                         compatible = "starfive,jh7110-aon-pinctrl";
 651                         reg = <0x0 0x17020000 0x0 0x10000>;
 652                         reg-names = "control";
 653                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 654                         interrupts = <85>;
 655                         interrupt-controller;
 656                         #gpio-cells = <2>;
 657                         ngpios = <4>;
 658                         status = "okay";
 659                 };
 660
 661                 sfctemp: tmon@120e0000  {
 662                         compatible = "starfive,jh7110-temp";
 663                         reg = <0x0 0x120e0000 0x0 0x10000>;
 664                         interrupts = <81>;
 665                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 666                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 667                         clock-names = "sense", "bus";
 668                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 669                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 670                         reset-names = "sense", "bus";
 671                         #thermal-sensor-cells = <0>;
 672                         status = "disabled";
 673                 };
 674
 675                 thermal-zones {
 676                         cpu-thermal {
 677                                 polling-delay-passive = <250>;
 678                                 polling-delay = <15000>;
 679
 680                                 thermal-sensors = <&sfctemp>;
 681
 682                                 cooling-maps {
 683                                 };
 684
 685                                 trips {
 686                                         cpu_alert0: cpu_alert0 {
 687                                                 /* milliCelsius */
 688                                                 temperature = <75000>;
 689                                                 hysteresis = <2000>;
 690                                                 type = "passive";
 691                                         };
 692
 693                                         cpu_crit: cpu_crit {
 694                                                 /* milliCelsius */
 695                                                 temperature = <90000>;
 696                                                 hysteresis = <2000>;
 697                                                 type = "critical";
 698                                         };
 699                                 };
 700                         };
 701                 };
 702
 703                 trng: trng@1600C000 {
 704                         compatible = "starfive,trng";
 705                         reg = <0x0 0x1600C000 0x0 0x4000>;
 706                         clocks = <&clkgen JH7110_SEC_HCLK>,
 707                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 708                         clock-names = "hclk", "miscahb_clk";
 709                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 710                         interrupts = <30>;
 711                         status = "disabled";
 712                 };
 713
 714                 sec_dma: sec_dma@16008000 {
 715                         /*compatible = "arm,pl080", "arm,primecell";*/
 716                         compatible = "starfive,pl080";
 717                         reg = <0x0 0x16008000 0x0 0x4000>;
 718                         reg-names = "sec_dma";
 719                         interrupts = <29>;
 720                         clocks = <&clkgen JH7110_SEC_HCLK>,
 721                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 722                         clock-names = "sec_hclk","sec_ahb";
 723                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 724                         reset-names = "sec_hre";
 725                         lli-bus-interface-ahb1;
 726                         mem-bus-interface-ahb1;
 727                         memcpy-burst-size = <256>;
 728                         memcpy-bus-width = <32>;
 729                         #dma-cells = <2>;
 730                         status = "disabled";
 731                 };
 732
 733                 crypto: crypto@16000000 {
 734                         compatible = "starfive,jh7110-sec";
 735                         reg = <0x0 0x16000000 0x0 0x4000>,
 736                               <0x0 0x16008000 0x0 0x4000>;
 737                         reg-names = "secreg","secdma";
 738                         interrupts = <28>, <29>;
 739                         interrupt-names = "secirq", "dmairq";
 740                         clocks = <&clkgen JH7110_SEC_HCLK>,
 741                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 742                         clock-names = "sec_hclk","sec_ahb";
 743                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 744                         reset-names = "sec_hre";
 745                         enable-side-channel-mitigation = "true";
 746                         enable-dma = "true";
 747                         dmas = <&sec_dma 1 2>,
 748                                <&sec_dma 0 2>;
 749                         dma-names = "sec_m","sec_p";
 750                         status = "disabled";
 751                 };
 752
 753                 i2c0: i2c@10030000 {
 754                         compatible = "snps,designware-i2c";
 755                         reg = <0x0 0x10030000 0x0 0x10000>;
 756                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 757                                  <&clkgen JH7110_I2C0_CLK_APB>;
 758                         clock-names = "ref", "pclk";
 759                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 760                         interrupts = <35>;
 761                         #address-cells = <1>;
 762                         #size-cells = <0>;
 763                         status = "disabled";
 764                 };
 765
 766                 i2c1: i2c@10040000 {
 767                         compatible = "snps,designware-i2c";
 768                         reg = <0x0 0x10040000 0x0 0x10000>;
 769                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 770                                  <&clkgen JH7110_I2C1_CLK_APB>;
 771                         clock-names = "ref", "pclk";
 772                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 773                         interrupts = <36>;
 774                         #address-cells = <1>;
 775                         #size-cells = <0>;
 776                         status = "disabled";
 777                 };
 778
 779                 i2c2: i2c@10050000 {
 780                         compatible = "snps,designware-i2c";
 781                         reg = <0x0 0x10050000 0x0 0x10000>;
 782                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 783                                  <&clkgen JH7110_I2C2_CLK_APB>;
 784                         clock-names = "ref", "pclk";
 785                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 786                         interrupts = <37>;
 787                         #address-cells = <1>;
 788                         #size-cells = <0>;
 789                         status = "disabled";
 790                 };
 791
 792                 i2c3: i2c@12030000 {
 793                         compatible = "snps,designware-i2c";
 794                         reg = <0x0 0x12030000 0x0 0x10000>;
 795                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 796                                  <&clkgen JH7110_I2C3_CLK_APB>;
 797                         clock-names = "ref", "pclk";
 798                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 799                         interrupts = <48>;
 800                         #address-cells = <1>;
 801                         #size-cells = <0>;
 802                         status = "disabled";
 803                 };
 804
 805                 i2c4: i2c@12040000 {
 806                         compatible = "snps,designware-i2c";
 807                         reg = <0x0 0x12040000 0x0 0x10000>;
 808                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 809                                  <&clkgen JH7110_I2C4_CLK_APB>;
 810                         clock-names = "ref", "pclk";
 811                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 812                         interrupts = <49>;
 813                         #address-cells = <1>;
 814                         #size-cells = <0>;
 815                         status = "disabled";
 816                 };
 817
 818                 i2c5: i2c@12050000 {
 819                         compatible = "snps,designware-i2c";
 820                         reg = <0x0 0x12050000 0x0 0x10000>;
 821                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 822                                  <&clkgen JH7110_I2C5_CLK_APB>;
 823                         clock-names = "ref", "pclk";
 824                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 825                         interrupts = <50>;
 826                         #address-cells = <1>;
 827                         #size-cells = <0>;
 828                         status = "disabled";
 829                 };
 830
 831                 i2c6: i2c@12060000 {
 832                         compatible = "snps,designware-i2c";
 833                         reg = <0x0 0x12060000 0x0 0x10000>;
 834                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 835                                  <&clkgen JH7110_I2C6_CLK_APB>;
 836                         clock-names = "ref", "pclk";
 837                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 838                         interrupts = <51>;
 839                         #address-cells = <1>;
 840                         #size-cells = <0>;
 841                         status = "disabled";
 842                 };
 843
 844                 /* unremovable emmc as mmcblk0 */
 845                 sdio0: sdio0@16010000 {
 846                         compatible = "snps,dw-mshc";
 847                         reg = <0x0 0x16010000 0x0 0x10000>;
 848                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 849                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 850                         clock-names = "biu","ciu";
 851                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 852                         reset-names = "reset";
 853                         interrupts = <74>;
 854                         fifo-depth = <32>;
 855                         fifo-watermark-aligned;
 856                         data-addr = <0>;
 857                         status = "disabled";
 858                 };
 859
 860                 sdio1: sdio1@16020000 {
 861                         compatible = "snps,dw-mshc";
 862                         reg = <0x0 0x16020000 0x0 0x10000>;
 863                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 864                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 865                         clock-names = "biu","ciu";
 866                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 867                         reset-names = "reset";
 868                         interrupts = <75>;
 869                         fifo-depth = <32>;
 870                         fifo-watermark-aligned;
 871                         data-addr = <0>;
 872                         status = "disabled";
 873                 };
 874
 875                 vin_sysctl: vin_sysctl@19800000 {
 876                         compatible = "starfive,jh7110-vin";
 877                         reg = <0x0 0x19800000 0x0 0x10000>,
 878                                 <0x0 0x19810000 0x0 0x10000>,
 879                                 <0x0 0x19820000 0x0 0x10000>,
 880                                 <0x0 0x19840000 0x0 0x10000>,
 881                                 <0x0 0x19870000 0x0 0x30000>,
 882                                 <0x0 0x11840000 0x0 0x10000>,
 883                                 <0x0 0x17030000 0x0 0x10000>,
 884                                 <0x0 0x13020000 0x0 0x10000>;
 885                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 886                                 "isp", "trst", "pmu", "syscrg";
 887                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 888                                  <&clkisp JH7110_U0_VIN_PCLK>,
 889                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 890                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 891                                  <&clkisp JH7110_DVP_INV>,
 892                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 893                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 894                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 895                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 896                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 897                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 898                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 899                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 900                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 901                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 902                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 903                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 904                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 905                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 906                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 907                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 908                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 909                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 910                                 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
 911                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 912                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 913                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 914                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 915                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 916                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 917                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 918                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 919                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 920                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 921                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 922                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 923                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 924                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 925                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 926                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 927                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 928                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 929                                 "rst_isp_top_n", "rst_isp_top_axi";
 930                         starfive,aon-syscon = <&aon_syscon 0x00>;
 931                         power-domains = <&pwrc JH7110_PD_ISP>;
 932                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 933                         interrupts = <92 87 88 89 90>;
 934                         status = "disabled";
 935                 };
 936
 937                 jpu: jpu@11900000 {
 938                         compatible = "starfive,jpu";
 939                         reg = <0x0 0x13090000 0x0 0x300>;
 940                         interrupts = <14>;
 941                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 942                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 943                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 944                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 945                         clock-names = "axi_clk", "core_clk",
 946                                       "apb_clk", "noc_bus";
 947                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 948                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 949                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 950                         reset-names = "rst_axi", "rst_core", "rst_apb";
 951                         power-domains = <&pwrc JH7110_PD_VDEC>;
 952                         status = "disabled";
 953                 };
 954
 955                 vpu_dec: vpu_dec@130A0000 {
 956                         compatible = "starfive,vdec";
 957                         reg = <0x0 0x130A0000 0x0 0x10000>;
 958                         interrupts = <13>;
 959                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 960                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 961                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 962                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 963                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 964                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 965                                       "apb_clk", "noc_bus";
 966                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 967                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 968                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 969                                 <&rstgen RSTN_U0_WAVE511_APB>,
 970                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 971                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 972                                       "rst_apb", "rst_sram";
 973                         starfive,vdec_noc_ctrl;
 974                         power-domains = <&pwrc JH7110_PD_VDEC>;
 975                         status = "disabled";
 976                 };
 977
 978                 vpu_enc: vpu_enc@130B0000 {
 979                         compatible = "starfive,venc";
 980                         reg = <0x0 0x130B0000 0x0 0x10000>;
 981                         interrupts = <15>;
 982                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 983                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 984                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 985                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 986                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 987                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 988                                       "apb_clk", "noc_bus";
 989                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 990                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 991                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 992                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 993                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 994                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 995                                       "rst_apb", "rst_sram";
 996                         starfive,venc_noc_ctrl;
 997                         power-domains = <&pwrc JH7110_PD_VENC>;
 998                         status = "disabled";
 999                 };
1000
1001                 rstgen: reset-controller {
1002                         compatible = "starfive,jh7110-reset";
1003                         reg = <0x0 0x13020000 0x0 0x10000>,
1004                                 <0x0 0x10230000 0x0 0x10000>,
1005                                 <0x0 0x17000000 0x0 0x10000>,
1006                                 <0x0 0x19810000 0x0 0x10000>,
1007                                 <0x0 0x295C0000 0x0 0x10000>;
1008                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
1009                         #reset-cells = <1>;
1010                         status = "okay";
1011                 };
1012
1013                 stmmac_axi_setup: stmmac-axi-config {
1014                         snps,wr_osr_lmt = <0xf>;
1015                         snps,rd_osr_lmt = <0xf>;
1016                         snps,blen = <256 128 64 32 0 0 0>;
1017                 };
1018
1019                 gmac0: ethernet@16030000 {
1020                         compatible = "starfive,jh7110-eqos-5.20";
1021                         reg = <0x0 0x16030000 0x0 0x10000>;
1022                         clock-names = "gtx",
1023                                 "tx",
1024                                 "ptp_ref",
1025                                 "stmmaceth",
1026                                 "pclk",
1027                                 "gtxc";
1028                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
1029                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
1030                                  <&clkgen JH7110_GMAC0_PTP>,
1031                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
1032                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
1033                                  <&clkgen JH7110_GMAC0_GTXC>;
1034                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
1035                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
1036                         reset-names = "ahb", "stmmaceth";
1037                         interrupts = <7>, <6>, <5> ;
1038                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1039                         max-frame-size = <9000>;
1040                         phy-mode = "rgmii-id";
1041                         snps,multicast-filter-bins = <64>;
1042                         snps,perfect-filter-entries = <128>;
1043                         rx-fifo-depth = <2048>;
1044                         tx-fifo-depth = <2048>;
1045                         snps,fixed-burst;
1046                         snps,no-pbl-x8;
1047                         snps,force_thresh_dma_mode;
1048                         snps,axi-config = <&stmmac_axi_setup>;
1049                         snps,tso;
1050                         snps,en-tx-lpi-clockgating;
1051                         snps,en-lpi;
1052                         snps,write-requests = <4>;
1053                         snps,read-requests = <4>;
1054                         snps,burst-map = <0x7>;
1055                         snps,txpbl = <16>;
1056                         snps,rxpbl = <16>;
1057                         status = "disabled";
1058                 };
1059
1060                 gmac1: ethernet@16040000 {
1061                         compatible = "starfive,jh7110-eqos-5.20";
1062                         reg = <0x0 0x16040000 0x0 0x10000>;
1063                         clock-names = "gtx",
1064                                 "tx",
1065                                 "ptp_ref",
1066                                 "stmmaceth",
1067                                 "pclk",
1068                                 "gtxc";
1069                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1070                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1071                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1072                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1073                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1074                                  <&clkgen JH7110_GMAC1_GTXC>;
1075                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1076                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1077                         reset-names = "ahb", "stmmaceth";
1078                         interrupts = <78>, <77>, <76> ;
1079                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1080                         max-frame-size = <9000>;
1081                         phy-mode = "rgmii-id";
1082                         snps,multicast-filter-bins = <64>;
1083                         snps,perfect-filter-entries = <128>;
1084                         rx-fifo-depth = <2048>;
1085                         tx-fifo-depth = <2048>;
1086                         snps,fixed-burst;
1087                         snps,no-pbl-x8;
1088                         snps,force_thresh_dma_mode;
1089                         snps,axi-config = <&stmmac_axi_setup>;
1090                         snps,tso;
1091                         snps,en-tx-lpi-clockgating;
1092                         snps,en-lpi;
1093                         snps,write-requests = <4>;
1094                         snps,read-requests = <4>;
1095                         snps,burst-map = <0x7>;
1096                         snps,txpbl = <16>;
1097                         snps,rxpbl = <16>;
1098                         status = "disabled";
1099                 };
1100
1101                 gpu: gpu@18000000 {
1102                         compatible = "img-gpu";
1103                         reg = <0x0 0x18000000 0x0 0x100000>,
1104                                 <0x0 0x130C000 0x0 0x10000>;
1105                         clocks = <&clkgen JH7110_GPU_CLK_APB>,
1106                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1107                                  <&clkgen JH7110_GPU_CORE_CLK>,
1108                                  <&clkgen JH7110_GPU_SYS_CLK>,
1109                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1110                         clock-names = "clk_apb", "clk_rtc", "clk_core",
1111                                         "clk_sys", "clk_axi";
1112                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1113                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1114                         reset-names = "rst_apb", "rst_doma";
1115                         power-domains = <&pwrc JH7110_PD_GPUA>;
1116                         interrupts = <82>;
1117                         current-clock = <8000000>;
1118                         status = "disabled";
1119                 };
1120
1121                 can0: can@130d0000 {
1122                         compatible = "ipms,can";
1123                         reg = <0x0 0x130d0000 0x0 0x1000>;
1124                         interrupts = <112>;
1125                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1126                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1127                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1128                         clock-names = "apb_clk", "core_clk", "timer_clk";
1129                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1130                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1131                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1132                         reset-names = "rst_apb", "rst_core", "rst_timer";
1133                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1134                         syscon,can_or_canfd = <0>;
1135                         status = "disabled";
1136                 };
1137
1138                 can1: can@130e0000 {
1139                         compatible = "ipms,can";
1140                         reg = <0x0 0x130e0000 0x0 0x1000>;
1141                         interrupts = <113>;
1142                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1143                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1144                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1145                         clock-names = "apb_clk", "core_clk", "timer_clk";
1146                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1147                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1148                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1149                         reset-names = "rst_apb", "rst_core", "rst_timer";
1150                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1151                         syscon,can_or_canfd = <0>;
1152                         status = "disabled";
1153                 };
1154
1155                 tdm: tdm@10090000 {
1156                         compatible = "starfive,sf-tdm";
1157                         reg = <0x0 0x10090000 0x0 0x1000>;
1158                         reg-names = "tdm";
1159                         clocks = <&clkgen JH7110_AHB0>,
1160                                  <&clkgen JH7110_TDM_CLK_AHB>,
1161                                  <&clkgen JH7110_APB0>,
1162                                  <&clkgen JH7110_TDM_CLK_APB>,
1163                                  <&clkgen JH7110_TDM_INTERNAL>,
1164                                  <&tdm_ext>,
1165                                  <&clkgen JH7110_TDM_CLK_TDM>,
1166                                  <&clkgen JH7110_MCLK_INNER>;
1167                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1168                                       "clk_apb0", "clk_tdm_apb",
1169                                       "clk_tdm_internal", "clk_tdm_ext",
1170                                       "clk_tdm", "mclk_inner";
1171                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1172                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1173                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1174                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1175                         dmas = <&dma 20 1>, <&dma 21 1>;
1176                         dma-names = "rx","tx";
1177                         #sound-dai-cells = <0>;
1178                         status = "disabled";
1179                 };
1180
1181                 spdif0: spdif0@100a0000 {
1182                         compatible = "starfive,sf-spdif";
1183                         reg = <0x0 0x100a0000 0x0 0x1000>;
1184                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1185                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1186                                  <&clkgen JH7110_AUDIO_ROOT>,
1187                                  <&clkgen JH7110_MCLK_INNER>;
1188                         clock-names = "spdif-apb", "spdif-core",
1189                                       "audroot", "mclk_inner";
1190                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1191                         reset-names = "rst_apb";
1192                         interrupts = <84>;
1193                         interrupt-names = "tx";
1194                         #sound-dai-cells = <0>;
1195                         status = "disabled";
1196                 };
1197
1198                 pwmdac: pwmdac@100b0000 {
1199                         compatible = "starfive,pwmdac";
1200                         reg = <0x0 0x100b0000 0x0 0x1000>;
1201                         clocks = <&clkgen JH7110_APB0>,
1202                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1203                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1204                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1205                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1206                         reset-names = "rst-apb";
1207                         dmas = <&dma 22 1>;
1208                         dma-names = "tx";
1209                         #sound-dai-cells = <0>;
1210                         status = "disabled";
1211                 };
1212
1213                 i2stx: i2stx@100c0000 {
1214                         compatible = "snps,designware-i2stx";
1215                         reg = <0x0 0x100c0000 0x0 0x1000>;
1216                         interrupt-names = "tx";
1217                         #sound-dai-cells = <0>;
1218                         dmas = <&dma 28 1>;
1219                         dma-names = "rx";
1220                         status = "disabled";
1221                 };
1222
1223                 pdm: pdm@100d0000 {
1224                         compatible = "starfive,sf-pdm";
1225                         reg = <0x0 0x100d0000 0x0 0x1000>;
1226                         reg-names = "pdm";
1227                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1228                                  <&clkgen JH7110_APB0>,
1229                                  <&clkgen JH7110_PDM_CLK_APB>,
1230                                  <&clkgen JH7110_MCLK_INNER>,
1231                                  <&clkgen JH7110_MCLK>,
1232                                  <&clkgen JH7110_MCLK_OUT>;
1233                         clock-names = "pdm_mclk", "clk_apb0",
1234                                       "pdm_apb", "mclk_inner",
1235                                       "clk_mclk", "mclk_out";
1236                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1237                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1238                         reset-names = "pdm_dmic", "pdm_apb";
1239                         #sound-dai-cells = <0>;
1240                 };
1241
1242                 i2srx_mst: i2srx_mst@100e0000 {
1243                         compatible = "snps,i2srx-master";
1244                         reg = <0x0 0x100e0000 0x0 0x1000>;
1245                         clocks = <&clkgen JH7110_APB0>,
1246                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1247                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1248                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1249                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1250                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1251                         clock-names = "apb0", "i2srx_apb",
1252                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1253                                       "i2srx_bclk", "i2srx_lrck";
1254                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1255                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1256                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1257                         dmas = <&dma 24 1>;
1258                         dma-names = "rx";
1259                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1260                         #sound-dai-cells = <0>;
1261                         status = "disabled";
1262                 };
1263
1264                 i2srx_3ch: i2srx_3ch@100e0000 {
1265                         compatible = "snps,designware-i2srx";
1266                         reg = <0x0 0x100e0000 0x0 0x1000>;
1267                         clocks = <&clkgen JH7110_APB0>,
1268                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1269                                  <&clkgen JH7110_AUDIO_ROOT>,
1270                                  <&clkgen JH7110_MCLK_INNER>,
1271                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1272                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1273                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1274                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1275                                  <&clkgen JH7110_MCLK>,
1276                                  <&i2srx_bclk_ext>,
1277                                  <&i2srx_lrck_ext>;
1278                         clock-names = "apb0", "3ch-apb",
1279                                         "audioroot", "mclk-inner",
1280                                         "bclk_mst", "3ch-lrck",
1281                                         "rx-bclk", "rx-lrck",
1282                                         "mclk", "bclk-ext",
1283                                         "lrck-ext";
1284                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1285                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1286                         dmas = <&dma 24 1>;
1287                         dma-names = "rx";
1288                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1289                         #sound-dai-cells = <0>;
1290                         status = "disabled";
1291                 };
1292
1293                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1294                         compatible = "snps,designware-i2stx-4ch0";
1295                         reg = <0x0 0x120b0000 0x0 0x1000>;
1296                         clocks = <&clkgen JH7110_MCLK_INNER>,
1297                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1298                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1299                                  <&clkgen JH7110_MCLK>,
1300                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1301                                  <&clkgen JH7110_I2STX0_4CHLRCK>;
1302                         clock-names = "inner", "bclk-mst",
1303                                         "lrck-mst", "mclk",
1304                                         "bclk0", "lrck0";
1305                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1306                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1307                         dmas = <&dma 47 1>;
1308                         dma-names = "tx";
1309                         #sound-dai-cells = <0>;
1310                         status = "disabled";
1311                 };
1312
1313                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1314                         compatible = "snps,designware-i2stx-4ch1";
1315                         reg = <0x0 0x120c0000 0x0 0x1000>;
1316                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1317                                  <&clkgen JH7110_MCLK_INNER>,
1318                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1319                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1320                                  <&clkgen JH7110_MCLK>,
1321                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1322                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1323                                  <&clkgen JH7110_MCLK_OUT>,
1324                                  <&clkgen JH7110_APB0>,
1325                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1326                                  <&mclk_ext>,
1327                                  <&i2stx_bclk_ext>,
1328                                  <&i2stx_lrck_ext>;
1329                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1330                                         "lrck_mst", "mclk", "4chbclk",
1331                                         "4chlrck", "mclk_out",
1332                                         "apb0", "clk_apb",
1333                                         "mclk_ext", "bclk_ext", "lrck_ext";
1334
1335                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1336                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1337                         dmas = <&dma 48 1>;
1338                         dma-names = "tx";
1339                         #sound-dai-cells = <0>;
1340                         status = "disabled";
1341                 };
1342
1343                 ptc: pwm@120d0000 {
1344                         compatible = "starfive,pwm";
1345                         reg = <0x0 0x120d0000 0x0 0x10000>;
1346                         reg-names = "control";
1347                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1348                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1349                         starfive,approx-freq = <2000000>;
1350                         #pwm-cells=<3>;
1351                         starfive,npwm = <8>;
1352                         status = "disabled";
1353                 };
1354
1355                 spdif_transmitter: spdif_transmitter {
1356                         compatible = "linux,spdif-dit";
1357                         #sound-dai-cells = <0>;
1358                         status = "disabled";
1359                 };
1360
1361                 spdif_receiver: spdif_receiver {
1362                         compatible = "linux,spdif-dir";
1363                         #sound-dai-cells = <0>;
1364                         status = "disabled";
1365                 };
1366
1367                 pwmdac_codec: pwmdac-transmitter {
1368                         compatible = "linux,pwmdac-dit";
1369                         #sound-dai-cells = <0>;
1370                         status = "disabled";
1371                 };
1372
1373                 dmic_codec: dmic_codec {
1374                         compatible = "dmic-codec";
1375                         #sound-dai-cells = <0>;
1376                         status = "disabled";
1377                 };
1378
1379                 spi0: spi@10060000 {
1380                         compatible = "arm,pl022", "arm,primecell";
1381                         reg = <0x0 0x10060000 0x0 0x10000>;
1382                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1383                         clock-names = "apb_pclk";
1384                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1385                         reset-names = "rst_apb";
1386                         interrupts = <38>;
1387                         /* shortage of dma channel that not be used */
1388                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1389                         /*dma-names = "rx","tx";*/
1390                         arm,primecell-periphid = <0x00041022>;
1391                         num-cs = <1>;
1392                         #address-cells = <1>;
1393                         #size-cells = <0>;
1394                         status = "disabled";
1395                 };
1396
1397                 spi1: spi@10070000 {
1398                         compatible = "arm,pl022", "arm,primecell";
1399                         reg = <0x0 0x10070000 0x0 0x10000>;
1400                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1401                         clock-names = "apb_pclk";
1402                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1403                         reset-names = "rst_apb";
1404                         interrupts = <39>;
1405                         /* shortage of dma channel that not be used */
1406                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1407                         /*dma-names = "rx","tx";*/
1408                         arm,primecell-periphid = <0x00041022>;
1409                         num-cs = <1>;
1410                         #address-cells = <1>;
1411                         #size-cells = <0>;
1412                         status = "disabled";
1413                 };
1414
1415                 spi2: spi@10080000 {
1416                         compatible = "arm,pl022", "arm,primecell";
1417                         reg = <0x0 0x10080000 0x0 0x10000>;
1418                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1419                         clock-names = "apb_pclk";
1420                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1421                         reset-names = "rst_apb";
1422                         interrupts = <40>;
1423                         /* shortage of dma channel that not be used */
1424                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1425                         /*dma-names = "rx","tx";*/
1426                         arm,primecell-periphid = <0x00041022>;
1427                         num-cs = <1>;
1428                         #address-cells = <1>;
1429                         #size-cells = <0>;
1430                         status = "disabled";
1431                 };
1432
1433                 spi3: spi@12070000 {
1434                         compatible = "arm,pl022", "arm,primecell";
1435                         reg = <0x0 0x12070000 0x0 0x10000>;
1436                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1437                         clock-names = "apb_pclk";
1438                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1439                         reset-names = "rst_apb";
1440                         interrupts = <52>;
1441                         /* shortage of dma channel that not be used */
1442                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1443                         /*dma-names = "rx","tx";*/
1444                         arm,primecell-periphid = <0x00041022>;
1445                         num-cs = <1>;
1446                         #address-cells = <1>;
1447                         #size-cells = <0>;
1448                         status = "disabled";
1449                 };
1450
1451                 spi4: spi@12080000 {
1452                         compatible = "arm,pl022", "arm,primecell";
1453                         reg = <0x0 0x12080000 0x0 0x10000>;
1454                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1455                         clock-names = "apb_pclk";
1456                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1457                         reset-names = "rst_apb";
1458                         interrupts = <53>;
1459                         /* shortage of dma channel that not be used */
1460                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1461                         /*dma-names = "rx","tx";*/
1462                         arm,primecell-periphid = <0x00041022>;
1463                         num-cs = <1>;
1464                         #address-cells = <1>;
1465                         #size-cells = <0>;
1466                         status = "disabled";
1467                 };
1468
1469                 spi5: spi@12090000 {
1470                         compatible = "arm,pl022", "arm,primecell";
1471                         reg = <0x0 0x12090000 0x0 0x10000>;
1472                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1473                         clock-names = "apb_pclk";
1474                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1475                         reset-names = "rst_apb";
1476                         interrupts = <54>;
1477                         /* shortage of dma channel that not be used */
1478                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1479                         /*dma-names = "rx","tx";*/
1480                         arm,primecell-periphid = <0x00041022>;
1481                         num-cs = <1>;
1482                         #address-cells = <1>;
1483                         #size-cells = <0>;
1484                         status = "disabled";
1485                 };
1486
1487                 spi6: spi@120A0000 {
1488                         compatible = "arm,pl022", "arm,primecell";
1489                         reg = <0x0 0x120A0000 0x0 0x10000>;
1490                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1491                         clock-names = "apb_pclk";
1492                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1493                         reset-names = "rst_apb";
1494                         interrupts = <55>;
1495                         /* shortage of dma channel that not be used */
1496                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1497                         /*dma-names = "rx","tx";*/
1498                         arm,primecell-periphid = <0x00041022>;
1499                         num-cs = <1>;
1500                         #address-cells = <1>;
1501                         #size-cells = <0>;
1502                         status = "disabled";
1503                 };
1504
1505                 pcie0: pcie@2B000000 {
1506                         compatible = "plda,pci-xpressrich3-axi";
1507                         #address-cells = <3>;
1508                         #size-cells = <2>;
1509                         #interrupt-cells = <1>;
1510                         reg = <0x0 0x2B000000 0x0 0x1000000
1511                                0x9 0x40000000 0x0 0x10000000>;
1512                         reg-names = "reg", "config";
1513                         device_type = "pci";
1514                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1515                         bus-range = <0x0 0xff>;
1516                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>;
1517                         msi-parent = <&plic>;
1518                         interrupts = <56>;
1519                         interrupt-controller;
1520                         interrupt-names = "msi";
1521                         interrupt-parent = <&plic>;
1522                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1523                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1524                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1525                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1526                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1527                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1528                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1529                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1530                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1531                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1532                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1533                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1534                                       "rst_brg", "rst_core", "rst_apb";
1535                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1536                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1537                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1538                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1539                         clock-names = "noc", "tl", "axi_mst0", "apb";
1540                         status = "disabled";
1541                 };
1542
1543                 pcie1: pcie@2C000000 {
1544                         compatible = "plda,pci-xpressrich3-axi";
1545                         #address-cells = <3>;
1546                         #size-cells = <2>;
1547                         #interrupt-cells = <1>;
1548                         reg = <0x0 0x2C000000 0x0 0x1000000
1549                                0x9 0xc0000000 0x0 0x10000000>;
1550                         reg-names = "reg", "config";
1551                         device_type = "pci";
1552                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1553                         bus-range = <0x0 0xff>;
1554                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>;
1555                         msi-parent = <&plic>;
1556                         interrupts = <57>;
1557                         interrupt-controller;
1558                         interrupt-names = "msi";
1559                         interrupt-parent = <&plic>;
1560                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1561                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1562                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1563                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1564                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1565                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1566                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1567                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1568                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1569                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1570                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1571                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1572                                       "rst_brg", "rst_core", "rst_apb";
1573                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1574                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1575                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1576                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1577                         clock-names = "noc", "tl", "axi_mst0", "apb";
1578                         status = "disabled";
1579                 };
1580
1581                 mailbox_contrl0: mailbox@0 {
1582                         compatible = "starfive,mail_box";
1583                         reg = <0x0 0x13060000 0x0 0x0001000>;
1584                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1585                         clock-names = "clk_apb";
1586                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1587                         reset-names = "mbx_rre";
1588                         interrupts = <26 27>;
1589                         #mbox-cells = <2>;
1590                         status = "disabled";
1591                 };
1592
1593                 mailbox_client0: mailbox_client@0 {
1594                         compatible = "starfive,mailbox-test";
1595                         mbox-names = "rx", "tx";
1596                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1597                         status = "disabled";
1598                 };
1599
1600                 display: display-subsystem {
1601                         compatible = "verisilicon,display-subsystem";
1602                         ports = <&dc_out_dpi0>;
1603                         status = "disabled";
1604                 };
1605
1606                 dssctrl: dssctrl@295B0000 {
1607                         compatible = "verisilicon,dss-ctrl", "syscon";
1608                         reg = <0 0x295B0000 0 0x90>;
1609                 };
1610
1611                 tda988x_pin: tda988x_pin {
1612                         compatible = "starfive,tda998x_rgb_pin";
1613                         status = "disabled";
1614                 };
1615
1616                 hdmi_output: hdmi-output {
1617                         compatible = "verisilicon,hdmi-encoder";
1618                         //verisilicon,dss-syscon = <&dssctrl>;
1619                         //verisilicon,mux-mask = <0x70 0x380>;
1620                         //verisilicon,mux-val = <0x40 0x280>;
1621                         status = "disabled";
1622                 };
1623
1624                 dc8200: dc8200@29400000 {
1625                         compatible = "verisilicon,dc8200";
1626                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1627                         reg = <0x0 0x29400000 0x0 0x100>,
1628                               <0x0 0x29400800 0x0 0x2000>,
1629                               <0x0 0x17030000 0x0 0x1000>;
1630                         interrupts = <95>;
1631                         status = "disabled";
1632                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1633                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1634                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1635                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1636                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1637                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1638                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1639                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1640                                  <&clkgen JH7110_VOUT_SRC>,
1641                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1642                                  <&clkgen JH7110_AHB1>,
1643                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1644                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1645                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1646                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1647                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1648                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1649                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1650                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1651                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1652                                  <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1653                                  <&hdmitx0_pixelclk>,
1654                                  <&clkvout JH7110_DC8200_PIX0>,
1655                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1656                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1657                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1658                                         "noc_disp","noc_isp","noc_stg","vout_src",
1659                                         "top_vout_axi","ahb1","top_vout_ahb",
1660                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1661                                         "axi_clk","core_clk","vout_ahb",
1662                                         "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1663                                         "dc8200_pix0_out","dc8200_pix1_out";
1664                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1665                                  <&rstgen RSTN_U0_DC8200_AXI>,
1666                                  <&rstgen RSTN_U0_DC8200_AHB>,
1667                                  <&rstgen RSTN_U0_DC8200_CORE>,
1668                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1669                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1670                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1671                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1672                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1673                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1674                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1675                                         "rst_noc_disp","rst_noc_stg";
1676                         power-domains = <&pwrc JH7110_PD_VOUT>;
1677                 };
1678
1679                 encoder: display-encoder {
1680                         compatible = "verisilicon,dsi-encoder";
1681                         status = "disabled";
1682                 };
1683
1684                 mipi_dphy: mipi-dphy@295e0000{
1685                         compatible = "starfive,jh7100-mipi-dphy-tx";
1686                         reg = <0x0 0x295e0000 0x0 0x10000>;
1687                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1688                         clock-names = "dphy_txesc";
1689                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1690                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1691                         reset-names = "dphy_sys", "dphy_txbytehs";
1692                         #phy-cells = <0>;
1693                         status = "disabled";
1694                 };
1695
1696                  mipi_dsi: mipi@295d0000 {
1697                         compatible = "cdns,dsi";
1698                         reg = <0x0 0x295d0000 0x0 0x10000>;
1699                         interrupts = <98>;
1700                         reg-names = "dsi";
1701                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1702                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1703                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1704                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1705                         clock-names = "sys", "apb", "txesc", "dpi";
1706                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1707                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1708                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1709                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1710                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1711                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1712                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1713                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1714                         phys = <&mipi_dphy>;
1715                         phy-names = "dphy";
1716                         status = "disabled";
1717
1718                         port {
1719                                 dsi_out_port: endpoint@0 {
1720                                         remote-endpoint = <&panel_dsi_port>;
1721                                 };
1722                                 dsi_in_port: endpoint@1 {
1723                                         remote-endpoint = <&mipi_out>;
1724                                 };
1725                         };
1726
1727                         mipi_panel: panel@0 {
1728                                 /*compatible = "";*/
1729                                 status = "okay";
1730                         };
1731                 };
1732
1733                 hdmi: hdmi@29590000 {
1734                         compatible = "rockchip,rk3036-inno-hdmi";
1735                         reg = <0x0 0x29590000 0x0 0x4000>;
1736                         interrupts = <99>;
1737                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1738                         /*clocks = <&cru  PCLK_HDMI>;*/
1739                         /*clock-names = "pclk";*/
1740                         /*pinctrl-names = "default";*/
1741                         /*pinctrl-0 = <&hdmi_ctl>;*/
1742                         status = "disabled";
1743                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1744                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1745                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1746                                  <&hdmitx0_pixelclk>;
1747                         clock-names = "sysclk", "mclk","bclk","pclk";
1748                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1749                         reset-names = "hdmi_tx";
1750                 };
1751
1752                 sound: snd-card {
1753                         compatible = "simple-audio-card";
1754                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1755                         #address-cells = <1>;
1756                         #size-cells = <0>;
1757                 };
1758
1759                 co_process: e24@0 {
1760                         compatible = "starfive,e24";
1761                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1762                                 <0x0 0xc0111000 0x0 0x0001f000>;
1763                         reg-names = "ecmd", "espace";
1764                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1765                                  <&clkgen JH7110_E2_CLK_CORE>,
1766                                  <&clkgen JH7110_E2_CLK_DBG>;
1767                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1768                         resets = <&rstgen RSTN_U0_E24_CORE>;
1769                         reset-names = "e24_core";
1770                         starfive,stg-syscon = <&stg_syscon>;
1771                         interrupt-parent = <&plic>;
1772                         firmware-name = "e24_elf";
1773                         irq-mode = <1>;
1774                         mbox-names = "tx", "rx";
1775                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1776                         #address-cells = <1>;
1777                         #size-cells = <1>;
1778                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1779                         status = "disabled";
1780                         dsp@0 {};
1781                 };
1782
1783                 xrp: xrp@0 {
1784                         compatible = "cdns,xrp";
1785                         reg = <0x0  0x10230000 0x0 0x00010000
1786                                 0x0  0x10240000 0x0 0x00010000>;
1787                         memory-region = <&xrp_reserved>;
1788                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1789                         clock-names = "core_clk";
1790                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1791                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1792                         reset-names = "rst_core","rst_axi";
1793                         starfive,stg-syscon = <&stg_syscon>;
1794                         firmware-name = "hifi4_elf";
1795                         #address-cells = <1>;
1796                         #size-cells = <1>;
1797                         ranges = <0x40000000 0x0 0x20000000 0x040000
1798                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1799                         status = "disabled";
1800                         dsp@0 {
1801                         };
1802                 };
1803
1804                 stf_cpufreq: starfive,stf-cpufreq {
1805                         compatible = "starfive,stf-cpufreq";
1806                         clocks = <&clkgen JH7110_PLL0_OUT>,
1807                                          <&clkgen JH7110_CPU_ROOT>,
1808                                          <&osc>;
1809                         clock-names = "pll0", "cpu_clk", "osc";
1810                 };
1811         };
1812 };