1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110-clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
13 #include <dt-bindings/power/jh7110-power.h>
16 compatible = "starfive,jh7110";
20 cluster0_opp: opp-table-0 {
21 compatible = "operating-points-v2";
24 opp-hz = /bits/ 64 <375000000>;
25 opp-microvolt = <880000>;
28 opp-hz = /bits/ 64 <500000000>;
29 opp-microvolt = <880000>;
32 opp-hz = /bits/ 64 <625000000>;
33 opp-microvolt = <880000>;
36 opp-hz = /bits/ 64 <750000000>;
37 opp-microvolt = <880000>;
40 opp-hz = /bits/ 64 <875000000>;
41 opp-microvolt = <880000>;
44 opp-hz = /bits/ 64 <1000000000>;
45 opp-microvolt = <900000>;
48 opp-hz = /bits/ 64 <1250000000>;
49 opp-microvolt = <950000>;
52 opp-hz = /bits/ 64 <1375000000>;
53 opp-microvolt = <1000000>;
56 opp-hz = /bits/ 64 <1500000000>;
57 opp-microvolt = <1100000>;
60 opp-hz = /bits/ 64 <1625000000>;
61 opp-microvolt = <1100000>;
64 opp-hz = /bits/ 64 <1750000000>;
65 opp-microvolt = <1200000>;
74 compatible = "sifive,u74-mc", "riscv";
76 d-cache-block-size = <64>;
78 d-cache-size = <8192>;
82 i-cache-block-size = <64>;
84 i-cache-size = <16384>;
87 mmu-type = "riscv,sv39";
88 cpu-idle-states = <&CPU_NONRET_0_0>;
89 next-level-cache = <&cachectrl>;
90 riscv,isa = "rv64imac";
94 cpu0intctrl: interrupt-controller {
95 #interrupt-cells = <1>;
96 compatible = "riscv,cpu-intc";
102 compatible = "sifive,u74-mc", "riscv";
104 d-cache-block-size = <64>;
106 d-cache-size = <32768>;
110 i-cache-block-size = <64>;
112 i-cache-size = <32768>;
115 mmu-type = "riscv,sv39";
116 cpu-idle-states = <&CPU_NONRET_0_0>;
117 next-level-cache = <&cachectrl>;
118 riscv,isa = "rv64imafdc";
121 operating-points-v2 = <&cluster0_opp>;
123 cpu1intctrl: interrupt-controller {
124 #interrupt-cells = <1>;
125 compatible = "riscv,cpu-intc";
126 interrupt-controller;
131 compatible = "sifive,u74-mc", "riscv";
133 d-cache-block-size = <64>;
135 d-cache-size = <32768>;
139 i-cache-block-size = <64>;
141 i-cache-size = <32768>;
144 mmu-type = "riscv,sv39";
145 cpu-idle-states = <&CPU_NONRET_0_0>;
146 next-level-cache = <&cachectrl>;
147 riscv,isa = "rv64imafdc";
150 operating-points-v2 = <&cluster0_opp>;
152 cpu2intctrl: interrupt-controller {
153 #interrupt-cells = <1>;
154 compatible = "riscv,cpu-intc";
155 interrupt-controller;
160 compatible = "sifive,u74-mc", "riscv";
162 d-cache-block-size = <64>;
164 d-cache-size = <32768>;
168 i-cache-block-size = <64>;
170 i-cache-size = <32768>;
173 mmu-type = "riscv,sv39";
174 cpu-idle-states = <&CPU_NONRET_0_0>;
175 next-level-cache = <&cachectrl>;
176 riscv,isa = "rv64imafdc";
179 operating-points-v2 = <&cluster0_opp>;
181 cpu3intctrl: interrupt-controller {
182 #interrupt-cells = <1>;
183 compatible = "riscv,cpu-intc";
184 interrupt-controller;
189 compatible = "sifive,u74-mc", "riscv";
191 d-cache-block-size = <64>;
193 d-cache-size = <32768>;
197 i-cache-block-size = <64>;
199 i-cache-size = <32768>;
202 mmu-type = "riscv,sv39";
203 cpu-idle-states = <&CPU_NONRET_0_0>;
204 next-level-cache = <&cachectrl>;
205 riscv,isa = "rv64imafdc";
208 operating-points-v2 = <&cluster0_opp>;
210 cpu4intctrl: interrupt-controller {
211 #interrupt-cells = <1>;
212 compatible = "riscv,cpu-intc";
213 interrupt-controller;
219 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
220 compatible = "riscv,idle-state";
221 riscv,sbi-suspend-param = <0x80000000>;
222 entry-latency-us = <600>;
223 exit-latency-us = <1100>;
224 min-residency-us = <2700>;
225 wakeup-latency-us = <1500>;
230 compatible = "simple-bus";
231 interrupt-parent = <&plic>;
232 #address-cells = <2>;
237 cachectrl: cache-controller@2010000 {
238 compatible = "sifive,fu740-c000-ccache", "cache";
239 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
240 reg-names = "control", "sideband";
241 interrupts = <1 3 4 2>;
242 cache-block-size = <64>;
245 cache-size = <2097152>;
249 aon_syscon: aon_syscon@17010000 {
250 compatible = "syscon";
251 reg = <0x0 0x17010000 0x0 0x1000>;
254 stg_syscon: stg_syscon@10240000 {
255 compatible = "syscon";
256 reg = <0x0 0x10240000 0x0 0x1000>;
259 sys_syscon: sys_syscon@13030000 {
260 compatible = "syscon";
261 reg = <0x0 0x13030000 0x0 0x1000>;
264 clint: clint@2000000 {
265 compatible = "riscv,clint0";
266 reg = <0x0 0x2000000 0x0 0x10000>;
267 reg-names = "control";
268 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
269 &cpu1intctrl 3 &cpu1intctrl 7
270 &cpu2intctrl 3 &cpu2intctrl 7
271 &cpu3intctrl 3 &cpu3intctrl 7
272 &cpu4intctrl 3 &cpu4intctrl 7>;
273 #interrupt-cells = <1>;
277 compatible = "riscv,plic0";
278 reg = <0x0 0xc000000 0x0 0x4000000>;
279 reg-names = "control";
280 interrupts-extended = <&cpu0intctrl 11
281 &cpu1intctrl 11 &cpu1intctrl 9
282 &cpu2intctrl 11 &cpu2intctrl 9
283 &cpu3intctrl 11 &cpu3intctrl 9
284 &cpu4intctrl 11 &cpu4intctrl 9>;
285 interrupt-controller;
286 #interrupt-cells = <1>;
287 riscv,max-priority = <7>;
291 clkgen: clock-controller {
292 compatible = "starfive,jh7110-clkgen";
293 reg = <0x0 0x13020000 0x0 0x10000>,
294 <0x0 0x10230000 0x0 0x10000>,
295 <0x0 0x17000000 0x0 0x10000>;
296 reg-names = "sys", "stg", "aon";
297 clocks = <&osc>, <&gmac1_rmii_refin>,
299 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
300 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
301 <&tdm_ext>, <&mclk_ext>,
302 <&jtag_tck_inner>, <&bist_apb>,
304 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
305 clock-names = "osc", "gmac1_rmii_refin",
307 "i2stx_bclk_ext", "i2stx_lrck_ext",
308 "i2srx_bclk_ext", "i2srx_lrck_ext",
309 "tdm_ext", "mclk_ext",
310 "jtag_tck_inner", "bist_apb",
312 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
314 starfive,sys-syscon = <&sys_syscon 0x18 0x1c
315 0x20 0x24 0x28 0x2c 0x30 0x34>;
319 clkvout: clock-controller@295C0000 {
320 compatible = "starfive,jh7110-clk-vout";
321 reg = <0x0 0x295C0000 0x0 0x10000>;
323 clocks = <&hdmitx0_pixelclk>,
324 <&mipitx_dphy_rxesc>,
325 <&mipitx_dphy_txbytehs>,
326 <&clkgen JH7110_VOUT_SRC>,
327 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
328 clock-names = "hdmitx0_pixelclk",
330 "mipitx_dphy_txbytehs",
333 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
334 reset-names = "vout_src";
336 power-domains = <&pwrc JH7110_PD_VOUT>;
340 clkisp: clock-controller@19810000 {
341 compatible = "starfive,jh7110-clk-isp";
342 reg = <0x0 0x19810000 0x0 0x10000>;
345 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
346 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
347 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
348 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
349 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
350 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
351 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
352 "u0_sft7110_noc_bus_clk_isp_axi";
353 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
354 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
355 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
356 reset-names = "rst_isp_top_n", "rst_isp_top_axi",
358 power-domains = <&pwrc JH7110_PD_ISP>;
363 compatible = "cdns,qspi-nor";
364 #address-cells = <1>;
366 reg = <0x0 0x13010000 0x0 0x10000
367 0x0 0x21000000 0x0 0x400000>;
368 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
369 clock-names = "clk_ref";
370 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
371 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
372 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
373 resets-names = "rst_apb", "rst_ahb", "rst_ref";
374 cdns,fifo-depth = <256>;
375 cdns,fifo-width = <4>;
376 spi-max-frequency = <250000000>;
378 nor_flash: nor-flash@0 {
379 compatible = "jedec,spi-nor";
381 spi-max-frequency = <100000000>;
390 compatible = "starfive,jh7110-otp";
391 reg = <0x0 0x17050000 0x0 0x10000>;
392 clock-frequency = <4000000>;
393 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
398 compatible = "starfive,jh7110-cdns3";
399 reg = <0x0 0x10210000 0x0 0x1000>,
400 <0x0 0x10200000 0x0 0x1000>;
401 clocks = <&clkgen JH7110_USB_125M>,
402 <&clkgen JH7110_USB0_CLK_APP_125>,
403 <&clkgen JH7110_USB0_CLK_LPM>,
404 <&clkgen JH7110_USB0_CLK_STB>,
405 <&clkgen JH7110_USB0_CLK_USB_APB>,
406 <&clkgen JH7110_USB0_CLK_AXI>,
407 <&clkgen JH7110_USB0_CLK_UTMI_APB>,
408 <&clkgen JH7110_PCIE0_CLK_APB>;
409 clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
410 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
411 <&rstgen RSTN_U0_CDN_USB_APB>,
412 <&rstgen RSTN_U0_CDN_USB_AXI>,
413 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
414 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
415 reset-names = "pwrup","apb","axi","utmi", "phy";
416 starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
417 starfive,sys-syscon = <&sys_syscon 0x18>;
419 #address-cells = <2>;
421 #interrupt-cells = <1>;
423 usbdrd_cdns3: usb@10100000 {
424 compatible = "cdns,usb3";
425 reg = <0x0 0x10100000 0x0 0x10000>,
426 <0x0 0x10110000 0x0 0x10000>,
427 <0x0 0x10120000 0x0 0x10000>;
428 reg-names = "otg", "xhci", "dev";
429 interrupts = <100>, <108>, <110>;
430 interrupt-names = "host", "peripheral", "otg";
431 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
432 maximum-speed = "super-speed";
436 timer: timer@13050000 {
437 compatible = "starfive,jh7110-timers";
438 reg = <0x0 0x13050000 0x0 0x10000>;
439 interrupts = <69>, <70>, <71> ,<72>;
440 interrupt-names = "timer0", "timer1",
442 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
443 <&clkgen JH7110_TIMER_CLK_TIMER1>,
444 <&clkgen JH7110_TIMER_CLK_TIMER2>,
445 <&clkgen JH7110_TIMER_CLK_TIMER3>,
446 <&clkgen JH7110_TIMER_CLK_APB>;
447 clock-names = "timer0", "timer1",
448 "timer2", "timer3", "apb_clk";
449 resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
450 <&rstgen RSTN_U0_TIMER_TIMER1>,
451 <&rstgen RSTN_U0_TIMER_TIMER2>,
452 <&rstgen RSTN_U0_TIMER_TIMER3>,
453 <&rstgen RSTN_U0_TIMER_APB>;
454 reset-names = "timer0", "timer1",
455 "timer2", "timer3", "apb_rst";
456 clock-frequency = <24000000>;
460 wdog: wdog@13070000 {
461 compatible = "starfive,jh7110-wdt";
462 reg = <0x0 0x13070000 0x0 0x10000>;
464 interrupt-names = "wdog";
465 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
466 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
467 clock-names = "core_clk", "apb_clk";
468 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
469 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
470 reset-names = "rst_apb", "rst_core";
476 compatible = "starfive,jh7110-rtc";
477 reg = <0x0 0x17040000 0x0 0x10000>;
478 interrupts = <10>, <11>, <12>;
479 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
480 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
481 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
482 clock-names = "pclk", "cal_clk";
483 resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
484 <&rstgen RSTN_U0_RTC_HMS_APB>,
485 <&rstgen RSTN_U0_RTC_HMS_CAL>;
486 reset-names = "rst_osc", "rst_apb", "rst_cal";
487 rtc,cal-clock-freq = <1000000>;
491 pwrc: power-controller@17030000 {
492 compatible = "starfive,jh7110-pmu";
493 reg = <0x0 0x17030000 0x0 0x10000>;
495 #power-domain-cells = <1>;
499 uart0: serial@10000000 {
500 compatible = "snps,dw-apb-uart";
501 reg = <0x0 0x10000000 0x0 0x10000>;
504 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
505 <&clkgen JH7110_UART0_CLK_APB>;
506 clock-names = "baudclk", "apb_pclk";
507 resets = <&rstgen RSTN_U0_DW_UART_APB>,
508 <&rstgen RSTN_U0_DW_UART_CORE>;
513 uart1: serial@10010000 {
514 compatible = "snps,dw-apb-uart";
515 reg = <0x0 0x10010000 0x0 0x10000>;
518 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
519 <&clkgen JH7110_UART1_CLK_APB>;
520 clock-names = "baudclk", "apb_pclk";
521 resets = <&rstgen RSTN_U1_DW_UART_APB>,
522 <&rstgen RSTN_U1_DW_UART_CORE>;
527 uart2: serial@10020000 {
528 compatible = "snps,dw-apb-uart";
529 reg = <0x0 0x10020000 0x0 0x10000>;
532 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
533 <&clkgen JH7110_UART2_CLK_APB>;
534 clock-names = "baudclk", "apb_pclk";
535 resets = <&rstgen RSTN_U2_DW_UART_APB>,
536 <&rstgen RSTN_U2_DW_UART_CORE>;
541 uart3: serial@12000000 {
542 compatible = "snps,dw-apb-uart";
543 reg = <0x0 0x12000000 0x0 0x10000>;
546 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
547 <&clkgen JH7110_UART3_CLK_APB>;
548 clock-names = "baudclk", "apb_pclk";
549 resets = <&rstgen RSTN_U3_DW_UART_APB>,
550 <&rstgen RSTN_U3_DW_UART_CORE>;
555 uart4: serial@12010000 {
556 compatible = "snps,dw-apb-uart";
557 reg = <0x0 0x12010000 0x0 0x10000>;
560 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
561 <&clkgen JH7110_UART4_CLK_APB>;
562 clock-names = "baudclk", "apb_pclk";
563 resets = <&rstgen RSTN_U4_DW_UART_APB>,
564 <&rstgen RSTN_U4_DW_UART_CORE>;
569 uart5: serial@12020000 {
570 compatible = "snps,dw-apb-uart";
571 reg = <0x0 0x12020000 0x0 0x10000>;
574 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
575 <&clkgen JH7110_UART5_CLK_APB>;
576 clock-names = "baudclk", "apb_pclk";
577 resets = <&rstgen RSTN_U5_DW_UART_APB>,
578 <&rstgen RSTN_U5_DW_UART_CORE>;
583 dma: dma-controller@16050000 {
584 compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
585 reg = <0x0 0x16050000 0x0 0x10000>;
586 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
587 <&clkgen JH7110_DMA1P_CLK_AHB>;
588 clock-names = "core-clk", "cfgr-clk";
589 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
590 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
591 reset-names = "rst_axi", "rst_ahb";
595 snps,dma-masters = <1>;
596 snps,data-width = <3>;
597 snps,num-hs-if = <56>;
598 snps,block-size = <65536 65536 65536 65536>;
599 snps,priority = <0 1 2 3>;
600 snps,axi-max-burst-len = <16>;
604 gpio: gpio@13040000 {
605 compatible = "starfive,jh7110-sys-pinctrl";
606 reg = <0x0 0x13040000 0x0 0x10000>;
607 reg-names = "control";
608 clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
609 resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
611 interrupt-controller;
617 gpioa: gpio@17020000 {
618 compatible = "starfive,jh7110-aon-pinctrl";
619 reg = <0x0 0x17020000 0x0 0x10000>;
620 reg-names = "control";
621 resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
623 interrupt-controller;
629 sfctemp: tmon@120e0000 {
630 compatible = "starfive,jh7110-temp";
631 reg = <0x0 0x120e0000 0x0 0x10000>;
633 clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
634 <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
635 clock-names = "sense", "bus";
636 resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
637 <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
638 reset-names = "sense", "bus";
639 #thermal-sensor-cells = <0>;
645 polling-delay-passive = <250>;
646 polling-delay = <15000>;
648 thermal-sensors = <&sfctemp>;
654 cpu_alert0: cpu_alert0 {
656 temperature = <75000>;
663 temperature = <90000>;
671 trng: trng@1600C000 {
672 compatible = "starfive,jh7110-trng";
673 reg = <0x0 0x1600C000 0x0 0x4000>;
674 clocks = <&clkgen JH7110_SEC_HCLK>,
675 <&clkgen JH7110_SEC_MISCAHB_CLK>;
676 clock-names = "hclk", "miscahb_clk";
677 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
682 sec_dma: sec_dma@16008000 {
683 compatible = "arm,pl080", "arm,primecell";
684 arm,primecell-periphid = <0x00041080>;
685 reg = <0x0 0x16008000 0x0 0x4000>;
686 reg-names = "sec_dma";
688 clocks = <&clkgen JH7110_SEC_HCLK>,
689 <&clkgen JH7110_SEC_MISCAHB_CLK>;
690 clock-names = "sec_hclk","apb_pclk";
691 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
692 reset-names = "sec_hre";
693 lli-bus-interface-ahb1;
694 mem-bus-interface-ahb1;
695 memcpy-burst-size = <256>;
696 memcpy-bus-width = <32>;
701 crypto: crypto@16000000 {
702 compatible = "starfive,jh7110-sec";
703 reg = <0x0 0x16000000 0x0 0x4000>,
704 <0x0 0x16008000 0x0 0x4000>;
705 reg-names = "secreg","secdma";
706 interrupts = <28>, <29>;
707 interrupt-names = "secirq", "dmairq";
708 clocks = <&clkgen JH7110_SEC_HCLK>,
709 <&clkgen JH7110_SEC_MISCAHB_CLK>;
710 clock-names = "sec_hclk","sec_ahb";
711 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
712 reset-names = "sec_hre";
713 enable-side-channel-mitigation = "true";
715 dmas = <&sec_dma 1 2>,
717 dma-names = "sec_m","sec_p";
722 compatible = "snps,designware-i2c";
723 reg = <0x0 0x10030000 0x0 0x10000>;
724 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
725 <&clkgen JH7110_I2C0_CLK_APB>;
726 clock-names = "ref", "pclk";
727 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
729 #address-cells = <1>;
735 compatible = "snps,designware-i2c";
736 reg = <0x0 0x10040000 0x0 0x10000>;
737 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
738 <&clkgen JH7110_I2C1_CLK_APB>;
739 clock-names = "ref", "pclk";
740 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
742 #address-cells = <1>;
748 compatible = "snps,designware-i2c";
749 reg = <0x0 0x10050000 0x0 0x10000>;
750 clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
751 <&clkgen JH7110_I2C2_CLK_APB>;
752 clock-names = "ref", "pclk";
753 resets = <&rstgen RSTN_U2_DW_I2C_APB>;
755 #address-cells = <1>;
761 compatible = "snps,designware-i2c";
762 reg = <0x0 0x12030000 0x0 0x10000>;
763 clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
764 <&clkgen JH7110_I2C3_CLK_APB>;
765 clock-names = "ref", "pclk";
766 resets = <&rstgen RSTN_U3_DW_I2C_APB>;
768 #address-cells = <1>;
774 compatible = "snps,designware-i2c";
775 reg = <0x0 0x12040000 0x0 0x10000>;
776 clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
777 <&clkgen JH7110_I2C4_CLK_APB>;
778 clock-names = "ref", "pclk";
779 resets = <&rstgen RSTN_U4_DW_I2C_APB>;
781 #address-cells = <1>;
787 compatible = "snps,designware-i2c";
788 reg = <0x0 0x12050000 0x0 0x10000>;
789 clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
790 <&clkgen JH7110_I2C5_CLK_APB>;
791 clock-names = "ref", "pclk";
792 resets = <&rstgen RSTN_U5_DW_I2C_APB>;
794 #address-cells = <1>;
800 compatible = "snps,designware-i2c";
801 reg = <0x0 0x12060000 0x0 0x10000>;
802 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
803 <&clkgen JH7110_I2C6_CLK_APB>;
804 clock-names = "ref", "pclk";
805 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
807 #address-cells = <1>;
812 /* unremovable emmc as mmcblk0 */
813 sdio0: sdio0@16010000 {
814 compatible = "starfive,jh7110-sdio";
815 reg = <0x0 0x16010000 0x0 0x10000>;
816 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
817 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
818 clock-names = "biu","ciu";
819 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
820 reset-names = "reset";
823 fifo-watermark-aligned;
825 starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
829 sdio1: sdio1@16020000 {
830 compatible = "starfive,jh7110-sdio";
831 reg = <0x0 0x16020000 0x0 0x10000>;
832 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
833 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
834 clock-names = "biu","ciu";
835 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
836 reset-names = "reset";
839 fifo-watermark-aligned;
844 vin_sysctl: vin_sysctl@19800000 {
845 compatible = "starfive,jh7110-vin";
846 reg = <0x0 0x19800000 0x0 0x10000>,
847 <0x0 0x19810000 0x0 0x10000>,
848 <0x0 0x19820000 0x0 0x10000>,
849 <0x0 0x19840000 0x0 0x10000>,
850 <0x0 0x19870000 0x0 0x30000>,
851 <0x0 0x11840000 0x0 0x10000>,
852 <0x0 0x17030000 0x0 0x10000>,
853 <0x0 0x13020000 0x0 0x10000>;
854 reg-names = "csi2rx", "vclk", "vrst", "sctrl",
855 "isp", "trst", "pmu", "syscrg";
856 clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
857 <&clkisp JH7110_U0_VIN_PCLK>,
858 <&clkisp JH7110_U0_VIN_SYS_CLK>,
859 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
860 <&clkisp JH7110_DVP_INV>,
861 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
862 <&clkisp JH7110_MIPI_RX0_PXL>,
863 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
864 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
865 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
866 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
867 <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
868 <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
869 <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
870 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
871 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
872 clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
873 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
874 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
875 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
876 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
877 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
878 "clk_ispcore_2x", "clk_isp_axi";
879 resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
880 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
881 <&rstgen RSTN_U0_VIN_N_PCLK>,
882 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
883 <&rstgen RSTN_U0_VIN_P_AXIRD>,
884 <&rstgen RSTN_U0_VIN_P_AXIWR>,
885 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
886 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
887 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
888 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
889 <&rstgen RSTN_U0_M31DPHY_HW>,
890 <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
891 <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
892 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
893 reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
894 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
895 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
896 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
897 "rst_isp_top_n", "rst_isp_top_axi";
898 starfive,aon-syscon = <&aon_syscon 0x00>;
899 power-domains = <&pwrc JH7110_PD_ISP>;
900 /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
901 interrupts = <92 87 88 89 90>;
906 compatible = "starfive,jpu";
907 reg = <0x0 0x13090000 0x0 0x300>;
909 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
910 <&clkgen JH7110_CODAJ12_CLK_CORE>,
911 <&clkgen JH7110_CODAJ12_CLK_APB>,
912 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
913 clock-names = "axi_clk", "core_clk",
914 "apb_clk", "noc_bus";
915 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
916 <&rstgen RSTN_U0_CODAJ12_CORE>,
917 <&rstgen RSTN_U0_CODAJ12_APB>;
918 reset-names = "rst_axi", "rst_core", "rst_apb";
919 power-domains = <&pwrc JH7110_PD_VDEC>;
923 vpu_dec: vpu_dec@130A0000 {
924 compatible = "starfive,vdec";
925 reg = <0x0 0x130A0000 0x0 0x10000>;
927 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
928 <&clkgen JH7110_WAVE511_CLK_BPU>,
929 <&clkgen JH7110_WAVE511_CLK_VCE>,
930 <&clkgen JH7110_WAVE511_CLK_APB>,
931 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
932 clock-names = "axi_clk", "bpu_clk", "vce_clk",
933 "apb_clk", "noc_bus";
934 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
935 <&rstgen RSTN_U0_WAVE511_BPU>,
936 <&rstgen RSTN_U0_WAVE511_VCE>,
937 <&rstgen RSTN_U0_WAVE511_APB>,
938 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
939 reset-names = "rst_axi", "rst_bpu", "rst_vce",
940 "rst_apb", "rst_sram";
941 starfive,vdec_noc_ctrl;
942 power-domains = <&pwrc JH7110_PD_VDEC>;
946 vpu_enc: vpu_enc@130B0000 {
947 compatible = "starfive,venc";
948 reg = <0x0 0x130B0000 0x0 0x10000>;
950 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
951 <&clkgen JH7110_WAVE420L_CLK_BPU>,
952 <&clkgen JH7110_WAVE420L_CLK_VCE>,
953 <&clkgen JH7110_WAVE420L_CLK_APB>,
954 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
955 clock-names = "axi_clk", "bpu_clk", "vce_clk",
956 "apb_clk", "noc_bus";
957 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
958 <&rstgen RSTN_U0_WAVE420L_BPU>,
959 <&rstgen RSTN_U0_WAVE420L_VCE>,
960 <&rstgen RSTN_U0_WAVE420L_APB>,
961 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
962 reset-names = "rst_axi", "rst_bpu", "rst_vce",
963 "rst_apb", "rst_sram";
964 starfive,venc_noc_ctrl;
965 power-domains = <&pwrc JH7110_PD_VENC>;
969 rstgen: reset-controller {
970 compatible = "starfive,jh7110-reset";
971 reg = <0x0 0x13020000 0x0 0x10000>,
972 <0x0 0x10230000 0x0 0x10000>,
973 <0x0 0x17000000 0x0 0x10000>,
974 <0x0 0x19810000 0x0 0x10000>,
975 <0x0 0x295C0000 0x0 0x10000>;
976 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
981 stmmac_axi_setup: stmmac-axi-config {
982 snps,wr_osr_lmt = <0xf>;
983 snps,rd_osr_lmt = <0xf>;
984 snps,blen = <256 128 64 32 0 0 0>;
987 gmac0: ethernet@16030000 {
988 compatible = "starfive,dwmac","snps,dwmac-5.10a";
989 reg = <0x0 0x16030000 0x0 0x10000>;
996 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
997 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
998 <&clkgen JH7110_GMAC0_PTP>,
999 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
1000 <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
1001 <&clkgen JH7110_GMAC0_GTXC>;
1002 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
1003 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
1004 reset-names = "ahb", "stmmaceth";
1005 interrupts = <7>, <6>, <5> ;
1006 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1007 max-frame-size = <9000>;
1008 phy-mode = "rgmii-id";
1009 snps,multicast-filter-bins = <64>;
1010 snps,perfect-filter-entries = <128>;
1011 rx-fifo-depth = <2048>;
1012 tx-fifo-depth = <2048>;
1015 snps,force_thresh_dma_mode;
1016 snps,axi-config = <&stmmac_axi_setup>;
1018 snps,en-tx-lpi-clockgating;
1020 snps,write-requests = <4>;
1021 snps,read-requests = <4>;
1022 snps,burst-map = <0x7>;
1025 status = "disabled";
1028 gmac1: ethernet@16040000 {
1029 compatible = "starfive,dwmac","snps,dwmac-5.10a";
1030 reg = <0x0 0x16040000 0x0 0x10000>;
1031 clock-names = "gtx",
1037 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1038 <&clkgen JH7110_GMAC5_CLK_TX>,
1039 <&clkgen JH7110_GMAC5_CLK_PTP>,
1040 <&clkgen JH7110_GMAC5_CLK_AHB>,
1041 <&clkgen JH7110_GMAC5_CLK_AXI>,
1042 <&clkgen JH7110_GMAC1_GTXC>;
1043 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1044 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1045 reset-names = "ahb", "stmmaceth";
1046 interrupts = <78>, <77>, <76> ;
1047 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1048 max-frame-size = <9000>;
1049 phy-mode = "rgmii-id";
1050 snps,multicast-filter-bins = <64>;
1051 snps,perfect-filter-entries = <128>;
1052 rx-fifo-depth = <2048>;
1053 tx-fifo-depth = <2048>;
1056 snps,force_thresh_dma_mode;
1057 snps,axi-config = <&stmmac_axi_setup>;
1059 snps,en-tx-lpi-clockgating;
1061 snps,write-requests = <4>;
1062 snps,read-requests = <4>;
1063 snps,burst-map = <0x7>;
1066 status = "disabled";
1070 compatible = "img-gpu";
1071 reg = <0x0 0x18000000 0x0 0x100000>,
1072 <0x0 0x130C000 0x0 0x10000>;
1073 clocks = <&clkgen JH7110_GPU_CORE>,
1074 <&clkgen JH7110_GPU_CLK_APB>,
1075 <&clkgen JH7110_GPU_RTC_TOGGLE>,
1076 <&clkgen JH7110_GPU_CORE_CLK>,
1077 <&clkgen JH7110_GPU_SYS_CLK>,
1078 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1079 clock-names = "clk_bv", "clk_apb", "clk_rtc",
1080 "clk_core", "clk_sys", "clk_axi";
1081 resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1082 <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1083 reset-names = "rst_apb", "rst_doma";
1084 power-domains = <&pwrc JH7110_PD_GPUA>;
1086 current-clock = <8000000>;
1087 status = "disabled";
1090 can0: can@130d0000 {
1091 compatible = "starfive,jh7110-can", "ipms,can";
1092 reg = <0x0 0x130d0000 0x0 0x1000>;
1094 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1095 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1096 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1097 clock-names = "apb_clk", "core_clk", "timer_clk";
1098 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1099 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1100 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1101 reset-names = "rst_apb", "rst_core", "rst_timer";
1102 frequency = <40000000>;
1103 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1104 syscon,can_or_canfd = <0>;
1105 status = "disabled";
1108 can1: can@130e0000 {
1109 compatible = "starfive,jh7110-can", "ipms,can";
1110 reg = <0x0 0x130e0000 0x0 0x1000>;
1112 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1113 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1114 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1115 clock-names = "apb_clk", "core_clk", "timer_clk";
1116 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1117 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1118 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1119 reset-names = "rst_apb", "rst_core", "rst_timer";
1120 frequency = <40000000>;
1121 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1122 syscon,can_or_canfd = <1>;
1123 status = "disabled";
1127 compatible = "starfive,jh7110-tdm";
1128 reg = <0x0 0x10090000 0x0 0x1000>;
1130 clocks = <&clkgen JH7110_AHB0>,
1131 <&clkgen JH7110_TDM_CLK_AHB>,
1132 <&clkgen JH7110_APB0>,
1133 <&clkgen JH7110_TDM_CLK_APB>,
1134 <&clkgen JH7110_TDM_INTERNAL>,
1136 <&clkgen JH7110_TDM_CLK_TDM>,
1137 <&clkgen JH7110_MCLK_INNER>;
1138 clock-names = "clk_ahb0", "clk_tdm_ahb",
1139 "clk_apb0", "clk_tdm_apb",
1140 "clk_tdm_internal", "clk_tdm_ext",
1141 "clk_tdm", "mclk_inner";
1142 resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1143 <&rstgen RSTN_U0_TDM16SLOT_APB>,
1144 <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1145 reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1146 dmas = <&dma 20 1>, <&dma 21 1>;
1147 dma-names = "rx","tx";
1148 #sound-dai-cells = <0>;
1149 status = "disabled";
1152 spdif0: spdif0@100a0000 {
1153 compatible = "starfive,jh7110-spdif";
1154 reg = <0x0 0x100a0000 0x0 0x1000>;
1155 clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1156 <&clkgen JH7110_SPDIF_CLK_CORE>,
1157 <&clkgen JH7110_AUDIO_ROOT>,
1158 <&clkgen JH7110_MCLK_INNER>,
1159 <&mclk_ext>, <&clkgen JH7110_MCLK>;
1160 clock-names = "spdif-apb", "spdif-core",
1161 "audroot", "mclk_inner",
1163 resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1164 reset-names = "rst_apb";
1166 interrupt-names = "tx";
1167 #sound-dai-cells = <0>;
1168 status = "disabled";
1171 pwmdac: pwmdac@100b0000 {
1172 compatible = "starfive,jh7110-pwmdac";
1173 reg = <0x0 0x100b0000 0x0 0x1000>;
1174 clocks = <&clkgen JH7110_APB0>,
1175 <&clkgen JH7110_PWMDAC_CLK_APB>,
1176 <&clkgen JH7110_PWMDAC_CLK_CORE>;
1177 clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1178 resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1179 reset-names = "rst-apb";
1182 #sound-dai-cells = <0>;
1183 status = "disabled";
1186 i2stx: i2stx@100c0000 {
1187 compatible = "snps,designware-i2stx";
1188 reg = <0x0 0x100c0000 0x0 0x1000>;
1189 interrupt-names = "tx";
1190 #sound-dai-cells = <0>;
1193 status = "disabled";
1197 compatible = "starfive,jh7110-pdm";
1198 reg = <0x0 0x100d0000 0x0 0x1000>;
1200 clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1201 <&clkgen JH7110_APB0>,
1202 <&clkgen JH7110_PDM_CLK_APB>,
1203 <&clkgen JH7110_MCLK>,
1205 clock-names = "pdm_mclk", "clk_apb0",
1206 "pdm_apb", "clk_mclk",
1208 resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1209 <&rstgen RSTN_U0_PDM_4MIC_APB>;
1210 reset-names = "pdm_dmic", "pdm_apb";
1211 #sound-dai-cells = <0>;
1214 i2srx_mst: i2srx_mst@100e0000 {
1215 compatible = "starfive,jh7110-i2srx-master";
1216 reg = <0x0 0x100e0000 0x0 0x1000>;
1217 clocks = <&clkgen JH7110_APB0>,
1218 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1219 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1220 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1221 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1222 <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1223 clock-names = "apb0", "i2srx_apb",
1224 "i2srx_bclk_mst", "i2srx_lrck_mst",
1225 "i2srx_bclk", "i2srx_lrck";
1226 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1227 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1228 reset-names = "rst_apb_rx", "rst_bclk_rx";
1231 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1232 #sound-dai-cells = <0>;
1233 status = "disabled";
1236 i2srx_3ch: i2srx_3ch@100e0000 {
1237 compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1238 reg = <0x0 0x100e0000 0x0 0x1000>;
1239 clocks = <&clkgen JH7110_APB0>,
1240 <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1241 <&clkgen JH7110_AUDIO_ROOT>,
1242 <&clkgen JH7110_MCLK_INNER>,
1243 <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1244 <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1245 <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1246 <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1247 <&clkgen JH7110_MCLK>,
1250 clock-names = "apb0", "3ch-apb",
1251 "audioroot", "mclk-inner",
1252 "bclk_mst", "3ch-lrck",
1253 "rx-bclk", "rx-lrck",
1256 resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1257 <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1260 starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1261 #sound-dai-cells = <0>;
1262 status = "disabled";
1265 i2stx_4ch0: i2stx_4ch0@120b0000 {
1266 compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1267 reg = <0x0 0x120b0000 0x0 0x1000>;
1268 clocks = <&clkgen JH7110_MCLK_INNER>,
1269 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1270 <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1271 <&clkgen JH7110_MCLK>,
1272 <&clkgen JH7110_I2STX0_4CHBCLK>,
1273 <&clkgen JH7110_I2STX0_4CHLRCK>,
1274 <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1276 clock-names = "inner", "bclk-mst",
1279 "i2s_apb", "mclk_ext";
1280 resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1281 <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1282 reset-names = "rst_apb", "rst_bclk";
1285 #sound-dai-cells = <0>;
1286 status = "disabled";
1289 i2stx_4ch1: i2stx_4ch1@120c0000 {
1290 compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1291 reg = <0x0 0x120c0000 0x0 0x1000>;
1292 clocks = <&clkgen JH7110_AUDIO_ROOT>,
1293 <&clkgen JH7110_MCLK_INNER>,
1294 <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1295 <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1296 <&clkgen JH7110_MCLK>,
1297 <&clkgen JH7110_I2STX1_4CHBCLK>,
1298 <&clkgen JH7110_I2STX1_4CHLRCK>,
1299 <&clkgen JH7110_MCLK_OUT>,
1300 <&clkgen JH7110_APB0>,
1301 <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1305 clock-names = "audroot", "mclk_inner", "bclk_mst",
1306 "lrck_mst", "mclk", "4chbclk",
1307 "4chlrck", "mclk_out",
1309 "mclk_ext", "bclk_ext", "lrck_ext";
1310 resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1311 <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1314 #sound-dai-cells = <0>;
1315 status = "disabled";
1319 compatible = "starfive,jh7110-pwm";
1320 reg = <0x0 0x120d0000 0x0 0x10000>;
1321 reg-names = "control";
1322 clocks = <&clkgen JH7110_PWM_CLK_APB>;
1323 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1324 starfive,approx-freq = <2000000>;
1326 starfive,npwm = <8>;
1327 status = "disabled";
1330 spdif_transmitter: spdif_transmitter {
1331 compatible = "linux,spdif-dit";
1332 #sound-dai-cells = <0>;
1333 status = "disabled";
1336 pwmdac_codec: pwmdac-transmitter {
1337 compatible = "starfive,jh7110-pwmdac-dit";
1338 #sound-dai-cells = <0>;
1339 status = "disabled";
1342 dmic_codec: dmic_codec {
1343 compatible = "dmic-codec";
1344 #sound-dai-cells = <0>;
1345 status = "disabled";
1348 spi0: spi@10060000 {
1349 compatible = "arm,pl022", "arm,primecell";
1350 reg = <0x0 0x10060000 0x0 0x10000>;
1351 clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1352 clock-names = "apb_pclk";
1353 resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1354 reset-names = "rst_apb";
1356 /* shortage of dma channel that not be used */
1357 /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1358 /*dma-names = "rx","tx";*/
1359 arm,primecell-periphid = <0x00041022>;
1361 #address-cells = <1>;
1363 status = "disabled";
1366 spi1: spi@10070000 {
1367 compatible = "arm,pl022", "arm,primecell";
1368 reg = <0x0 0x10070000 0x0 0x10000>;
1369 clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1370 clock-names = "apb_pclk";
1371 resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1372 reset-names = "rst_apb";
1374 /* shortage of dma channel that not be used */
1375 /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1376 /*dma-names = "rx","tx";*/
1377 arm,primecell-periphid = <0x00041022>;
1379 #address-cells = <1>;
1381 status = "disabled";
1384 spi2: spi@10080000 {
1385 compatible = "arm,pl022", "arm,primecell";
1386 reg = <0x0 0x10080000 0x0 0x10000>;
1387 clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1388 clock-names = "apb_pclk";
1389 resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1390 reset-names = "rst_apb";
1392 /* shortage of dma channel that not be used */
1393 /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1394 /*dma-names = "rx","tx";*/
1395 arm,primecell-periphid = <0x00041022>;
1397 #address-cells = <1>;
1399 status = "disabled";
1402 spi3: spi@12070000 {
1403 compatible = "arm,pl022", "arm,primecell";
1404 reg = <0x0 0x12070000 0x0 0x10000>;
1405 clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1406 clock-names = "apb_pclk";
1407 resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1408 reset-names = "rst_apb";
1410 /* shortage of dma channel that not be used */
1411 /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1412 /*dma-names = "rx","tx";*/
1413 arm,primecell-periphid = <0x00041022>;
1415 #address-cells = <1>;
1417 status = "disabled";
1420 spi4: spi@12080000 {
1421 compatible = "arm,pl022", "arm,primecell";
1422 reg = <0x0 0x12080000 0x0 0x10000>;
1423 clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1424 clock-names = "apb_pclk";
1425 resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1426 reset-names = "rst_apb";
1428 /* shortage of dma channel that not be used */
1429 /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1430 /*dma-names = "rx","tx";*/
1431 arm,primecell-periphid = <0x00041022>;
1433 #address-cells = <1>;
1435 status = "disabled";
1438 spi5: spi@12090000 {
1439 compatible = "arm,pl022", "arm,primecell";
1440 reg = <0x0 0x12090000 0x0 0x10000>;
1441 clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1442 clock-names = "apb_pclk";
1443 resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1444 reset-names = "rst_apb";
1446 /* shortage of dma channel that not be used */
1447 /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1448 /*dma-names = "rx","tx";*/
1449 arm,primecell-periphid = <0x00041022>;
1451 #address-cells = <1>;
1453 status = "disabled";
1456 spi6: spi@120A0000 {
1457 compatible = "arm,pl022", "arm,primecell";
1458 reg = <0x0 0x120A0000 0x0 0x10000>;
1459 clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1460 clock-names = "apb_pclk";
1461 resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1462 reset-names = "rst_apb";
1464 /* shortage of dma channel that not be used */
1465 /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1466 /*dma-names = "rx","tx";*/
1467 arm,primecell-periphid = <0x00041022>;
1469 #address-cells = <1>;
1471 status = "disabled";
1474 pcie0: pcie@2B000000 {
1475 compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1476 #address-cells = <3>;
1478 #interrupt-cells = <1>;
1479 reg = <0x0 0x2B000000 0x0 0x1000000
1480 0x9 0x40000000 0x0 0x10000000>;
1481 reg-names = "reg", "config";
1482 device_type = "pci";
1483 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1484 bus-range = <0x0 0xff>;
1485 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>,
1486 <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;
1487 msi-parent = <&plic>;
1489 interrupt-controller;
1490 interrupt-names = "msi";
1491 interrupt-parent = <&plic>;
1492 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1493 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1494 <0x0 0x0 0x0 0x2 &plic 0x2>,
1495 <0x0 0x0 0x0 0x3 &plic 0x3>,
1496 <0x0 0x0 0x0 0x4 &plic 0x4>;
1497 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1498 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1499 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1500 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1501 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1502 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1503 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1504 "rst_brg", "rst_core", "rst_apb";
1505 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1506 <&clkgen JH7110_PCIE0_CLK_TL>,
1507 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1508 <&clkgen JH7110_PCIE0_CLK_APB>;
1509 clock-names = "noc", "tl", "axi_mst0", "apb";
1510 status = "disabled";
1513 pcie1: pcie@2C000000 {
1514 compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1515 #address-cells = <3>;
1517 #interrupt-cells = <1>;
1518 reg = <0x0 0x2C000000 0x0 0x1000000
1519 0x9 0xc0000000 0x0 0x10000000>;
1520 reg-names = "reg", "config";
1521 device_type = "pci";
1522 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1523 bus-range = <0x0 0xff>;
1524 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>,
1525 <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
1526 msi-parent = <&plic>;
1528 interrupt-controller;
1529 interrupt-names = "msi";
1530 interrupt-parent = <&plic>;
1531 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1532 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1533 <0x0 0x0 0x0 0x2 &plic 0x2>,
1534 <0x0 0x0 0x0 0x3 &plic 0x3>,
1535 <0x0 0x0 0x0 0x4 &plic 0x4>;
1536 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1537 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1538 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1539 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1540 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1541 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1542 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1543 "rst_brg", "rst_core", "rst_apb";
1544 clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1545 <&clkgen JH7110_PCIE1_CLK_TL>,
1546 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1547 <&clkgen JH7110_PCIE1_CLK_APB>;
1548 clock-names = "noc", "tl", "axi_mst0", "apb";
1549 status = "disabled";
1552 mailbox_contrl0: mailbox@0 {
1553 compatible = "starfive,mail_box";
1554 reg = <0x0 0x13060000 0x0 0x0001000>;
1555 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1556 clock-names = "clk_apb";
1557 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1558 reset-names = "mbx_rre";
1559 interrupts = <26 27>;
1561 status = "disabled";
1564 mailbox_client0: mailbox_client@0 {
1565 compatible = "starfive,mailbox-test";
1566 mbox-names = "rx", "tx";
1567 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1568 status = "disabled";
1571 display: display-subsystem {
1572 compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1573 ports = <&dc_out_dpi0>;
1574 status = "disabled";
1577 dssctrl: dssctrl@295B0000 {
1578 compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1579 reg = <0 0x295B0000 0 0x90>;
1582 tda988x_pin: tda988x_pin {
1583 compatible = "starfive,tda998x_rgb_pin";
1584 status = "disabled";
1587 rgb_output: rgb-output {
1588 compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1589 //verisilicon,dss-syscon = <&dssctrl>;
1590 //verisilicon,mux-mask = <0x70 0x380>;
1591 //verisilicon,mux-val = <0x40 0x280>;
1592 status = "disabled";
1595 dc8200: dc8200@29400000 {
1596 compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1597 verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1598 reg = <0x0 0x29400000 0x0 0x100>,
1599 <0x0 0x29400800 0x0 0x2000>,
1600 <0x0 0x17030000 0x0 0x1000>;
1602 status = "disabled";
1603 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1604 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1605 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1606 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1607 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1608 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1609 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1610 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1611 <&clkgen JH7110_VOUT_SRC>,
1612 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1613 <&clkgen JH7110_AHB1>,
1614 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1615 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1616 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1617 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1618 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1619 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1620 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1621 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1622 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1623 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1624 <&hdmitx0_pixelclk>,
1625 <&clkvout JH7110_DC8200_PIX0>,
1626 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1627 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1628 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1629 "noc_disp","noc_isp","noc_stg","vout_src",
1630 "top_vout_axi","ahb1","top_vout_ahb",
1631 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1632 "axi_clk","core_clk","vout_ahb",
1633 "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1634 "dc8200_pix0_out","dc8200_pix1_out";
1635 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1636 <&rstgen RSTN_U0_DC8200_AXI>,
1637 <&rstgen RSTN_U0_DC8200_AHB>,
1638 <&rstgen RSTN_U0_DC8200_CORE>,
1639 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1640 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1641 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1642 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1643 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1644 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1645 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1646 "rst_noc_disp","rst_noc_stg";
1647 power-domains = <&pwrc JH7110_PD_VOUT>;
1650 dsi_output: dsi-output {
1651 compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1652 status = "disabled";
1655 mipi_dphy: mipi-dphy@295e0000{
1656 compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1657 reg = <0x0 0x295e0000 0x0 0x10000>;
1658 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1659 clock-names = "dphy_txesc";
1660 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1661 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1662 reset-names = "dphy_sys", "dphy_txbytehs";
1664 status = "disabled";
1667 mipi_dsi: mipi@295d0000 {
1668 compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1669 reg = <0x0 0x295d0000 0x0 0x10000>;
1672 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1673 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1674 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1675 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1676 clock-names = "sys", "apb", "txesc", "dpi";
1677 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1678 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1679 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1680 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1681 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1682 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1683 reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1684 "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1685 phys = <&mipi_dphy>;
1687 status = "disabled";
1690 dsi_out_port: endpoint@0 {
1691 remote-endpoint = <&panel_dsi_port>;
1693 dsi_in_port: endpoint@1 {
1694 remote-endpoint = <&mipi_out>;
1698 mipi_panel: panel@0 {
1699 /*compatible = "";*/
1704 hdmi: hdmi@29590000 {
1705 compatible = "starfive,jh7110-hdmi","inno,hdmi";
1706 reg = <0x0 0x29590000 0x0 0x4000>;
1708 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1709 /*clocks = <&cru PCLK_HDMI>;*/
1710 /*clock-names = "pclk";*/
1711 /*pinctrl-names = "default";*/
1712 /*pinctrl-0 = <&hdmi_ctl>;*/
1713 status = "disabled";
1714 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1715 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1716 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1717 <&hdmitx0_pixelclk>;
1718 clock-names = "sysclk", "mclk", "bclk", "pclk";
1719 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1720 reset-names = "hdmi_tx";
1721 #sound-dai-cells = <0>;
1725 compatible = "simple-audio-card";
1726 simple-audio-card,name = "Starfive-Multi-Sound-Card";
1727 #address-cells = <1>;
1732 compatible = "starfive,e24";
1733 reg = <0x0 0xc0110000 0x0 0x00001000>,
1734 <0x0 0xc0111000 0x0 0x0001f000>;
1735 reg-names = "ecmd", "espace";
1736 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1737 <&clkgen JH7110_E2_CLK_CORE>,
1738 <&clkgen JH7110_E2_CLK_DBG>;
1739 clock-names = "clk_rtc", "clk_core", "clk_dbg";
1740 resets = <&rstgen RSTN_U0_E24_CORE>;
1741 reset-names = "e24_core";
1742 starfive,stg-syscon = <&stg_syscon>;
1743 interrupt-parent = <&plic>;
1744 firmware-name = "e24_elf";
1746 mbox-names = "tx", "rx";
1747 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1748 #address-cells = <1>;
1750 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1751 status = "disabled";
1756 compatible = "cdns,xrp";
1757 reg = <0x0 0x10230000 0x0 0x00010000
1758 0x0 0x10240000 0x0 0x00010000>;
1759 memory-region = <&xrp_reserved>;
1760 clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1761 clock-names = "core_clk";
1762 resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1763 <&rstgen RSTN_U0_HIFI4_AXI>;
1764 reset-names = "rst_core","rst_axi";
1765 starfive,stg-syscon = <&stg_syscon>;
1766 firmware-name = "hifi4_elf";
1767 #address-cells = <1>;
1769 ranges = <0x40000000 0x0 0x20000000 0x040000
1770 0xf0000000 0x0 0xf0000000 0x03000000>;
1771 status = "disabled";
1776 starfive_cpufreq: starfive,jh7110-cpufreq {
1777 compatible = "starfive,jh7110-cpufreq";
1778 clocks = <&clkgen JH7110_PLL0_OUT>,
1779 <&clkgen JH7110_CPU_ROOT>,
1781 clock-names = "pll0", "cpu_clk", "osc";