1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright (C) 2022 StarFive Technology Co., Ltd.
4 * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
8 #include "jh7110_clk.dtsi"
9 #include <dt-bindings/reset/starfive-jh7110.h>
10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
15 compatible = "starfive,jh7110";
24 compatible = "sifive,u74-mc", "riscv";
26 d-cache-block-size = <64>;
28 d-cache-size = <8192>;
32 i-cache-block-size = <64>;
34 i-cache-size = <16384>;
37 mmu-type = "riscv,sv39";
38 next-level-cache = <&cachectrl>;
39 riscv,isa = "rv64imac";
43 cpu0intctrl: interrupt-controller {
44 #interrupt-cells = <1>;
45 compatible = "riscv,cpu-intc";
51 compatible = "sifive,u74-mc", "riscv";
53 d-cache-block-size = <64>;
55 d-cache-size = <32768>;
59 i-cache-block-size = <64>;
61 i-cache-size = <32768>;
64 mmu-type = "riscv,sv39";
65 next-level-cache = <&cachectrl>;
66 riscv,isa = "rv64imafdc";
70 cpu1intctrl: interrupt-controller {
71 #interrupt-cells = <1>;
72 compatible = "riscv,cpu-intc";
78 compatible = "sifive,u74-mc", "riscv";
80 d-cache-block-size = <64>;
82 d-cache-size = <32768>;
86 i-cache-block-size = <64>;
88 i-cache-size = <32768>;
91 mmu-type = "riscv,sv39";
92 next-level-cache = <&cachectrl>;
93 riscv,isa = "rv64imafdc";
97 cpu2intctrl: interrupt-controller {
98 #interrupt-cells = <1>;
99 compatible = "riscv,cpu-intc";
100 interrupt-controller;
105 compatible = "sifive,u74-mc", "riscv";
107 d-cache-block-size = <64>;
109 d-cache-size = <32768>;
113 i-cache-block-size = <64>;
115 i-cache-size = <32768>;
118 mmu-type = "riscv,sv39";
119 next-level-cache = <&cachectrl>;
120 riscv,isa = "rv64imafdc";
124 cpu3intctrl: interrupt-controller {
125 #interrupt-cells = <1>;
126 compatible = "riscv,cpu-intc";
127 interrupt-controller;
132 compatible = "sifive,u74-mc", "riscv";
134 d-cache-block-size = <64>;
136 d-cache-size = <32768>;
140 i-cache-block-size = <64>;
142 i-cache-size = <32768>;
145 mmu-type = "riscv,sv39";
146 next-level-cache = <&cachectrl>;
147 riscv,isa = "rv64imafdc";
151 cpu4intctrl: interrupt-controller {
152 #interrupt-cells = <1>;
153 compatible = "riscv,cpu-intc";
154 interrupt-controller;
160 compatible = "simple-bus";
161 interrupt-parent = <&plic>;
162 #address-cells = <2>;
167 cachectrl: cache-controller@2010000 {
168 compatible = "sifive,fu740-c000-ccache", "cache";
169 reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
170 reg-names = "control", "sideband";
171 interrupts = <1 3 4 2>;
172 cache-block-size = <64>;
175 cache-size = <2097152>;
179 aon_syscon: aon_syscon@17010000 {
180 compatible = "syscon";
181 reg = <0x0 0x17010000 0x0 0x1000>;
184 stg_syscon: stg_syscon@10240000 {
185 compatible = "syscon";
186 reg = <0x0 0x10240000 0x0 0x1000>;
189 sys_syscon: sys_syscon@13030000 {
190 compatible = "syscon";
191 reg = <0x0 0x13030000 0x0 0x1000>;
194 clint: clint@2000000 {
195 compatible = "riscv,clint0";
196 reg = <0x0 0x2000000 0x0 0x10000>;
197 reg-names = "control";
198 interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
199 &cpu1intctrl 3 &cpu1intctrl 7
200 &cpu2intctrl 3 &cpu2intctrl 7
201 &cpu3intctrl 3 &cpu3intctrl 7
202 &cpu4intctrl 3 &cpu4intctrl 7>;
203 #interrupt-cells = <1>;
207 compatible = "riscv,plic0";
208 reg = <0x0 0xc000000 0x0 0x4000000>;
209 reg-names = "control";
210 interrupts-extended = <&cpu0intctrl 11
211 &cpu1intctrl 11 &cpu1intctrl 9
212 &cpu2intctrl 11 &cpu2intctrl 9
213 &cpu3intctrl 11 &cpu3intctrl 9
214 &cpu4intctrl 11 &cpu4intctrl 9>;
215 interrupt-controller;
216 #interrupt-cells = <1>;
217 riscv,max-priority = <7>;
221 clkgen: clock-controller {
222 compatible = "starfive,jh7110-clkgen";
223 reg = <0x0 0x13020000 0x0 0x10000>,
224 <0x0 0x10230000 0x0 0x10000>,
225 <0x0 0x17000000 0x0 0x10000>;
226 reg-names = "sys", "stg", "aon";
227 clocks = <&osc>, <&gmac1_rmii_refin>,
229 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
230 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
231 <&tdm_ext>, <&mclk_ext>,
232 <&jtag_tck_inner>, <&bist_apb>,
233 <&stg_apb>, <&clk_rtc>,
234 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
235 clock-names = "osc", "gmac1_rmii_refin",
237 "i2stx_bclk_ext", "i2stx_lrck_ext",
238 "i2srx_bclk_ext", "i2srx_lrck_ext",
239 "tdm_ext", "mclk_ext",
240 "jtag_tck_inner", "bist_apb",
241 "stg_apb", "clk_rtc",
242 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
247 clkvout: clock-controller@295C0000 {
248 compatible = "starfive,jh7110-clk-vout";
249 reg = <0x0 0x295C0000 0x0 0x10000>;
251 clocks = <&hdmitx0_pixelclk>,
252 <&mipitx_dphy_rxesc>,
253 <&mipitx_dphy_txbytehs>;
254 clock-names = "hdmitx0_pixelclk",
256 "mipitx_dphy_txbytehs";
261 clkisp: clock-controller@19810000 {
262 compatible = "starfive,jh7110-clk-isp";
263 reg = <0x0 0x19810000 0x0 0x10000>;
266 clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
267 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
268 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
269 clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
270 "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
271 "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
272 resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
273 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
274 reset-names = "rst_isp_top_n", "rst_isp_top_axi";
278 qspi: qspi@13010000 {
279 compatible = "cadence,qspi","cdns,qspi-nor";
280 #address-cells = <1>;
282 reg = <0x0 0x13010000 0x0 0x10000
283 0x0 0x21000000 0x0 0x400000>;
284 clocks = <&clkgen JH7110_QSPI_CLK_REF>;
285 clock-names = "clk_ref";
286 resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
287 <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
288 <&rstgen RSTN_U0_CDNS_QSPI_REF>;
289 resets-names = "rst_apb", "rst_ahb", "rst_ref";
290 cdns,fifo-depth = <256>;
291 cdns,fifo-width = <4>;
292 spi-max-frequency = <250000000>;
294 nor_flash: nor-flash@0 {
295 compatible = "jedec,spi-nor";
297 spi-max-frequency = <100000000>;
306 compatible = "starfive,jh7110-otp";
307 reg = <0x0 0x17050000 0x0 0x10000>;
308 clock-frequency = <4000000>;
309 clocks = <&clkgen JH7110_OTPC_CLK_APB>;
313 USB30: usb@10100000 {
314 compatible = "cdns,usb3";
315 reg = <0x0 0x10100000 0x0 0x10000>,
316 <0x0 0x10110000 0x0 0x10000>,
317 <0x0 0x10120000 0x0 0x10000>;
318 reg-names = "otg", "xhci", "dev";
319 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
320 clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
321 <&clkgen JH7110_USB0_CLK_LPM>,
322 <&clkgen JH7110_USB0_CLK_STB>,
323 <&clkgen JH7110_USB0_CLK_USB_APB>,
324 <&clkgen JH7110_USB0_CLK_AXI>,
325 <&clkgen JH7110_USB0_CLK_UTMI_APB>;
326 clock-names = "app","lpm","stb","apb","axi","utmi";
327 resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
328 <&rstgen RSTN_U0_CDN_USB_APB>,
329 <&rstgen RSTN_U0_CDN_USB_AXI>,
330 <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
331 reset-names = "rst_pwrup","rst_apb","rst_axi","rst_utmi";
334 timer: timer@13050000 {
335 compatible = "starfive,si5-timers";
336 reg = <0x0 0x13050000 0x0 0x10000>;
337 interrupts = <69>, <70>, <71> ,<72>;
338 interrupt-names = "timer0", "timer1",
340 clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
341 <&clkgen JH7110_TIMER_CLK_TIMER1>,
342 <&clkgen JH7110_TIMER_CLK_TIMER2>,
343 <&clkgen JH7110_TIMER_CLK_TIMER3>,
344 <&clkgen JH7110_TIMER_CLK_APB>;
345 clock-names = "timer0", "timer1",
346 "timer2", "timer3", "apb_clk";
347 clock-frequency = <2000000>;
351 wdog: wdog@13070000 {
352 compatible = "starfive,dskit-wdt";
353 reg = <0x0 0x13070000 0x0 0x10000>;
355 interrupt-names = "wdog";
356 clock-frequency = <2000000>;
357 clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
358 <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
359 clock-names = "core_clk", "apb_clk";
360 resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
361 <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
362 reset-names = "rst_apb", "rst_core";
368 compatible = "starfive,rtc_hms";
369 reg = <0x0 0x17040000 0x0 0x10000>;
370 interrupts = <10>, <11>, <12>;
371 interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
372 clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
373 <&clkgen JH7110_RTC_HMS_CLK_CAL>;
374 clock-names = "pclk", "cal_clk";
375 resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
376 <&rstgen RSTN_U0_RTC_HMS_CAL>,
377 <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
378 reset-names = "rst_apb", "rst_cal", "rst_osc";
379 rtc,cal-clock-freq = <1000000>;
384 compatible = "starfive,jh7110-pmu";
385 reg = <0x0 0x17030000 0x0 0x10000>;
390 uart0: serial@10000000 {
391 compatible = "snps,dw-apb-uart";
392 reg = <0x0 0x10000000 0x0 0x10000>;
395 clocks = <&clkgen JH7110_UART0_CLK_CORE>,
396 <&clkgen JH7110_UART0_CLK_APB>;
397 clock-names = "baudclk", "apb_pclk";
398 resets = <&rstgen RSTN_U0_DW_UART_APB>;
403 uart1: serial@10010000 {
404 compatible = "snps,dw-apb-uart";
405 reg = <0x0 0x10010000 0x0 0x10000>;
408 clocks = <&clkgen JH7110_UART1_CLK_CORE>,
409 <&clkgen JH7110_UART1_CLK_APB>;
410 clock-names = "baudclk", "apb_pclk";
411 resets = <&rstgen RSTN_U1_DW_UART_APB>;
416 uart2: serial@10020000 {
417 compatible = "snps,dw-apb-uart";
418 reg = <0x0 0x10020000 0x0 0x10000>;
421 clocks = <&clkgen JH7110_UART2_CLK_CORE>,
422 <&clkgen JH7110_UART2_CLK_APB>;
423 clock-names = "baudclk", "apb_pclk";
424 resets = <&rstgen RSTN_U2_DW_UART_APB>;
429 uart3: serial@12000000 {
430 compatible = "snps,dw-apb-uart";
431 reg = <0x0 0x12000000 0x0 0x10000>;
434 clocks = <&clkgen JH7110_UART3_CLK_CORE>,
435 <&clkgen JH7110_UART3_CLK_APB>;
436 clock-names = "baudclk", "apb_pclk";
437 resets = <&rstgen RSTN_U3_DW_UART_APB>;
442 uart4: serial@12010000 {
443 compatible = "snps,dw-apb-uart";
444 reg = <0x0 0x12010000 0x0 0x10000>;
447 clocks = <&clkgen JH7110_UART4_CLK_CORE>,
448 <&clkgen JH7110_UART4_CLK_APB>;
449 clock-names = "baudclk", "apb_pclk";
450 resets = <&rstgen RSTN_U4_DW_UART_APB>;
455 uart5: serial@12020000 {
456 compatible = "snps,dw-apb-uart";
457 reg = <0x0 0x12020000 0x0 0x10000>;
460 clocks = <&clkgen JH7110_UART5_CLK_CORE>,
461 <&clkgen JH7110_UART5_CLK_APB>;
462 clock-names = "baudclk", "apb_pclk";
463 resets = <&rstgen RSTN_U5_DW_UART_APB>;
468 dma: dma-controller@16050000 {
469 compatible = "starfive,axi-dma";
470 reg = <0x0 0x16050000 0x0 0x10000>;
471 clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
472 <&clkgen JH7110_DMA1P_CLK_AHB>;
473 clock-names = "core-clk", "cfgr-clk";
474 resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
475 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
476 reset-names = "rst_axi",
481 snps,dma-masters = <1>;
482 snps,data-width = <3>;
483 snps,num-hs-if = <56>;
484 snps,block-size = <65536 65536 65536 65536>;
485 snps,priority = <0 1 2 3>;
486 snps,axi-max-burst-len = <16>;
490 gpio: gpio@13040000 {
491 compatible = "starfive_jh7110-sys-pinctrl";
492 reg = <0x0 0x13040000 0x0 0x10000>;
493 reg-names = "control";
495 interrupt-controller;
501 gpioa: gpio@17020000 {
502 compatible = "starfive_jh7110-aon-pinctrl";
503 reg = <0x0 0x17020000 0x0 0x10000>;
504 reg-names = "control";
506 interrupt-controller;
512 trng: trng@1600C000 {
513 compatible = "starfive,trng";
514 reg = <0x0 0x1600C000 0x0 0x4000>;
515 clocks = <&clkgen JH7110_SEC_HCLK>,
516 <&clkgen JH7110_SEC_MISCAHB_CLK>;
517 clock-names = "hclk", "miscahb_clk";
518 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
523 sec_dma: sec_dma@16008000 {
524 /*compatible = "arm,pl080", "arm,primecell";*/
525 compatible = "starfive,pl080";
526 reg = <0x0 0x16008000 0x0 0x4000>;
527 reg-names = "sec_dma";
528 interrupt-parent = <&plic>;
531 clock-names = "apb_pclk";
532 lli-bus-interface-ahb1;
533 /*lli-bus-interface-ahb2;*/
534 mem-bus-interface-ahb1;
535 /*mem-bus-interface-ahb2;*/
536 memcpy-burst-size = <256>;
537 memcpy-bus-width = <32>;
539 /*status = "disabled";*/
542 crypto: crypto@16000000 {
543 compatible = "starfive,jh7110-sec";
544 reg = <0x0 0x16000000 0x0 0x4000>,
545 <0x0 0x16008000 0x0 0x4000>;
546 reg-names = "secreg","secdma";
547 interrupts = <28>, <29>;
548 interrupt-names = "secirq",
550 clocks = <&clkgen JH7110_SEC_HCLK>,
551 <&clkgen JH7110_SEC_MISCAHB_CLK>;
552 clock-names = "sec_hclk","sec_ahb";
553 resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
554 reset-names = "sec_hre";
559 compatible = "snps,designware-i2c";
560 reg = <0x0 0x12060000 0x0 0x10000>;
561 clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
562 <&clkgen JH7110_I2C6_CLK_APB>;
563 clock-names = "ref", "pclk";
564 resets = <&rstgen RSTN_U6_DW_I2C_APB>;
566 #address-cells = <1>;
572 compatible = "snps,designware-i2c";
573 reg = <0x0 0x10030000 0x0 0x10000>;
574 clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
575 <&clkgen JH7110_I2C0_CLK_APB>;
576 clock-names = "ref", "pclk";
577 resets = <&rstgen RSTN_U0_DW_I2C_APB>;
579 #address-cells = <1>;
585 compatible = "snps,designware-i2c";
586 reg = <0x0 0x10040000 0x0 0x10000>;
587 clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
588 <&clkgen JH7110_I2C1_CLK_APB>;
589 clock-names = "ref", "pclk";
590 resets = <&rstgen RSTN_U1_DW_I2C_APB>;
592 #address-cells = <1>;
597 /* unremovable emmc as mmcblk0 */
598 sdio0: sdio0@16010000 {
599 compatible = "snps,dw-mshc";
600 reg = <0x0 0x16010000 0x0 0x10000>;
601 clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
602 <&clkgen JH7110_SDIO0_CLK_SDCARD>;
603 clock-names = "biu","ciu";
604 resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
605 reset-names = "reset";
608 fifo-watermark-aligned;
613 sdio1: sdio1@16020000 {
614 compatible = "snps,dw-mshc";
615 reg = <0x0 0x16020000 0x0 0x10000>;
616 clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
617 <&clkgen JH7110_SDIO1_CLK_SDCARD>;
618 clock-names = "biu","ciu";
619 resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
620 reset-names = "reset";
623 fifo-watermark-aligned;
628 vin_sysctl: vin_sysctl@19800000 {
629 compatible = "starfive,stf-vin";
630 reg = <0x0 0x19800000 0x0 0x10000>,
631 <0x0 0x19810000 0x0 0x10000>,
632 <0x0 0x19820000 0x0 0x10000>,
633 <0x0 0x19830000 0x0 0x10000>,
634 <0x0 0x19840000 0x0 0x10000>,
635 <0x0 0x19870000 0x0 0x30000>,
636 <0x0 0x198a0000 0x0 0x30000>,
637 <0x0 0x11800000 0x0 0x10000>,
638 <0x0 0x11840000 0x0 0x10000>,
639 <0x0 0x11858000 0x0 0x10000>,
640 <0x0 0x17030000 0x0 0x10000>,
641 <0x0 0x13020000 0x0 0x10000>;
642 reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl", "isp0", "isp1", "tclk", "trst", "iopad", "pmu", "syscrg";
643 interrupts = <92 87 86>;
648 compatible = "starfive,jpu";
649 reg = <0x0 0x13090000 0x0 0x300>;
651 clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
652 <&clkgen JH7110_CODAJ12_CLK_CORE>,
653 <&clkgen JH7110_CODAJ12_CLK_APB>;
654 clock-names = "axi_clk", "core_clk", "apb_clk";
655 resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
656 <&rstgen RSTN_U0_CODAJ12_CORE>,
657 <&rstgen RSTN_U0_CODAJ12_APB>;
658 reset-names = "rst_axi", "rst_core", "rst_apb";
662 vpu_dec: vpu_dec@130A0000 {
663 compatible = "starfive,vdec";
664 reg = <0x0 0x130A0000 0x0 0x10000>;
666 clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
667 <&clkgen JH7110_WAVE511_CLK_BPU>,
668 <&clkgen JH7110_WAVE511_CLK_VCE>,
669 <&clkgen JH7110_WAVE511_CLK_APB>,
670 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
671 clock-names = "axi_clk",
676 resets = <&rstgen RSTN_U0_WAVE511_AXI>,
677 <&rstgen RSTN_U0_WAVE511_BPU>,
678 <&rstgen RSTN_U0_WAVE511_VCE>,
679 <&rstgen RSTN_U0_WAVE511_APB>,
680 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
681 reset-names = "rst_axi",
686 starfive,vdec_noc_ctrl;
690 vpu_enc: vpu_enc@130B0000 {
691 compatible = "starfive,venc";
692 reg = <0x0 0x130B0000 0x0 0x10000>;
694 clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
695 <&clkgen JH7110_WAVE420L_CLK_BPU>,
696 <&clkgen JH7110_WAVE420L_CLK_VCE>,
697 <&clkgen JH7110_WAVE420L_CLK_APB>,
698 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
699 clock-names = "axi_clk",
704 resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
705 <&rstgen RSTN_U0_WAVE420L_BPU>,
706 <&rstgen RSTN_U0_WAVE420L_VCE>,
707 <&rstgen RSTN_U0_WAVE420L_APB>,
708 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
709 reset-names = "rst_axi",
714 starfive,venc_noc_ctrl;
718 rstgen: reset-controller {
719 compatible = "starfive,jh7110-reset";
720 reg = <0x0 0x13020000 0x0 0x10000>,
721 <0x0 0x10230000 0x0 0x10000>,
722 <0x0 0x17000000 0x0 0x10000>,
723 <0x0 0x19810000 0x0 0x10000>,
724 <0x0 0x295C0000 0x0 0x10000>;
725 reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
730 stmmac_axi_setup: stmmac-axi-config {
731 snps,wr_osr_lmt = <0xf>;
732 snps,rd_osr_lmt = <0xf>;
733 snps,blen = <256 128 64 32 0 0 0>;
736 gmac0: ethernet@16030000 {
737 compatible = "starfive,jh7110-eqos-5.20";
738 reg = <0x0 0x16030000 0x0 0x10000>;
744 clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
745 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
746 <&clkgen JH7110_GMAC0_PTP>,
747 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
748 <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
749 resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
750 <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
751 reset-names = "ahb", "stmmaceth";
752 interrupts = <7>, <6>, <5> ;
753 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
754 max-frame-size = <9000>;
755 phy-mode = "rgmii-id";
756 snps,multicast-filter-bins = <256>;
757 snps,perfect-filter-entries = <128>;
758 rx-fifo-depth = <262144>;
759 tx-fifo-depth = <131072>;
762 snps,force_thresh_dma_mode;
763 snps,axi-config = <&stmmac_axi_setup>;
765 snps,en-tx-lpi-clockgating;
767 snps,write-requests = <2>;
768 snps,read-requests = <16>;
769 snps,burst-map = <0x7>;
775 gmac1: ethernet@16040000 {
776 compatible = "starfive,jh7110-eqos-5.20";
777 reg = <0x0 0x16040000 0x0 0x10000>;
783 clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
784 <&clkgen JH7110_GMAC5_CLK_TX>,
785 <&clkgen JH7110_GMAC5_CLK_PTP>,
786 <&clkgen JH7110_GMAC5_CLK_AHB>,
787 <&clkgen JH7110_GMAC5_CLK_AXI>;
788 resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
789 <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
790 reset-names = "ahb", "stmmaceth";
791 interrupts = <78>, <77>, <76> ;
792 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
793 max-frame-size = <9000>;
794 phy-mode = "rgmii-id";
795 snps,multicast-filter-bins = <256>;
796 snps,perfect-filter-entries = <128>;
797 rx-fifo-depth = <262144>;
798 tx-fifo-depth = <131072>;
801 snps,force_thresh_dma_mode;
802 snps,axi-config = <&stmmac_axi_setup>;
804 snps,en-tx-lpi-clockgating;
806 snps,write-requests = <2>;
807 snps,read-requests = <16>;
808 snps,burst-map = <0x7>;
815 compatible = "img-gpu";
816 reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
817 clocks = <&gpu_core_clk>, <&gpu_sys_clk>;
818 clock-names = "gpu_core_clk","gpu_sys_clk";
820 current-clock = <8000000>;
825 compatible = "ipms,can";
826 reg = <0x0 0x130d0000 0x0 0x1000>;
828 clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
829 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
830 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
831 clock-names = "apb_clk",
834 resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
835 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
836 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
837 reset-names = "rst_apb",
840 starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
841 syscon,can_or_canfd = <0>;
846 compatible = "ipms,can";
847 reg = <0x0 0x130e0000 0x0 0x1000>;
849 clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
850 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
851 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
852 clock-names = "apb_clk",
855 resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
856 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
857 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
858 reset-names = "rst_apb",
861 starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
862 syscon,can_or_canfd = <0>;
867 compatible = "starfive,tdm";
868 reg = <0x0 0x10090000 0x0 0x1000>;
870 clocks = <&audioclk>;
871 clock-names = "audioclk";
872 dmas = <&dma 20 1>, <&dma 21 1>;
873 dma-names = "rx","tx";
874 #sound-dai-cells = <0>;
878 spdif0: spdif0@100a0000 {
879 compatible = "starfive,sf-spdif";
880 reg = <0x0 0x100a0000 0x0 0x1000>;
881 clocks = <&audioclk>;
882 clock-names = "audioclk";
884 interrupt-names = "tx";
885 #sound-dai-cells = <0>;
889 pwmdac: pwmdac@100b0000 {
890 compatible = "sf,pwmdac";
891 reg = <0x0 0x100b0000 0x0 0x1000>;
895 #sound-dai-cells = <0>;
899 i2stx: i2stx@100c0000 {
900 compatible = "snps,designware-i2stx";
901 reg = <0x0 0x100c0000 0x0 0x1000>;
903 clock-names = "i2sclk";
904 interrupt-names = "tx";
905 #sound-dai-cells = <0>;
912 compatible = "starfive,sf-pdm";
913 reg = <0x0 0x100d0000 0x0 0x1000>;
915 clocks = <&audioclk>;
916 clock-names = "audioclk";
917 #sound-dai-cells = <0>;
921 i2srx_3ch: i2srx-3ch@100e0000 {
922 compatible = "snps,designware-i2srx";
923 reg = <0x0 0x100e0000 0x0 0x1000>;
925 clock-names = "i2sclk";
927 interrupt-names = "rx";
928 #sound-dai-cells = <0>;
932 i2stx_4ch0: i2stx-4ch0@120b0000 {
933 compatible = "snps,designware-i2stx-4ch0";
934 reg = <0x0 0x120b0000 0x0 0x1000>;
936 clock-names = "i2sclk";
938 interrupt-names = "tx";
939 #sound-dai-cells = <0>;
943 i2stx_4ch1: i2sdac1@120c0000 {
944 compatible = "snps,designware-i2stx-4ch1";
945 reg = <0x0 0x120c0000 0x0 0x1000>;
947 clock-names = "i2sclk";
949 interrupt-names = "tx";
950 #sound-dai-cells = <0>;
955 compatible = "starfive,pwm0";
956 reg = <0x0 0x120d0000 0x0 0x10000>;
957 reg-names = "control";
958 clocks = <&clkgen JH7110_PWM_CLK_APB>;
959 resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
960 starfive,approx-period = <2000000>;
966 spdif_transmitter: spdif_transmitter {
967 compatible = "linux,spdif-dit";
968 #sound-dai-cells = <0>;
972 spdif_receiver: spdif_receiver {
973 compatible = "linux,spdif-dir";
974 #sound-dai-cells = <0>;
978 pwmdac_codec: pwmdac-transmitter {
979 compatible = "linux,pwmdac-dit";
980 #sound-dai-cells = <0>;
984 dmic_codec: dmic_codec {
985 compatible = "dmic-codec";
986 #sound-dai-cells = <0>;
990 spi0: spi0@10060000 {
991 compatible = "arm,pl022", "arm,primecell";
992 reg = <0x0 0x10060000 0x0 0x10000>;
994 clock-names = "apb_pclk";
996 dmas = <&dma 14 1>, <&dma 15 1>;
997 dma-names = "rx","tx";
998 arm,primecell-periphid = <0x00041022>;
1000 #address-cells = <1>;
1002 status = "disabled";
1005 pcie0: pcie0@2B000000 {
1006 compatible = "plda,pci-xpressrich3-axi";
1007 reg = <0x0 0x2B000000 0x0 0x1000000
1008 0x9 0x40000000 0x0 0x10000000>;
1009 reg-names = "reg", "config";
1011 interrupt-controller;
1012 interrupt-names = "msi";
1013 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1014 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1015 <0x0 0x0 0x0 0x2 &plic 0x2>,
1016 <0x0 0x0 0x0 0x3 &plic 0x3>,
1017 <0x0 0x0 0x0 0x4 &plic 0x4>;
1018 resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1019 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1020 <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1021 <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1022 <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1023 <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1024 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1025 "rst_brg", "rst_core", "rst_apb";
1026 clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
1027 <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1028 <&clkgen JH7110_PCIE0_CLK_APB>;
1029 clock-names = "tl", "axi_mst0", "apb";
1030 #interrupt-cells = <1>;
1031 device_type = "pci";
1032 starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1033 bus-range = <0x0 0xff>;
1034 msi-parent = <&plic>;
1035 #address-cells = <3>;
1037 ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x06000000>;
1038 status = "disabled";
1041 pcie1:pcie1@2C000000 {
1042 compatible = "plda,pci-xpressrich3-axi";
1043 reg = <0x0 0x2C000000 0x0 0x1000000
1044 0x9 0xc0000000 0x0 0x10000000>;
1045 reg-names = "reg", "config";
1046 device_type = "pci";
1047 starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1048 bus-range = <0x0 0xff>;
1049 #address-cells = <3>;
1051 #interrupt-cells = <1>;
1052 ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x06000000>;
1053 msi-parent = <&plic>;
1055 interrupt-controller;
1056 interrupt-names = "msi";
1057 interrupt-parent = <&plic>;
1058 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1059 interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1060 <0x0 0x0 0x0 0x2 &plic 0x2>,
1061 <0x0 0x0 0x0 0x3 &plic 0x3>,
1062 <0x0 0x0 0x0 0x4 &plic 0x4>;
1063 resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1064 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1065 <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1066 <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1067 <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1068 <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1069 reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1070 "rst_brg", "rst_core", "rst_apb";
1071 clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
1072 <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1073 <&clkgen JH7110_PCIE1_CLK_APB>;
1074 clock-names = "tl", "axi_mst0", "apb";
1075 status = "disabled";
1078 mailbox_contrl0: mailbox@0 {
1079 compatible = "starfive,mail_box";
1080 reg = <0x0 0x13060000 0x0 0x0001000>;
1081 clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1082 clock-names = "clk_apb";
1083 resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1084 reset-names = "mbx_rre";
1085 interrupts = <26 27>;
1087 status = "disabled";
1090 mailbox_client0: mailbox_client@0 {
1091 compatible = "starfive,mailbox-test";
1092 mbox-names = "rx", "tx";
1093 mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1094 status = "disabled";
1097 display: display-subsystem {
1098 compatible = "verisilicon,display-subsystem";
1099 ports = <&dc_out_dpi0>;
1100 status = "disabled";
1103 dssctrl: dssctrl@295B0000 {
1104 compatible = "verisilicon,dss-ctrl", "syscon";
1105 reg = <0 0x295B0000 0 0x90>;
1108 hdmi_output: hdmi-output {
1109 compatible = "verisilicon,hdmi-encoder";
1110 verisilicon,dss-syscon = <&dssctrl>;
1111 verisilicon,mux-mask = <0x70 0x380>;
1112 verisilicon,mux-val = <0x40 0x280>;
1113 status = "disabled";
1116 dc8200: dc8200@29400000 {
1117 compatible = "verisilicon,dc8200";
1118 reg = <0x0 0x29400000 0x0 0x100>,
1119 <0x0 0x29400800 0x0 0x2000>,
1120 <0x0 0x17030000 0x0 0x1000>;
1122 status = "disabled";
1123 clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1124 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1125 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1126 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1127 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1128 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1129 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1130 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1131 <&clkgen JH7110_VOUT_SRC>,
1132 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1133 <&clkgen JH7110_AHB1>,
1134 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1135 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1136 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1138 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1139 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1140 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1141 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1142 <&clkvout JH7110_U0_DC8200_CLK_AHB>;
1143 clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1144 "noc_disp","noc_isp","noc_stg","vout_src",
1145 "top_vout_axi","ahb1","top_vout_ahb",
1146 "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1147 "axi_clk","core_clk","vout_ahb";
1149 resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1150 <&rstgen RSTN_U0_DC8200_AXI>,
1151 <&rstgen RSTN_U0_DC8200_AHB>,
1152 <&rstgen RSTN_U0_DC8200_CORE>,
1153 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1154 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1155 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1156 <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
1157 <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
1158 <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
1159 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1160 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
1161 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
1162 <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
1163 reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1164 "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1165 "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
1166 "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
1171 mipi_dphy: mipi-dphy@295e0000{
1172 compatible = "starfive,jh7100-mipi-dphy-tx";
1173 reg = <0x0 0x295e0000 0x0 0x10000>;
1174 /*clocks = <&uartclk>, <&apb2clk>;*/
1175 /*clock-names = "baudclk", "apb_pclk";*/
1176 clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1177 clock-names = "dphy_txesc";
1178 resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1179 <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1180 reset-names = "dphy_sys",
1183 status = "disabled";
1186 mipi_dsi: mipi@295d0000 {
1187 compatible = "cdns,dsi";
1188 reg = <0x0 0x295d0000 0x0 0x10000>;
1190 /*clocks = <&apb1clk>, <&apb2clk>;*/
1191 /*clock-names = "dsi_p_clk", "dsi_sys_clk";*/
1192 clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1193 <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1194 <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1195 <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1196 clock-names = "sys",
1200 resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1201 <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1202 <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1203 <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1204 <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1205 <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1206 reset-names = "dsi_dpi",
1212 phys = <&mipi_dphy>;
1214 status = "disabled";
1217 dsi_out_port: endpoint {
1218 /*remote-endpoint = <&panel_dsi_port>;*/
1222 mipi_panel: panel@0 {
1223 /*compatible = "";*/
1224 status = "disabled";
1228 hdmi: hdmi@29590000 {
1229 compatible = "rockchip,rk3036-inno-hdmi";
1230 reg = <0x29590000 0x4000>;
1231 /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1232 /*clocks = <&cru PCLK_HDMI>;*/
1233 /*clock-names = "pclk";*/
1234 /*pinctrl-names = "default";*/
1235 /*pinctrl-0 = <&hdmi_ctl>;*/
1236 status = "disabled";
1237 clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1238 <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1239 <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
1240 clock-names = "sysclk",
1243 resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1244 reset-names = "hdmi_tx";
1247 #address-cells = <1>;
1249 hdmi_in_lcdc: endpoint@0 {
1251 remote-endpoint = <&dc_out_dpi0>;
1256 sound_pwmdac: snd-card_pwmdac {
1257 compatible = "simple-audio-card";
1258 simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
1259 simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
1260 simple-audio-card,frame-master = <&pwmdac_dailink_master>;
1261 simple-audio-card,format = "left_j";
1262 status = "disabled";
1264 pwmdac_dailink_master: simple-audio-card,cpu {
1265 sound-dai = <&pwmdac>;
1268 simple-audio-card,codec {
1269 sound-dai = <&pwmdac_codec>;
1274 compatible = "starfive,e24";
1275 reg = <0x0 0xc0110000 0x0 0x00001000
1276 0x0 0xc0111000 0x0 0x0001f000>;
1277 reg-names = "ecmd","espace";
1278 clocks = <&clkgen JH7110_E2_RTC_CLK>,
1279 <&clkgen JH7110_E2_CLK_CORE>,
1280 <&clkgen JH7110_E2_CLK_DBG>;
1281 clock-names = "clk_rtc","clk_core","clk_dbg";
1282 resets = <&rstgen RSTN_U0_E24_CORE>;
1283 reset-names = "e24_core";
1284 starfive,stg-syscon = <&stg_syscon>;
1285 interrupt-parent = <&plic>;
1286 firmware-name = "e24_elf";
1288 mbox-names = "tx", "rx";
1289 mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1290 #address-cells = <1>;
1292 ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1293 status = "disabled";