arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <880000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <880000>;
  30                         };
  31                         opp-625000000 {
  32                                         opp-hz = /bits/ 64 <625000000>;
  33                                         opp-microvolt = <880000>;
  34                         };
  35                         opp-750000000 {
  36                                         opp-hz = /bits/ 64 <750000000>;
  37                                         opp-microvolt = <880000>;
  38                         };
  39                         opp-875000000 {
  40                                         opp-hz = /bits/ 64 <875000000>;
  41                                         opp-microvolt = <880000>;
  42                         };
  43                         opp-1000000000 {
  44                                         opp-hz = /bits/ 64 <1000000000>;
  45                                         opp-microvolt = <900000>;
  46                         };
  47                         opp-1250000000 {
  48                                         opp-hz = /bits/ 64 <1250000000>;
  49                                         opp-microvolt = <950000>;
  50                         };
  51                         opp-1375000000 {
  52                                         opp-hz = /bits/ 64 <1375000000>;
  53                                         opp-microvolt = <1000000>;
  54                         };
  55                         opp-1500000000 {
  56                                         opp-hz = /bits/ 64 <1500000000>;
  57                                         opp-microvolt = <1100000>;
  58                         };
  59                         opp-1625000000 {
  60                                         opp-hz = /bits/ 64 <1625000000>;
  61                                         opp-microvolt = <1100000>;
  62                         };
  63                         opp-1750000000 {
  64                                         opp-hz = /bits/ 64 <1750000000>;
  65                                         opp-microvolt = <1200000>;
  66                         };
  67         };
  68
  69         cpus {
  70                 #address-cells = <1>;
  71                 #size-cells = <0>;
  72
  73                 cpu0: cpu@0 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <0>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <8192>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <16384>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         cpu-idle-states = <&CPU_NONRET_0_0>;
  89                         next-level-cache = <&cachectrl>;
  90                         riscv,isa = "rv64imac";
  91                         tlb-split;
  92                         status = "disabled";
  93
  94                         cpu0intctrl: interrupt-controller {
  95                                 #interrupt-cells = <1>;
  96                                 compatible = "riscv,cpu-intc";
  97                                 interrupt-controller;
  98                         };
  99                 };
 100
 101                 cpu1: cpu@1 {
 102                         compatible = "sifive,u74-mc", "riscv";
 103                         reg = <1>;
 104                         d-cache-block-size = <64>;
 105                         d-cache-sets = <64>;
 106                         d-cache-size = <32768>;
 107                         d-tlb-sets = <1>;
 108                         d-tlb-size = <40>;
 109                         device_type = "cpu";
 110                         i-cache-block-size = <64>;
 111                         i-cache-sets = <64>;
 112                         i-cache-size = <32768>;
 113                         i-tlb-sets = <1>;
 114                         i-tlb-size = <40>;
 115                         mmu-type = "riscv,sv39";
 116                         cpu-idle-states = <&CPU_NONRET_0_0>;
 117                         next-level-cache = <&cachectrl>;
 118                         riscv,isa = "rv64imafdc";
 119                         tlb-split;
 120                         status = "okay";
 121                         operating-points-v2 = <&cluster0_opp>;
 122
 123                         cpu1intctrl: interrupt-controller {
 124                                 #interrupt-cells = <1>;
 125                                 compatible = "riscv,cpu-intc";
 126                                 interrupt-controller;
 127                         };
 128                 };
 129
 130                 cpu2: cpu@2 {
 131                         compatible = "sifive,u74-mc", "riscv";
 132                         reg = <2>;
 133                         d-cache-block-size = <64>;
 134                         d-cache-sets = <64>;
 135                         d-cache-size = <32768>;
 136                         d-tlb-sets = <1>;
 137                         d-tlb-size = <40>;
 138                         device_type = "cpu";
 139                         i-cache-block-size = <64>;
 140                         i-cache-sets = <64>;
 141                         i-cache-size = <32768>;
 142                         i-tlb-sets = <1>;
 143                         i-tlb-size = <40>;
 144                         mmu-type = "riscv,sv39";
 145                         cpu-idle-states = <&CPU_NONRET_0_0>;
 146                         next-level-cache = <&cachectrl>;
 147                         riscv,isa = "rv64imafdc";
 148                         tlb-split;
 149                         status = "okay";
 150                         operating-points-v2 = <&cluster0_opp>;
 151
 152                         cpu2intctrl: interrupt-controller {
 153                                 #interrupt-cells = <1>;
 154                                 compatible = "riscv,cpu-intc";
 155                                 interrupt-controller;
 156                         };
 157                 };
 158
 159                 cpu3: cpu@3 {
 160                         compatible = "sifive,u74-mc", "riscv";
 161                         reg = <3>;
 162                         d-cache-block-size = <64>;
 163                         d-cache-sets = <64>;
 164                         d-cache-size = <32768>;
 165                         d-tlb-sets = <1>;
 166                         d-tlb-size = <40>;
 167                         device_type = "cpu";
 168                         i-cache-block-size = <64>;
 169                         i-cache-sets = <64>;
 170                         i-cache-size = <32768>;
 171                         i-tlb-sets = <1>;
 172                         i-tlb-size = <40>;
 173                         mmu-type = "riscv,sv39";
 174                         cpu-idle-states = <&CPU_NONRET_0_0>;
 175                         next-level-cache = <&cachectrl>;
 176                         riscv,isa = "rv64imafdc";
 177                         tlb-split;
 178                         status = "okay";
 179                         operating-points-v2 = <&cluster0_opp>;
 180
 181                         cpu3intctrl: interrupt-controller {
 182                                 #interrupt-cells = <1>;
 183                                 compatible = "riscv,cpu-intc";
 184                                 interrupt-controller;
 185                         };
 186                 };
 187
 188                 cpu4: cpu@4 {
 189                         compatible = "sifive,u74-mc", "riscv";
 190                         reg = <4>;
 191                         d-cache-block-size = <64>;
 192                         d-cache-sets = <64>;
 193                         d-cache-size = <32768>;
 194                         d-tlb-sets = <1>;
 195                         d-tlb-size = <40>;
 196                         device_type = "cpu";
 197                         i-cache-block-size = <64>;
 198                         i-cache-sets = <64>;
 199                         i-cache-size = <32768>;
 200                         i-tlb-sets = <1>;
 201                         i-tlb-size = <40>;
 202                         mmu-type = "riscv,sv39";
 203                         cpu-idle-states = <&CPU_NONRET_0_0>;
 204                         next-level-cache = <&cachectrl>;
 205                         riscv,isa = "rv64imafdc";
 206                         tlb-split;
 207                         status = "okay";
 208                         operating-points-v2 = <&cluster0_opp>;
 209
 210                         cpu4intctrl: interrupt-controller {
 211                                 #interrupt-cells = <1>;
 212                                 compatible = "riscv,cpu-intc";
 213                                 interrupt-controller;
 214                         };
 215                 };
 216         };
 217
 218         idle-states {
 219                 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
 220                         compatible = "riscv,idle-state";
 221                         riscv,sbi-suspend-param = <0x80000000>;
 222                         entry-latency-us = <600>;
 223                         exit-latency-us = <1100>;
 224                         min-residency-us = <2700>;
 225                         wakeup-latency-us = <1500>;
 226                 };
 227         };
 228
 229         soc: soc {
 230                 compatible = "simple-bus";
 231                 interrupt-parent = <&plic>;
 232                 #address-cells = <2>;
 233                 #size-cells = <2>;
 234                 #clock-cells = <1>;
 235                 ranges;
 236
 237                 cachectrl: cache-controller@2010000 {
 238                         compatible = "sifive,fu740-c000-ccache", "cache";
 239                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 240                         reg-names = "control", "sideband";
 241                         interrupts = <1 3 4 2>;
 242                         cache-block-size = <64>;
 243                         cache-level = <2>;
 244                         cache-sets = <2048>;
 245                         cache-size = <2097152>;
 246                         cache-unified;
 247                 };
 248
 249                 aon_syscon: aon_syscon@17010000 {
 250                         compatible = "syscon";
 251                         reg = <0x0 0x17010000 0x0 0x1000>;
 252                 };
 253
 254                 stg_syscon: stg_syscon@10240000 {
 255                         compatible = "syscon";
 256                         reg = <0x0 0x10240000 0x0 0x1000>;
 257                 };
 258
 259                 sys_syscon: sys_syscon@13030000 {
 260                         compatible = "syscon";
 261                         reg = <0x0 0x13030000 0x0 0x1000>;
 262                 };
 263
 264                 clint: clint@2000000 {
 265                         compatible = "riscv,clint0";
 266                         reg = <0x0 0x2000000 0x0 0x10000>;
 267                         reg-names = "control";
 268                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 269                                                 &cpu1intctrl 3 &cpu1intctrl 7
 270                                                 &cpu2intctrl 3 &cpu2intctrl 7
 271                                                 &cpu3intctrl 3 &cpu3intctrl 7
 272                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 273                         #interrupt-cells = <1>;
 274                 };
 275
 276                 plic: plic@c000000 {
 277                         compatible = "riscv,plic0";
 278                         reg = <0x0 0xc000000 0x0 0x4000000>;
 279                         reg-names = "control";
 280                         interrupts-extended = <&cpu0intctrl 11
 281                                                 &cpu1intctrl 11 &cpu1intctrl 9
 282                                                 &cpu2intctrl 11 &cpu2intctrl 9
 283                                                 &cpu3intctrl 11 &cpu3intctrl 9
 284                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 285                         interrupt-controller;
 286                         #interrupt-cells = <1>;
 287                         riscv,max-priority = <7>;
 288                         riscv,ndev = <136>;
 289                 };
 290
 291                 clkgen: clock-controller {
 292                         compatible = "starfive,jh7110-clkgen";
 293                         reg = <0x0 0x13020000 0x0 0x10000>,
 294                                 <0x0 0x10230000 0x0 0x10000>,
 295                                 <0x0 0x17000000 0x0 0x10000>;
 296                         reg-names = "sys", "stg", "aon";
 297                         clocks = <&osc>, <&gmac1_rmii_refin>,
 298                                  <&gmac1_rgmii_rxin>,
 299                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 300                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 301                                  <&tdm_ext>, <&mclk_ext>,
 302                                  <&jtag_tck_inner>, <&bist_apb>,
 303                                  <&clk_rtc>,
 304                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 305                         clock-names = "osc", "gmac1_rmii_refin",
 306                                 "gmac1_rgmii_rxin",
 307                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 308                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 309                                 "tdm_ext", "mclk_ext",
 310                                 "jtag_tck_inner", "bist_apb",
 311                                 "clk_rtc",
 312                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 313                         #clock-cells = <1>;
 314                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 315                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 316                         status = "okay";
 317                 };
 318
 319                 clkvout: clock-controller@295C0000 {
 320                         compatible = "starfive,jh7110-clk-vout";
 321                         reg = <0x0 0x295C0000 0x0 0x10000>;
 322                         reg-names = "vout";
 323                         clocks = <&hdmitx0_pixelclk>,
 324                                  <&mipitx_dphy_rxesc>,
 325                                  <&mipitx_dphy_txbytehs>,
 326                                  <&clkgen JH7110_VOUT_SRC>,
 327                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 328                         clock-names = "hdmitx0_pixelclk",
 329                                       "mipitx_dphy_rxesc",
 330                                       "mipitx_dphy_txbytehs",
 331                                       "vout_src",
 332                                       "vout_top_ahb";
 333                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 334                         reset-names = "vout_src";
 335                         #clock-cells = <1>;
 336                         power-domains = <&pwrc JH7110_PD_VOUT>;
 337                         status = "okay";
 338                 };
 339
 340                 clkisp: clock-controller@19810000 {
 341                         compatible = "starfive,jh7110-clk-isp";
 342                         reg = <0x0 0x19810000 0x0 0x10000>;
 343                         reg-names = "isp";
 344                         #clock-cells = <1>;
 345                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 346                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 347                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 348                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 349                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 350                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 351                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 352                                       "u0_sft7110_noc_bus_clk_isp_axi";
 353                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 354                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 355                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 356                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 357                                       "rst_isp_noc_bus_n";
 358                         power-domains = <&pwrc JH7110_PD_ISP>;
 359                         status = "okay";
 360                 };
 361
 362                 qspi: spi@13010000 {
 363                         compatible = "cdns,qspi-nor";
 364                         #address-cells = <1>;
 365                         #size-cells = <0>;
 366                         reg = <0x0 0x13010000 0x0 0x10000
 367                                 0x0 0x21000000 0x0 0x400000>;
 368                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 369                         clock-names = "clk_ref";
 370                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 371                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 372                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 373                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 374                         cdns,fifo-depth = <256>;
 375                         cdns,fifo-width = <4>;
 376                         spi-max-frequency = <250000000>;
 377
 378                         nor_flash: nor-flash@0 {
 379                                 compatible = "jedec,spi-nor";
 380                                 reg=<0>;
 381                                 spi-max-frequency = <100000000>;
 382                                 cdns,tshsl-ns = <1>;
 383                                 cdns,tsd2d-ns = <1>;
 384                                 cdns,tchsh-ns = <1>;
 385                                 cdns,tslch-ns = <1>;
 386                         };
 387                 };
 388
 389                 otp: otp@17050000 {
 390                         compatible = "starfive,jh7110-otp";
 391                         reg = <0x0 0x17050000 0x0 0x10000>;
 392                         clock-frequency = <4000000>;
 393                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 394                         clock-names = "apb";
 395                 };
 396
 397                 usbdrd30: usbdrd{
 398                         compatible = "starfive,jh7110-cdns3";
 399                         reg = <0x0 0x10210000 0x0 0x1000>,
 400                               <0x0 0x10200000 0x0 0x1000>;
 401                         clocks = <&clkgen JH7110_USB_125M>,
 402                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 403                                  <&clkgen JH7110_USB0_CLK_LPM>,
 404                                  <&clkgen JH7110_USB0_CLK_STB>,
 405                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 406                                  <&clkgen JH7110_USB0_CLK_AXI>,
 407                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 408                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 409                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 410                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 411                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 412                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 413                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 414                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 415                         reset-names = "pwrup","apb","axi","utmi", "phy";
 416                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 417                         starfive,sys-syscon = <&sys_syscon 0x18>;
 418                         status = "disabled";
 419                         #address-cells = <2>;
 420                         #size-cells = <2>;
 421                         #interrupt-cells = <1>;
 422                         ranges;
 423                         usbdrd_cdns3: usb@10100000 {
 424                                 compatible = "cdns,usb3";
 425                                 reg = <0x0 0x10100000 0x0 0x10000>,
 426                                       <0x0 0x10110000 0x0 0x10000>,
 427                                       <0x0 0x10120000 0x0 0x10000>;
 428                                 reg-names = "otg", "xhci", "dev";
 429                                 interrupts = <100>, <108>, <110>;
 430                                 interrupt-names = "host", "peripheral", "otg";
 431                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 432                                 maximum-speed = "super-speed";
 433                         };
 434                 };
 435
 436                 timer: timer@13050000 {
 437                         compatible = "starfive,jh7110-timers";
 438                         reg = <0x0 0x13050000 0x0 0x10000>;
 439                         interrupts = <69>, <70>, <71> ,<72>;
 440                         interrupt-names = "timer0", "timer1",
 441                                           "timer2", "timer3";
 442                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 443                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 444                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 445                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 446                                  <&clkgen JH7110_TIMER_CLK_APB>;
 447                         clock-names = "timer0", "timer1",
 448                                       "timer2", "timer3", "apb_clk";
 449                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 450                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 451                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 452                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 453                                  <&rstgen RSTN_U0_TIMER_APB>;
 454                         reset-names = "timer0", "timer1",
 455                                       "timer2", "timer3", "apb_rst";
 456                         clock-frequency = <24000000>;
 457                         status = "okay";
 458                 };
 459
 460                 wdog: wdog@13070000 {
 461                         compatible = "starfive,jh7110-wdt";
 462                         reg = <0x0 0x13070000 0x0 0x10000>;
 463                         interrupts = <68>;
 464                         interrupt-names = "wdog";
 465                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 466                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 467                         clock-names = "core_clk", "apb_clk";
 468                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 469                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 470                         reset-names = "rst_apb", "rst_core";
 471                         timeout-sec = <15>;
 472                         status = "okay";
 473                 };
 474
 475                 rtc: rtc@17040000 {
 476                         compatible = "starfive,jh7110-rtc";
 477                         reg = <0x0 0x17040000 0x0 0x10000>;
 478                         interrupts = <10>, <11>, <12>;
 479                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 480                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 481                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 482                         clock-names = "pclk", "cal_clk";
 483                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 484                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 485                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 486                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 487                         rtc,cal-clock-freq = <1000000>;
 488                         status = "okay";
 489                 };
 490
 491                 pwrc: power-controller@17030000 {
 492                         compatible = "starfive,jh7110-pmu";
 493                         reg = <0x0 0x17030000 0x0 0x10000>;
 494                         interrupts = <111>;
 495                         #power-domain-cells = <1>;
 496                         status = "okay";
 497                 };
 498
 499                 uart0: serial@10000000 {
 500                         compatible = "snps,dw-apb-uart";
 501                         reg = <0x0 0x10000000 0x0 0x10000>;
 502                         reg-io-width = <4>;
 503                         reg-shift = <2>;
 504                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 505                                  <&clkgen JH7110_UART0_CLK_APB>;
 506                         clock-names = "baudclk", "apb_pclk";
 507                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 508                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 509                         interrupts = <32>;
 510                         status = "disabled";
 511                 };
 512
 513                 uart1: serial@10010000 {
 514                         compatible = "snps,dw-apb-uart";
 515                         reg = <0x0 0x10010000 0x0 0x10000>;
 516                         reg-io-width = <4>;
 517                         reg-shift = <2>;
 518                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 519                                  <&clkgen JH7110_UART1_CLK_APB>;
 520                         clock-names = "baudclk", "apb_pclk";
 521                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 522                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 523                         interrupts = <33>;
 524                         status = "disabled";
 525                 };
 526
 527                 uart2: serial@10020000 {
 528                         compatible = "snps,dw-apb-uart";
 529                         reg = <0x0 0x10020000 0x0 0x10000>;
 530                         reg-io-width = <4>;
 531                         reg-shift = <2>;
 532                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 533                                  <&clkgen JH7110_UART2_CLK_APB>;
 534                         clock-names = "baudclk", "apb_pclk";
 535                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 536                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 537                         interrupts = <34>;
 538                         status = "disabled";
 539                 };
 540
 541                 uart3: serial@12000000 {
 542                         compatible = "snps,dw-apb-uart";
 543                         reg = <0x0 0x12000000 0x0 0x10000>;
 544                         reg-io-width = <4>;
 545                         reg-shift = <2>;
 546                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 547                                  <&clkgen JH7110_UART3_CLK_APB>;
 548                         clock-names = "baudclk", "apb_pclk";
 549                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 550                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 551                         interrupts = <45>;
 552                         status = "disabled";
 553                 };
 554
 555                 uart4: serial@12010000 {
 556                         compatible = "snps,dw-apb-uart";
 557                         reg = <0x0 0x12010000 0x0 0x10000>;
 558                         reg-io-width = <4>;
 559                         reg-shift = <2>;
 560                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 561                                  <&clkgen JH7110_UART4_CLK_APB>;
 562                         clock-names = "baudclk", "apb_pclk";
 563                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 564                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 565                         interrupts = <46>;
 566                         status = "disabled";
 567                 };
 568
 569                 uart5: serial@12020000 {
 570                         compatible = "snps,dw-apb-uart";
 571                         reg = <0x0 0x12020000 0x0 0x10000>;
 572                         reg-io-width = <4>;
 573                         reg-shift = <2>;
 574                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 575                                  <&clkgen JH7110_UART5_CLK_APB>;
 576                         clock-names = "baudclk", "apb_pclk";
 577                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 578                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 579                         interrupts = <47>;
 580                         status = "disabled";
 581                 };
 582
 583                 dma: dma-controller@16050000 {
 584                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 585                         reg = <0x0 0x16050000 0x0 0x10000>;
 586                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 587                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 588                         clock-names = "core-clk", "cfgr-clk";
 589                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 590                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 591                         reset-names = "rst_axi", "rst_ahb";
 592                         interrupts = <73>;
 593                         #dma-cells = <2>;
 594                         dma-channels = <4>;
 595                         snps,dma-masters = <1>;
 596                         snps,data-width = <3>;
 597                         snps,num-hs-if = <56>;
 598                         snps,block-size = <65536 65536 65536 65536>;
 599                         snps,priority = <0 1 2 3>;
 600                         snps,axi-max-burst-len = <16>;
 601                         status = "disabled";
 602                 };
 603
 604                 gpio: gpio@13040000 {
 605                         compatible = "starfive,jh7110-sys-pinctrl";
 606                         reg = <0x0 0x13040000 0x0 0x10000>;
 607                         reg-names = "control";
 608                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 609                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 610                         interrupts = <86>;
 611                         interrupt-controller;
 612                         #gpio-cells = <2>;
 613                         ngpios = <64>;
 614                         status = "okay";
 615                 };
 616
 617                 gpioa: gpio@17020000 {
 618                         compatible = "starfive,jh7110-aon-pinctrl";
 619                         reg = <0x0 0x17020000 0x0 0x10000>;
 620                         reg-names = "control";
 621                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 622                         interrupts = <85>;
 623                         interrupt-controller;
 624                         #gpio-cells = <2>;
 625                         ngpios = <4>;
 626                         status = "okay";
 627                 };
 628
 629                 sfctemp: tmon@120e0000  {
 630                         compatible = "starfive,jh7110-temp";
 631                         reg = <0x0 0x120e0000 0x0 0x10000>;
 632                         interrupts = <81>;
 633                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 634                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 635                         clock-names = "sense", "bus";
 636                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 637                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 638                         reset-names = "sense", "bus";
 639                         #thermal-sensor-cells = <0>;
 640                         status = "disabled";
 641                 };
 642
 643                 thermal-zones {
 644                         cpu-thermal {
 645                                 polling-delay-passive = <250>;
 646                                 polling-delay = <15000>;
 647
 648                                 thermal-sensors = <&sfctemp>;
 649
 650                                 cooling-maps {
 651                                 };
 652
 653                                 trips {
 654                                         cpu_alert0: cpu_alert0 {
 655                                                 /* milliCelsius */
 656                                                 temperature = <75000>;
 657                                                 hysteresis = <2000>;
 658                                                 type = "passive";
 659                                         };
 660
 661                                         cpu_crit: cpu_crit {
 662                                                 /* milliCelsius */
 663                                                 temperature = <90000>;
 664                                                 hysteresis = <2000>;
 665                                                 type = "critical";
 666                                         };
 667                                 };
 668                         };
 669                 };
 670
 671                 trng: trng@1600C000 {
 672                         compatible = "starfive,jh7110-trng";
 673                         reg = <0x0 0x1600C000 0x0 0x4000>;
 674                         clocks = <&clkgen JH7110_SEC_HCLK>,
 675                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 676                         clock-names = "hclk", "miscahb_clk";
 677                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 678                         interrupts = <30>;
 679                         status = "disabled";
 680                 };
 681
 682                 sec_dma: sec_dma@16008000 {
 683                         compatible = "arm,pl080", "arm,primecell";
 684                         arm,primecell-periphid = <0x00041080>;
 685                         reg = <0x0 0x16008000 0x0 0x4000>;
 686                         reg-names = "sec_dma";
 687                         interrupts = <29>;
 688                         clocks = <&clkgen JH7110_SEC_HCLK>,
 689                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 690                         clock-names = "sec_hclk","apb_pclk";
 691                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 692                         reset-names = "sec_hre";
 693                         lli-bus-interface-ahb1;
 694                         mem-bus-interface-ahb1;
 695                         memcpy-burst-size = <256>;
 696                         memcpy-bus-width = <32>;
 697                         #dma-cells = <2>;
 698                         status = "disabled";
 699                 };
 700
 701                 crypto: crypto@16000000 {
 702                         compatible = "starfive,jh7110-sec";
 703                         reg = <0x0 0x16000000 0x0 0x4000>,
 704                               <0x0 0x16008000 0x0 0x4000>;
 705                         reg-names = "secreg","secdma";
 706                         interrupts = <28>, <29>;
 707                         interrupt-names = "secirq", "dmairq";
 708                         clocks = <&clkgen JH7110_SEC_HCLK>,
 709                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 710                         clock-names = "sec_hclk","sec_ahb";
 711                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 712                         reset-names = "sec_hre";
 713                         enable-side-channel-mitigation = "true";
 714                         enable-dma = "true";
 715                         dmas = <&sec_dma 1 2>,
 716                                <&sec_dma 0 2>;
 717                         dma-names = "sec_m","sec_p";
 718                         status = "disabled";
 719                 };
 720
 721                 i2c0: i2c@10030000 {
 722                         compatible = "snps,designware-i2c";
 723                         reg = <0x0 0x10030000 0x0 0x10000>;
 724                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 725                                  <&clkgen JH7110_I2C0_CLK_APB>;
 726                         clock-names = "ref", "pclk";
 727                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 728                         interrupts = <35>;
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                         status = "disabled";
 732                 };
 733
 734                 i2c1: i2c@10040000 {
 735                         compatible = "snps,designware-i2c";
 736                         reg = <0x0 0x10040000 0x0 0x10000>;
 737                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 738                                  <&clkgen JH7110_I2C1_CLK_APB>;
 739                         clock-names = "ref", "pclk";
 740                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 741                         interrupts = <36>;
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744                         status = "disabled";
 745                 };
 746
 747                 i2c2: i2c@10050000 {
 748                         compatible = "snps,designware-i2c";
 749                         reg = <0x0 0x10050000 0x0 0x10000>;
 750                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 751                                  <&clkgen JH7110_I2C2_CLK_APB>;
 752                         clock-names = "ref", "pclk";
 753                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 754                         interrupts = <37>;
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         status = "disabled";
 758                 };
 759
 760                 i2c3: i2c@12030000 {
 761                         compatible = "snps,designware-i2c";
 762                         reg = <0x0 0x12030000 0x0 0x10000>;
 763                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 764                                  <&clkgen JH7110_I2C3_CLK_APB>;
 765                         clock-names = "ref", "pclk";
 766                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 767                         interrupts = <48>;
 768                         #address-cells = <1>;
 769                         #size-cells = <0>;
 770                         status = "disabled";
 771                 };
 772
 773                 i2c4: i2c@12040000 {
 774                         compatible = "snps,designware-i2c";
 775                         reg = <0x0 0x12040000 0x0 0x10000>;
 776                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 777                                  <&clkgen JH7110_I2C4_CLK_APB>;
 778                         clock-names = "ref", "pclk";
 779                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 780                         interrupts = <49>;
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783                         status = "disabled";
 784                 };
 785
 786                 i2c5: i2c@12050000 {
 787                         compatible = "snps,designware-i2c";
 788                         reg = <0x0 0x12050000 0x0 0x10000>;
 789                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 790                                  <&clkgen JH7110_I2C5_CLK_APB>;
 791                         clock-names = "ref", "pclk";
 792                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 793                         interrupts = <50>;
 794                         #address-cells = <1>;
 795                         #size-cells = <0>;
 796                         status = "disabled";
 797                 };
 798
 799                 i2c6: i2c@12060000 {
 800                         compatible = "snps,designware-i2c";
 801                         reg = <0x0 0x12060000 0x0 0x10000>;
 802                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 803                                  <&clkgen JH7110_I2C6_CLK_APB>;
 804                         clock-names = "ref", "pclk";
 805                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 806                         interrupts = <51>;
 807                         #address-cells = <1>;
 808                         #size-cells = <0>;
 809                         status = "disabled";
 810                 };
 811
 812                 /* unremovable emmc as mmcblk0 */
 813                 sdio0: sdio0@16010000 {
 814                         compatible = "starfive,jh7110-sdio";
 815                         reg = <0x0 0x16010000 0x0 0x10000>;
 816                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 817                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 818                         clock-names = "biu","ciu";
 819                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 820                         reset-names = "reset";
 821                         interrupts = <74>;
 822                         fifo-depth = <32>;
 823                         fifo-watermark-aligned;
 824                         data-addr = <0>;
 825                         starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
 826                         status = "disabled";
 827                 };
 828
 829                 sdio1: sdio1@16020000 {
 830                         compatible = "starfive,jh7110-sdio";
 831                         reg = <0x0 0x16020000 0x0 0x10000>;
 832                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 833                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 834                         clock-names = "biu","ciu";
 835                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 836                         reset-names = "reset";
 837                         interrupts = <75>;
 838                         fifo-depth = <32>;
 839                         fifo-watermark-aligned;
 840                         data-addr = <0>;
 841                         status = "disabled";
 842                 };
 843
 844                 vin_sysctl: vin_sysctl@19800000 {
 845                         compatible = "starfive,jh7110-vin";
 846                         reg = <0x0 0x19800000 0x0 0x10000>,
 847                                 <0x0 0x19810000 0x0 0x10000>,
 848                                 <0x0 0x19820000 0x0 0x10000>,
 849                                 <0x0 0x19840000 0x0 0x10000>,
 850                                 <0x0 0x19870000 0x0 0x30000>,
 851                                 <0x0 0x11840000 0x0 0x10000>,
 852                                 <0x0 0x17030000 0x0 0x10000>,
 853                                 <0x0 0x13020000 0x0 0x10000>;
 854                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 855                                 "isp", "trst", "pmu", "syscrg";
 856                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 857                                  <&clkisp JH7110_U0_VIN_PCLK>,
 858                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 859                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 860                                  <&clkisp JH7110_DVP_INV>,
 861                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 862                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 863                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 864                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 865                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 866                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 867                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 868                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 869                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 870                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 871                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 872                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 873                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 874                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 875                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 876                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 877                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 878                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 879                                 "clk_ispcore_2x", "clk_isp_axi", "clk_noc_bus_clk_isp_axi";
 880                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 881                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 882                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 883                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 884                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 885                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 886                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 887                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 888                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 889                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 890                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 891                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 892                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 893                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 894                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 895                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 896                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 897                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 898                                 "rst_isp_top_n", "rst_isp_top_axi";
 899                         starfive,aon-syscon = <&aon_syscon 0x00>;
 900                         power-domains = <&pwrc JH7110_PD_ISP>;
 901                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 902                         interrupts = <92 87 88 89 90>;
 903                         status = "disabled";
 904                 };
 905
 906                 jpu: jpu@11900000 {
 907                         compatible = "starfive,jpu";
 908                         reg = <0x0 0x13090000 0x0 0x300>;
 909                         interrupts = <14>;
 910                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 911                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 912                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 913                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 914                         clock-names = "axi_clk", "core_clk",
 915                                       "apb_clk", "noc_bus";
 916                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 917                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 918                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 919                         reset-names = "rst_axi", "rst_core", "rst_apb";
 920                         power-domains = <&pwrc JH7110_PD_VDEC>;
 921                         status = "disabled";
 922                 };
 923
 924                 vpu_dec: vpu_dec@130A0000 {
 925                         compatible = "starfive,vdec";
 926                         reg = <0x0 0x130A0000 0x0 0x10000>;
 927                         interrupts = <13>;
 928                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 929                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 930                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 931                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 932                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 933                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 934                                       "apb_clk", "noc_bus";
 935                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 936                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 937                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 938                                 <&rstgen RSTN_U0_WAVE511_APB>,
 939                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 940                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 941                                       "rst_apb", "rst_sram";
 942                         starfive,vdec_noc_ctrl;
 943                         power-domains = <&pwrc JH7110_PD_VDEC>;
 944                         status = "disabled";
 945                 };
 946
 947                 vpu_enc: vpu_enc@130B0000 {
 948                         compatible = "starfive,venc";
 949                         reg = <0x0 0x130B0000 0x0 0x10000>;
 950                         interrupts = <15>;
 951                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 952                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 953                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 954                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 955                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 956                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 957                                       "apb_clk", "noc_bus";
 958                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 959                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 960                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 961                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 962                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 963                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 964                                       "rst_apb", "rst_sram";
 965                         starfive,venc_noc_ctrl;
 966                         power-domains = <&pwrc JH7110_PD_VENC>;
 967                         status = "disabled";
 968                 };
 969
 970                 rstgen: reset-controller {
 971                         compatible = "starfive,jh7110-reset";
 972                         reg = <0x0 0x13020000 0x0 0x10000>,
 973                                 <0x0 0x10230000 0x0 0x10000>,
 974                                 <0x0 0x17000000 0x0 0x10000>,
 975                                 <0x0 0x19810000 0x0 0x10000>,
 976                                 <0x0 0x295C0000 0x0 0x10000>;
 977                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 978                         #reset-cells = <1>;
 979                         status = "okay";
 980                 };
 981
 982                 stmmac_axi_setup: stmmac-axi-config {
 983                         snps,wr_osr_lmt = <0xf>;
 984                         snps,rd_osr_lmt = <0xf>;
 985                         snps,blen = <256 128 64 32 0 0 0>;
 986                 };
 987
 988                 gmac0: ethernet@16030000 {
 989                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
 990                         reg = <0x0 0x16030000 0x0 0x10000>;
 991                         clock-names = "gtx",
 992                                 "tx",
 993                                 "ptp_ref",
 994                                 "stmmaceth",
 995                                 "pclk",
 996                                 "gtxc";
 997                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 998                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 999                                  <&clkgen JH7110_GMAC0_PTP>,
1000                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
1001                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
1002                                  <&clkgen JH7110_GMAC0_GTXC>;
1003                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
1004                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
1005                         reset-names = "ahb", "stmmaceth";
1006                         interrupts = <7>, <6>, <5> ;
1007                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1008                         max-frame-size = <9000>;
1009                         phy-mode = "rgmii-id";
1010                         snps,multicast-filter-bins = <64>;
1011                         snps,perfect-filter-entries = <128>;
1012                         rx-fifo-depth = <2048>;
1013                         tx-fifo-depth = <2048>;
1014                         snps,fixed-burst;
1015                         snps,no-pbl-x8;
1016                         snps,force_thresh_dma_mode;
1017                         snps,axi-config = <&stmmac_axi_setup>;
1018                         snps,tso;
1019                         snps,en-tx-lpi-clockgating;
1020                         snps,en-lpi;
1021                         snps,write-requests = <4>;
1022                         snps,read-requests = <4>;
1023                         snps,burst-map = <0x7>;
1024                         snps,txpbl = <16>;
1025                         snps,rxpbl = <16>;
1026                         status = "disabled";
1027                 };
1028
1029                 gmac1: ethernet@16040000 {
1030                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
1031                         reg = <0x0 0x16040000 0x0 0x10000>;
1032                         clock-names = "gtx",
1033                                 "tx",
1034                                 "ptp_ref",
1035                                 "stmmaceth",
1036                                 "pclk",
1037                                 "gtxc";
1038                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1039                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1040                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1041                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1042                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1043                                  <&clkgen JH7110_GMAC1_GTXC>;
1044                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1045                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1046                         reset-names = "ahb", "stmmaceth";
1047                         interrupts = <78>, <77>, <76> ;
1048                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1049                         max-frame-size = <9000>;
1050                         phy-mode = "rgmii-id";
1051                         snps,multicast-filter-bins = <64>;
1052                         snps,perfect-filter-entries = <128>;
1053                         rx-fifo-depth = <2048>;
1054                         tx-fifo-depth = <2048>;
1055                         snps,fixed-burst;
1056                         snps,no-pbl-x8;
1057                         snps,force_thresh_dma_mode;
1058                         snps,axi-config = <&stmmac_axi_setup>;
1059                         snps,tso;
1060                         snps,en-tx-lpi-clockgating;
1061                         snps,en-lpi;
1062                         snps,write-requests = <4>;
1063                         snps,read-requests = <4>;
1064                         snps,burst-map = <0x7>;
1065                         snps,txpbl = <16>;
1066                         snps,rxpbl = <16>;
1067                         status = "disabled";
1068                 };
1069
1070                 gpu: gpu@18000000 {
1071                         compatible = "img-gpu";
1072                         reg = <0x0 0x18000000 0x0 0x100000>,
1073                                 <0x0 0x130C000 0x0 0x10000>;
1074                         clocks = <&clkgen JH7110_GPU_CORE>,
1075                                  <&clkgen JH7110_GPU_CLK_APB>,
1076                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1077                                  <&clkgen JH7110_GPU_CORE_CLK>,
1078                                  <&clkgen JH7110_GPU_SYS_CLK>,
1079                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1080                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1081                                         "clk_core", "clk_sys", "clk_axi";
1082                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1083                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1084                         reset-names = "rst_apb", "rst_doma";
1085                         power-domains = <&pwrc JH7110_PD_GPUA>;
1086                         interrupts = <82>;
1087                         current-clock = <8000000>;
1088                         status = "disabled";
1089                 };
1090
1091                 can0: can@130d0000 {
1092                         compatible = "starfive,jh7110-can", "ipms,can";
1093                         reg = <0x0 0x130d0000 0x0 0x1000>;
1094                         interrupts = <112>;
1095                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1096                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1097                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1098                         clock-names = "apb_clk", "core_clk", "timer_clk";
1099                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1100                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1101                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1102                         reset-names = "rst_apb", "rst_core", "rst_timer";
1103                         frequency = <40000000>;
1104                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1105                         syscon,can_or_canfd = <0>;
1106                         status = "disabled";
1107                 };
1108
1109                 can1: can@130e0000 {
1110                         compatible = "starfive,jh7110-can", "ipms,can";
1111                         reg = <0x0 0x130e0000 0x0 0x1000>;
1112                         interrupts = <113>;
1113                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1114                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1115                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1116                         clock-names = "apb_clk", "core_clk", "timer_clk";
1117                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1118                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1119                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1120                         reset-names = "rst_apb", "rst_core", "rst_timer";
1121                         frequency = <40000000>;
1122                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1123                         syscon,can_or_canfd = <1>;
1124                         status = "disabled";
1125                 };
1126
1127                 tdm: tdm@10090000 {
1128                         compatible = "starfive,jh7110-tdm";
1129                         reg = <0x0 0x10090000 0x0 0x1000>;
1130                         reg-names = "tdm";
1131                         clocks = <&clkgen JH7110_AHB0>,
1132                                  <&clkgen JH7110_TDM_CLK_AHB>,
1133                                  <&clkgen JH7110_APB0>,
1134                                  <&clkgen JH7110_TDM_CLK_APB>,
1135                                  <&clkgen JH7110_TDM_INTERNAL>,
1136                                  <&tdm_ext>,
1137                                  <&clkgen JH7110_TDM_CLK_TDM>,
1138                                  <&clkgen JH7110_MCLK_INNER>;
1139                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1140                                       "clk_apb0", "clk_tdm_apb",
1141                                       "clk_tdm_internal", "clk_tdm_ext",
1142                                       "clk_tdm", "mclk_inner";
1143                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1144                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1145                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1146                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1147                         dmas = <&dma 20 1>, <&dma 21 1>;
1148                         dma-names = "rx","tx";
1149                         #sound-dai-cells = <0>;
1150                         status = "disabled";
1151                 };
1152
1153                 spdif0: spdif0@100a0000 {
1154                         compatible = "starfive,jh7110-spdif";
1155                         reg = <0x0 0x100a0000 0x0 0x1000>;
1156                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1157                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1158                                  <&clkgen JH7110_AUDIO_ROOT>,
1159                                  <&clkgen JH7110_MCLK_INNER>,
1160                                  <&mclk_ext>, <&clkgen JH7110_MCLK>;
1161                         clock-names = "spdif-apb", "spdif-core",
1162                                       "audroot", "mclk_inner",
1163                                       "mclk_ext", "mclk";
1164                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1165                         reset-names = "rst_apb";
1166                         interrupts = <84>;
1167                         interrupt-names = "tx";
1168                         #sound-dai-cells = <0>;
1169                         status = "disabled";
1170                 };
1171
1172                 pwmdac: pwmdac@100b0000 {
1173                         compatible = "starfive,jh7110-pwmdac";
1174                         reg = <0x0 0x100b0000 0x0 0x1000>;
1175                         clocks = <&clkgen JH7110_APB0>,
1176                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1177                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1178                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1179                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1180                         reset-names = "rst-apb";
1181                         dmas = <&dma 22 1>;
1182                         dma-names = "tx";
1183                         #sound-dai-cells = <0>;
1184                         status = "disabled";
1185                 };
1186
1187                 i2stx: i2stx@100c0000 {
1188                         compatible = "snps,designware-i2stx";
1189                         reg = <0x0 0x100c0000 0x0 0x1000>;
1190                         interrupt-names = "tx";
1191                         #sound-dai-cells = <0>;
1192                         dmas = <&dma 28 1>;
1193                         dma-names = "rx";
1194                         status = "disabled";
1195                 };
1196
1197                 pdm: pdm@100d0000 {
1198                         compatible = "starfive,jh7110-pdm";
1199                         reg = <0x0 0x100d0000 0x0 0x1000>;
1200                         reg-names = "pdm";
1201                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1202                                  <&clkgen JH7110_APB0>,
1203                                  <&clkgen JH7110_PDM_CLK_APB>,
1204                                  <&clkgen JH7110_MCLK>,
1205                                  <&mclk_ext>;
1206                         clock-names = "pdm_mclk", "clk_apb0",
1207                                       "pdm_apb", "clk_mclk",
1208                                       "mclk_ext";
1209                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1210                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1211                         reset-names = "pdm_dmic", "pdm_apb";
1212                         #sound-dai-cells = <0>;
1213                 };
1214
1215                 i2srx_mst: i2srx_mst@100e0000 {
1216                         compatible = "starfive,jh7110-i2srx-master";
1217                         reg = <0x0 0x100e0000 0x0 0x1000>;
1218                         clocks = <&clkgen JH7110_APB0>,
1219                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1220                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1221                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1222                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1223                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1224                         clock-names = "apb0", "i2srx_apb",
1225                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1226                                       "i2srx_bclk", "i2srx_lrck";
1227                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1228                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1229                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1230                         dmas = <&dma 24 1>;
1231                         dma-names = "rx";
1232                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1233                         #sound-dai-cells = <0>;
1234                         status = "disabled";
1235                 };
1236
1237                 i2srx_3ch: i2srx_3ch@100e0000 {
1238                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1239                         reg = <0x0 0x100e0000 0x0 0x1000>;
1240                         clocks = <&clkgen JH7110_APB0>,
1241                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1242                                  <&clkgen JH7110_AUDIO_ROOT>,
1243                                  <&clkgen JH7110_MCLK_INNER>,
1244                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1245                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1246                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1247                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1248                                  <&clkgen JH7110_MCLK>,
1249                                  <&i2srx_bclk_ext>,
1250                                  <&i2srx_lrck_ext>;
1251                         clock-names = "apb0", "3ch-apb",
1252                                       "audioroot", "mclk-inner",
1253                                       "bclk_mst", "3ch-lrck",
1254                                       "rx-bclk", "rx-lrck",
1255                                       "mclk", "bclk-ext",
1256                                       "lrck-ext";
1257                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1258                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1259                         dmas = <&dma 24 1>;
1260                         dma-names = "rx";
1261                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1262                         #sound-dai-cells = <0>;
1263                         status = "disabled";
1264                 };
1265
1266                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1267                         compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1268                         reg = <0x0 0x120b0000 0x0 0x1000>;
1269                         clocks = <&clkgen JH7110_MCLK_INNER>,
1270                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1271                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1272                                  <&clkgen JH7110_MCLK>,
1273                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1274                                  <&clkgen JH7110_I2STX0_4CHLRCK>,
1275                                  <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1276                                  <&mclk_ext>;
1277                         clock-names = "inner", "bclk-mst",
1278                                         "lrck-mst", "mclk",
1279                                         "bclk0", "lrck0",
1280                                         "i2s_apb", "mclk_ext";
1281                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1282                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1283                         reset-names = "rst_apb", "rst_bclk";
1284                         dmas = <&dma 47 1>;
1285                         dma-names = "tx";
1286                         #sound-dai-cells = <0>;
1287                         status = "disabled";
1288                 };
1289
1290                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1291                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1292                         reg = <0x0 0x120c0000 0x0 0x1000>;
1293                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1294                                  <&clkgen JH7110_MCLK_INNER>,
1295                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1296                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1297                                  <&clkgen JH7110_MCLK>,
1298                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1299                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1300                                  <&clkgen JH7110_MCLK_OUT>,
1301                                  <&clkgen JH7110_APB0>,
1302                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1303                                  <&mclk_ext>,
1304                                  <&i2stx_bclk_ext>,
1305                                  <&i2stx_lrck_ext>;
1306                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1307                                       "lrck_mst", "mclk", "4chbclk",
1308                                       "4chlrck", "mclk_out",
1309                                       "apb0", "clk_apb",
1310                                       "mclk_ext", "bclk_ext", "lrck_ext";
1311                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1312                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1313                         dmas = <&dma 48 1>;
1314                         dma-names = "tx";
1315                         #sound-dai-cells = <0>;
1316                         status = "disabled";
1317                 };
1318
1319                 ptc: pwm@120d0000 {
1320                         compatible = "starfive,jh7110-pwm";
1321                         reg = <0x0 0x120d0000 0x0 0x10000>;
1322                         reg-names = "control";
1323                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1324                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1325                         starfive,approx-freq = <2000000>;
1326                         #pwm-cells=<3>;
1327                         starfive,npwm = <8>;
1328                         status = "disabled";
1329                 };
1330
1331                 spdif_transmitter: spdif_transmitter {
1332                         compatible = "linux,spdif-dit";
1333                         #sound-dai-cells = <0>;
1334                         status = "disabled";
1335                 };
1336
1337                 pwmdac_codec: pwmdac-transmitter {
1338                         compatible = "starfive,jh7110-pwmdac-dit";
1339                         #sound-dai-cells = <0>;
1340                         status = "disabled";
1341                 };
1342
1343                 dmic_codec: dmic_codec {
1344                         compatible = "dmic-codec";
1345                         #sound-dai-cells = <0>;
1346                         status = "disabled";
1347                 };
1348
1349                 spi0: spi@10060000 {
1350                         compatible = "arm,pl022", "arm,primecell";
1351                         reg = <0x0 0x10060000 0x0 0x10000>;
1352                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1353                         clock-names = "apb_pclk";
1354                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1355                         reset-names = "rst_apb";
1356                         interrupts = <38>;
1357                         /* shortage of dma channel that not be used */
1358                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1359                         /*dma-names = "rx","tx";*/
1360                         arm,primecell-periphid = <0x00041022>;
1361                         num-cs = <1>;
1362                         #address-cells = <1>;
1363                         #size-cells = <0>;
1364                         status = "disabled";
1365                 };
1366
1367                 spi1: spi@10070000 {
1368                         compatible = "arm,pl022", "arm,primecell";
1369                         reg = <0x0 0x10070000 0x0 0x10000>;
1370                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1371                         clock-names = "apb_pclk";
1372                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1373                         reset-names = "rst_apb";
1374                         interrupts = <39>;
1375                         /* shortage of dma channel that not be used */
1376                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1377                         /*dma-names = "rx","tx";*/
1378                         arm,primecell-periphid = <0x00041022>;
1379                         num-cs = <1>;
1380                         #address-cells = <1>;
1381                         #size-cells = <0>;
1382                         status = "disabled";
1383                 };
1384
1385                 spi2: spi@10080000 {
1386                         compatible = "arm,pl022", "arm,primecell";
1387                         reg = <0x0 0x10080000 0x0 0x10000>;
1388                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1389                         clock-names = "apb_pclk";
1390                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1391                         reset-names = "rst_apb";
1392                         interrupts = <40>;
1393                         /* shortage of dma channel that not be used */
1394                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1395                         /*dma-names = "rx","tx";*/
1396                         arm,primecell-periphid = <0x00041022>;
1397                         num-cs = <1>;
1398                         #address-cells = <1>;
1399                         #size-cells = <0>;
1400                         status = "disabled";
1401                 };
1402
1403                 spi3: spi@12070000 {
1404                         compatible = "arm,pl022", "arm,primecell";
1405                         reg = <0x0 0x12070000 0x0 0x10000>;
1406                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1407                         clock-names = "apb_pclk";
1408                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1409                         reset-names = "rst_apb";
1410                         interrupts = <52>;
1411                         /* shortage of dma channel that not be used */
1412                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1413                         /*dma-names = "rx","tx";*/
1414                         arm,primecell-periphid = <0x00041022>;
1415                         num-cs = <1>;
1416                         #address-cells = <1>;
1417                         #size-cells = <0>;
1418                         status = "disabled";
1419                 };
1420
1421                 spi4: spi@12080000 {
1422                         compatible = "arm,pl022", "arm,primecell";
1423                         reg = <0x0 0x12080000 0x0 0x10000>;
1424                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1425                         clock-names = "apb_pclk";
1426                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1427                         reset-names = "rst_apb";
1428                         interrupts = <53>;
1429                         /* shortage of dma channel that not be used */
1430                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1431                         /*dma-names = "rx","tx";*/
1432                         arm,primecell-periphid = <0x00041022>;
1433                         num-cs = <1>;
1434                         #address-cells = <1>;
1435                         #size-cells = <0>;
1436                         status = "disabled";
1437                 };
1438
1439                 spi5: spi@12090000 {
1440                         compatible = "arm,pl022", "arm,primecell";
1441                         reg = <0x0 0x12090000 0x0 0x10000>;
1442                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1443                         clock-names = "apb_pclk";
1444                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1445                         reset-names = "rst_apb";
1446                         interrupts = <54>;
1447                         /* shortage of dma channel that not be used */
1448                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1449                         /*dma-names = "rx","tx";*/
1450                         arm,primecell-periphid = <0x00041022>;
1451                         num-cs = <1>;
1452                         #address-cells = <1>;
1453                         #size-cells = <0>;
1454                         status = "disabled";
1455                 };
1456
1457                 spi6: spi@120A0000 {
1458                         compatible = "arm,pl022", "arm,primecell";
1459                         reg = <0x0 0x120A0000 0x0 0x10000>;
1460                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1461                         clock-names = "apb_pclk";
1462                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1463                         reset-names = "rst_apb";
1464                         interrupts = <55>;
1465                         /* shortage of dma channel that not be used */
1466                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1467                         /*dma-names = "rx","tx";*/
1468                         arm,primecell-periphid = <0x00041022>;
1469                         num-cs = <1>;
1470                         #address-cells = <1>;
1471                         #size-cells = <0>;
1472                         status = "disabled";
1473                 };
1474
1475                 pcie0: pcie@2B000000 {
1476                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1477                         #address-cells = <3>;
1478                         #size-cells = <2>;
1479                         #interrupt-cells = <1>;
1480                         reg = <0x0 0x2B000000 0x0 0x1000000
1481                                0x9 0x40000000 0x0 0x10000000>;
1482                         reg-names = "reg", "config";
1483                         device_type = "pci";
1484                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1485                         bus-range = <0x0 0xff>;
1486                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1487                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1488                         msi-parent = <&plic>;
1489                         interrupts = <56>;
1490                         interrupt-controller;
1491                         interrupt-names = "msi";
1492                         interrupt-parent = <&plic>;
1493                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1494                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1495                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1496                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1497                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1498                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1499                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1500                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1501                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1502                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1503                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1504                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1505                                       "rst_brg", "rst_core", "rst_apb";
1506                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1507                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1508                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1509                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1510                         clock-names = "noc", "tl", "axi_mst0", "apb";
1511                         status = "disabled";
1512                 };
1513
1514                 pcie1: pcie@2C000000 {
1515                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1516                         #address-cells = <3>;
1517                         #size-cells = <2>;
1518                         #interrupt-cells = <1>;
1519                         reg = <0x0 0x2C000000 0x0 0x1000000
1520                                0x9 0xc0000000 0x0 0x10000000>;
1521                         reg-names = "reg", "config";
1522                         device_type = "pci";
1523                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1524                         bus-range = <0x0 0xff>;
1525                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1526                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1527                         msi-parent = <&plic>;
1528                         interrupts = <57>;
1529                         interrupt-controller;
1530                         interrupt-names = "msi";
1531                         interrupt-parent = <&plic>;
1532                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1533                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1534                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1535                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1536                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1537                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1538                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1539                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1540                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1541                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1542                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1543                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1544                                       "rst_brg", "rst_core", "rst_apb";
1545                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1546                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1547                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1548                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1549                         clock-names = "noc", "tl", "axi_mst0", "apb";
1550                         status = "disabled";
1551                 };
1552
1553                 mailbox_contrl0: mailbox@0 {
1554                         compatible = "starfive,mail_box";
1555                         reg = <0x0 0x13060000 0x0 0x0001000>;
1556                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1557                         clock-names = "clk_apb";
1558                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1559                         reset-names = "mbx_rre";
1560                         interrupts = <26 27>;
1561                         #mbox-cells = <2>;
1562                         status = "disabled";
1563                 };
1564
1565                 mailbox_client0: mailbox_client@0 {
1566                         compatible = "starfive,mailbox-test";
1567                         mbox-names = "rx", "tx";
1568                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1569                         status = "disabled";
1570                 };
1571
1572                 display: display-subsystem {
1573                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1574                         ports = <&dc_out_dpi0>;
1575                         status = "disabled";
1576                 };
1577
1578                 dssctrl: dssctrl@295B0000 {
1579                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1580                         reg = <0 0x295B0000 0 0x90>;
1581                 };
1582
1583                 tda988x_pin: tda988x_pin {
1584                         compatible = "starfive,tda998x_rgb_pin";
1585                         status = "disabled";
1586                 };
1587
1588                 rgb_output: rgb-output {
1589                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1590                         //verisilicon,dss-syscon = <&dssctrl>;
1591                         //verisilicon,mux-mask = <0x70 0x380>;
1592                         //verisilicon,mux-val = <0x40 0x280>;
1593                         status = "disabled";
1594                 };
1595
1596                 dc8200: dc8200@29400000 {
1597                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1598                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1599                         reg = <0x0 0x29400000 0x0 0x100>,
1600                               <0x0 0x29400800 0x0 0x2000>,
1601                               <0x0 0x17030000 0x0 0x1000>;
1602                         interrupts = <95>;
1603                         status = "disabled";
1604                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1605                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1606                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1607                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1608                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1609                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1610                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1611                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1612                                  <&clkgen JH7110_VOUT_SRC>,
1613                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1614                                  <&clkgen JH7110_AHB1>,
1615                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1616                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1617                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1618                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1619                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1620                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1621                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1622                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1623                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1624                                  <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1625                                  <&hdmitx0_pixelclk>,
1626                                  <&clkvout JH7110_DC8200_PIX0>,
1627                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1628                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1629                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1630                                         "noc_disp","noc_isp","noc_stg","vout_src",
1631                                         "top_vout_axi","ahb1","top_vout_ahb",
1632                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1633                                         "axi_clk","core_clk","vout_ahb",
1634                                         "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1635                                         "dc8200_pix0_out","dc8200_pix1_out";
1636                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1637                                  <&rstgen RSTN_U0_DC8200_AXI>,
1638                                  <&rstgen RSTN_U0_DC8200_AHB>,
1639                                  <&rstgen RSTN_U0_DC8200_CORE>,
1640                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1641                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1642                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1643                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1644                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
1645                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1646                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1647                                         "rst_noc_disp","rst_noc_stg";
1648                         power-domains = <&pwrc JH7110_PD_VOUT>;
1649                 };
1650
1651                 dsi_output: dsi-output {
1652                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1653                         status = "disabled";
1654                 };
1655
1656                 mipi_dphy: mipi-dphy@295e0000{
1657                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1658                         reg = <0x0 0x295e0000 0x0 0x10000>;
1659                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1660                         clock-names = "dphy_txesc";
1661                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1662                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1663                         reset-names = "dphy_sys", "dphy_txbytehs";
1664                         #phy-cells = <0>;
1665                         status = "disabled";
1666                 };
1667
1668                  mipi_dsi: mipi@295d0000 {
1669                         compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1670                         reg = <0x0 0x295d0000 0x0 0x10000>;
1671                         interrupts = <98>;
1672                         reg-names = "dsi";
1673                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1674                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1675                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1676                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1677                         clock-names = "sys", "apb", "txesc", "dpi";
1678                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1679                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1680                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1681                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1682                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1683                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1684                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1685                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1686                         phys = <&mipi_dphy>;
1687                         phy-names = "dphy";
1688                         status = "disabled";
1689
1690                         port {
1691                                 dsi_out_port: endpoint@0 {
1692                                         remote-endpoint = <&panel_dsi_port>;
1693                                 };
1694                                 dsi_in_port: endpoint@1 {
1695                                         remote-endpoint = <&mipi_out>;
1696                                 };
1697                         };
1698
1699                         mipi_panel: panel@0 {
1700                                 /*compatible = "";*/
1701                                 status = "okay";
1702                         };
1703                 };
1704
1705                 hdmi: hdmi@29590000 {
1706                         compatible = "starfive,jh7110-hdmi","inno,hdmi";
1707                         reg = <0x0 0x29590000 0x0 0x4000>;
1708                         interrupts = <99>;
1709                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1710                         /*clocks = <&cru  PCLK_HDMI>;*/
1711                         /*clock-names = "pclk";*/
1712                         /*pinctrl-names = "default";*/
1713                         /*pinctrl-0 = <&hdmi_ctl>;*/
1714                         status = "disabled";
1715                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1716                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1717                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1718                                  <&hdmitx0_pixelclk>;
1719                         clock-names = "sysclk", "mclk", "bclk", "pclk";
1720                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1721                         reset-names = "hdmi_tx";
1722                         #sound-dai-cells = <0>;
1723                 };
1724
1725                 sound: snd-card {
1726                         compatible = "simple-audio-card";
1727                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1728                         #address-cells = <1>;
1729                         #size-cells = <0>;
1730                 };
1731
1732                 co_process: e24@0 {
1733                         compatible = "starfive,e24";
1734                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1735                                 <0x0 0xc0111000 0x0 0x0001f000>;
1736                         reg-names = "ecmd", "espace";
1737                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1738                                  <&clkgen JH7110_E2_CLK_CORE>,
1739                                  <&clkgen JH7110_E2_CLK_DBG>;
1740                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1741                         resets = <&rstgen RSTN_U0_E24_CORE>;
1742                         reset-names = "e24_core";
1743                         starfive,stg-syscon = <&stg_syscon>;
1744                         interrupt-parent = <&plic>;
1745                         firmware-name = "e24_elf";
1746                         irq-mode = <1>;
1747                         mbox-names = "tx", "rx";
1748                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1749                         #address-cells = <1>;
1750                         #size-cells = <1>;
1751                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1752                         status = "disabled";
1753                         dsp@0 {};
1754                 };
1755
1756                 xrp: xrp@0 {
1757                         compatible = "cdns,xrp";
1758                         reg = <0x0  0x10230000 0x0 0x00010000
1759                                 0x0  0x10240000 0x0 0x00010000>;
1760                         memory-region = <&xrp_reserved>;
1761                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1762                         clock-names = "core_clk";
1763                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1764                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1765                         reset-names = "rst_core","rst_axi";
1766                         starfive,stg-syscon = <&stg_syscon>;
1767                         firmware-name = "hifi4_elf";
1768                         #address-cells = <1>;
1769                         #size-cells = <1>;
1770                         ranges = <0x40000000 0x0 0x20000000 0x040000
1771                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1772                         status = "disabled";
1773                         dsp@0 {
1774                         };
1775                 };
1776
1777                 starfive_cpufreq: starfive,jh7110-cpufreq {
1778                         compatible = "starfive,jh7110-cpufreq";
1779                         clocks = <&clkgen JH7110_PLL0_OUT>,
1780                                          <&clkgen JH7110_CPU_ROOT>,
1781                                          <&osc>;
1782                         clock-names = "pll0", "cpu_clk", "osc";
1783                 };
1784         };
1785 };