arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110_clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13
  14 / {
  15         compatible = "starfive,jh7110";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: cpu@0 {
  24                         compatible = "sifive,u74-mc", "riscv";
  25                         reg = <0>;
  26                         d-cache-block-size = <64>;
  27                         d-cache-sets = <64>;
  28                         d-cache-size = <8192>;
  29                         d-tlb-sets = <1>;
  30                         d-tlb-size = <40>;
  31                         device_type = "cpu";
  32                         i-cache-block-size = <64>;
  33                         i-cache-sets = <64>;
  34                         i-cache-size = <16384>;
  35                         i-tlb-sets = <1>;
  36                         i-tlb-size = <40>;
  37                         mmu-type = "riscv,sv39";
  38                         next-level-cache = <&cachectrl>;
  39                         riscv,isa = "rv64imac";
  40                         tlb-split;
  41                         status = "disabled";
  42
  43                         cpu0intctrl: interrupt-controller {
  44                                 #interrupt-cells = <1>;
  45                                 compatible = "riscv,cpu-intc";
  46                                 interrupt-controller;
  47                         };
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         compatible = "sifive,u74-mc", "riscv";
  52                         reg = <1>;
  53                         d-cache-block-size = <64>;
  54                         d-cache-sets = <64>;
  55                         d-cache-size = <32768>;
  56                         d-tlb-sets = <1>;
  57                         d-tlb-size = <40>;
  58                         device_type = "cpu";
  59                         i-cache-block-size = <64>;
  60                         i-cache-sets = <64>;
  61                         i-cache-size = <32768>;
  62                         i-tlb-sets = <1>;
  63                         i-tlb-size = <40>;
  64                         mmu-type = "riscv,sv39";
  65                         next-level-cache = <&cachectrl>;
  66                         riscv,isa = "rv64imafdc";
  67                         tlb-split;
  68                         status = "okay";
  69
  70                         cpu1intctrl: interrupt-controller {
  71                                 #interrupt-cells = <1>;
  72                                 compatible = "riscv,cpu-intc";
  73                                 interrupt-controller;
  74                         };
  75                 };
  76
  77                 cpu2: cpu@2 {
  78                         compatible = "sifive,u74-mc", "riscv";
  79                         reg = <2>;
  80                         d-cache-block-size = <64>;
  81                         d-cache-sets = <64>;
  82                         d-cache-size = <32768>;
  83                         d-tlb-sets = <1>;
  84                         d-tlb-size = <40>;
  85                         device_type = "cpu";
  86                         i-cache-block-size = <64>;
  87                         i-cache-sets = <64>;
  88                         i-cache-size = <32768>;
  89                         i-tlb-sets = <1>;
  90                         i-tlb-size = <40>;
  91                         mmu-type = "riscv,sv39";
  92                         next-level-cache = <&cachectrl>;
  93                         riscv,isa = "rv64imafdc";
  94                         tlb-split;
  95                         status = "okay";
  96
  97                         cpu2intctrl: interrupt-controller {
  98                                 #interrupt-cells = <1>;
  99                                 compatible = "riscv,cpu-intc";
 100                                 interrupt-controller;
 101                         };
 102                 };
 103
 104                 cpu3: cpu@3 {
 105                         compatible = "sifive,u74-mc", "riscv";
 106                         reg = <3>;
 107                         d-cache-block-size = <64>;
 108                         d-cache-sets = <64>;
 109                         d-cache-size = <32768>;
 110                         d-tlb-sets = <1>;
 111                         d-tlb-size = <40>;
 112                         device_type = "cpu";
 113                         i-cache-block-size = <64>;
 114                         i-cache-sets = <64>;
 115                         i-cache-size = <32768>;
 116                         i-tlb-sets = <1>;
 117                         i-tlb-size = <40>;
 118                         mmu-type = "riscv,sv39";
 119                         next-level-cache = <&cachectrl>;
 120                         riscv,isa = "rv64imafdc";
 121                         tlb-split;
 122                         status = "okay";
 123
 124                         cpu3intctrl: interrupt-controller {
 125                                 #interrupt-cells = <1>;
 126                                 compatible = "riscv,cpu-intc";
 127                                 interrupt-controller;
 128                         };
 129                 };
 130
 131                 cpu4: cpu@4 {
 132                         compatible = "sifive,u74-mc", "riscv";
 133                         reg = <4>;
 134                         d-cache-block-size = <64>;
 135                         d-cache-sets = <64>;
 136                         d-cache-size = <32768>;
 137                         d-tlb-sets = <1>;
 138                         d-tlb-size = <40>;
 139                         device_type = "cpu";
 140                         i-cache-block-size = <64>;
 141                         i-cache-sets = <64>;
 142                         i-cache-size = <32768>;
 143                         i-tlb-sets = <1>;
 144                         i-tlb-size = <40>;
 145                         mmu-type = "riscv,sv39";
 146                         next-level-cache = <&cachectrl>;
 147                         riscv,isa = "rv64imafdc";
 148                         tlb-split;
 149                         status = "okay";
 150
 151                         cpu4intctrl: interrupt-controller {
 152                                 #interrupt-cells = <1>;
 153                                 compatible = "riscv,cpu-intc";
 154                                 interrupt-controller;
 155                         };
 156                 };
 157         };
 158
 159         soc: soc {
 160                 compatible = "simple-bus";
 161                 interrupt-parent = <&plic>;
 162                 #address-cells = <2>;
 163                 #size-cells = <2>;
 164                 #clock-cells = <1>;
 165                 ranges;
 166
 167                 cachectrl: cache-controller@2010000 {
 168                         compatible = "sifive,fu740-c000-ccache", "cache";
 169                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 170                         reg-names = "control", "sideband";
 171                         interrupts = <1 3 4 2>;
 172                         cache-block-size = <64>;
 173                         cache-level = <2>;
 174                         cache-sets = <2048>;
 175                         cache-size = <2097152>;
 176                         cache-unified;
 177                 };
 178
 179                 aon_syscon: aon_syscon@17010000 {
 180                         compatible = "syscon";
 181                         reg = <0x0 0x17010000 0x0 0x1000>;
 182                 };
 183
 184                 stg_syscon: stg_syscon@10240000 {
 185                         compatible = "syscon";
 186                         reg = <0x0 0x10240000 0x0 0x1000>;
 187                 };
 188
 189                 sys_syscon: sys_syscon@13030000 {
 190                         compatible = "syscon";
 191                         reg = <0x0 0x13030000 0x0 0x1000>;
 192                 };
 193
 194                 clint: clint@2000000 {
 195                         compatible = "riscv,clint0";
 196                         reg = <0x0 0x2000000 0x0 0x10000>;
 197                         reg-names = "control";
 198                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 199                                                 &cpu1intctrl 3 &cpu1intctrl 7
 200                                                 &cpu2intctrl 3 &cpu2intctrl 7
 201                                                 &cpu3intctrl 3 &cpu3intctrl 7
 202                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 203                         #interrupt-cells = <1>;
 204                 };
 205
 206                 plic: plic@c000000 {
 207                         compatible = "riscv,plic0";
 208                         reg = <0x0 0xc000000 0x0 0x4000000>;
 209                         reg-names = "control";
 210                         interrupts-extended = <&cpu0intctrl 11
 211                                                 &cpu1intctrl 11 &cpu1intctrl 9
 212                                                 &cpu2intctrl 11 &cpu2intctrl 9
 213                                                 &cpu3intctrl 11 &cpu3intctrl 9
 214                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <1>;
 217                         riscv,max-priority = <7>;
 218                         riscv,ndev = <136>;
 219                 };
 220
 221                 clkgen: clock-controller {
 222                         compatible = "starfive,jh7110-clkgen";
 223                         reg = <0x0 0x13020000 0x0 0x10000>,
 224                                 <0x0 0x10230000 0x0 0x10000>,
 225                                 <0x0 0x17000000 0x0 0x10000>;
 226                         reg-names = "sys", "stg", "aon";
 227                         clocks = <&osc>, <&gmac1_rmii_refin>,
 228                                 <&gmac1_rgmii_rxin>,
 229                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 230                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 231                                 <&tdm_ext>, <&mclk_ext>,
 232                                 <&jtag_tck_inner>, <&bist_apb>,
 233                                 <&stg_apb>, <&clk_rtc>,
 234                                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 235                         clock-names = "osc", "gmac1_rmii_refin",
 236                                 "gmac1_rgmii_rxin",
 237                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 238                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 239                                 "tdm_ext", "mclk_ext",
 240                                 "jtag_tck_inner", "bist_apb",
 241                                 "stg_apb", "clk_rtc",
 242                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 243                         #clock-cells = <1>;
 244                         status = "okay";
 245                 };
 246
 247                 clkvout: clock-controller@295C0000 {
 248                         compatible = "starfive,jh7110-clk-vout";
 249                         reg = <0x0 0x295C0000 0x0 0x10000>;
 250                         reg-names = "vout";
 251                         clocks = <&hdmitx0_pixelclk>,
 252                                 <&mipitx_dphy_rxesc>,
 253                                 <&mipitx_dphy_txbytehs>;
 254                         clock-names = "hdmitx0_pixelclk",
 255                                 "mipitx_dphy_rxesc",
 256                                 "mipitx_dphy_txbytehs";
 257                         #clock-cells = <1>;
 258                         status = "disabled";
 259                 };
 260
 261                 clkisp: clock-controller@19810000 {
 262                         compatible = "starfive,jh7110-clk-isp";
 263                         reg = <0x0 0x19810000 0x0 0x10000>;
 264                         reg-names = "isp";
 265                         #clock-cells = <1>;
 266                         status = "disabled";
 267                 };
 268
 269                 qspi: qspi@13010000 {
 270                         compatible = "cadence,qspi","cdns,qspi-nor";
 271                         #address-cells = <1>;
 272                         #size-cells = <0>;
 273                         reg = <0x0 0x13010000 0x0 0x10000
 274                                 0x0 0x21000000 0x0 0x400000>;
 275                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 276                         clock-names = "clk_ref";
 277                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 278                                         <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 279                                         <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 280                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 281                         cdns,fifo-depth = <256>;
 282                         cdns,fifo-width = <4>;
 283                         spi-max-frequency = <250000000>;
 284
 285                         nor_flash: nor-flash@0 {
 286                                 compatible = "jedec,spi-nor";
 287                                 reg=<0>;
 288                                 spi-max-frequency = <100000000>;
 289                                 cdns,tshsl-ns = <1>;
 290                                 cdns,tsd2d-ns = <1>;
 291                                 cdns,tchsh-ns = <1>;
 292                                 cdns,tslch-ns = <1>;
 293                         };
 294                 };
 295
 296                 otp: otp@17050000 {
 297                         compatible = "starfive,jh7110-otp";
 298                         reg = <0x0 0x17050000 0x0 0x10000>;
 299                         clock-frequency = <4000000>;
 300                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 301                         clock-names = "apb";
 302                 };
 303
 304                 USB30: usb@10100000 {
 305                         compatible = "cdns,usb3";
 306                         reg = <0x0 0x10100000 0x0 0x10000>,
 307                                 <0x0 0x10110000 0x0 0x10000>,
 308                                 <0x0 0x10120000 0x0 0x10000>;
 309                         reg-names = "otg", "xhci", "dev";
 310                         phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 311                         clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
 312                                 <&clkgen JH7110_USB0_CLK_LPM>,
 313                                 <&clkgen JH7110_USB0_CLK_STB>,
 314                                 <&clkgen JH7110_USB0_CLK_USB_APB>,
 315                                 <&clkgen JH7110_USB0_CLK_AXI>,
 316                                 <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 317                         clock-names = "app","lpm","stb","apb","axi","utmi";
 318                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 319                                         <&rstgen RSTN_U0_CDN_USB_APB>,
 320                                         <&rstgen RSTN_U0_CDN_USB_AXI>,
 321                                         <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 322                         reset-names = "rst_pwrup","rst_apb","rst_axi","rst_utmi";
 323                 };
 324
 325                 timer: timer@13050000 {
 326                         compatible = "starfive,si5-timers";
 327                         reg = <0x0 0x13050000 0x0 0x10000>;
 328                         interrupts = <69>, <70>, <71> ,<72>;
 329                         interrupt-names = "timer0", "timer1",
 330                                           "timer2", "timer3";
 331                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 332                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 333                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 334                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 335                                  <&clkgen JH7110_TIMER_CLK_APB>;
 336                         clock-names = "timer0", "timer1",
 337                                       "timer2", "timer3", "apb_clk";
 338                         clock-frequency = <2000000>;
 339                         status = "okay";
 340                 };
 341
 342                 wdog: wdog@13070000 {
 343                         compatible = "starfive,dskit-wdt";
 344                         reg = <0x0 0x13070000 0x0 0x10000>;
 345                         interrupts = <68>;
 346                         interrupt-names = "wdog";
 347                         clock-frequency = <2000000>;
 348                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 349                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 350                         clock-names = "core_clk", "apb_clk";
 351                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 352                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 353                         reset-names = "rst_apb", "rst_core";
 354                         timeout-sec = <15>;
 355                         status = "okay";
 356                 };
 357
 358                 rtc: rtc@17040000 {
 359                         compatible = "starfive,rtc_hms";
 360                         reg = <0x0 0x17040000 0x0 0x10000>;
 361                         interrupts = <10>, <11>, <12>;
 362                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 363                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 364                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 365                         clock-names = "pclk", "cal_clk";
 366                         resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
 367                                  <&rstgen RSTN_U0_RTC_HMS_CAL>,
 368                                  <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
 369                         reset-names = "rst_apb", "rst_cal", "rst_osc";
 370                         rtc,cal-clock-freq = <1000000>;
 371                         status = "okay";
 372                 };
 373
 374                 pmu: pmu@17030000 {
 375                         compatible = "starfive,jh7110-pmu";
 376                         reg = <0x0 0x17030000 0x0 0x10000>;
 377                         interrupts = <111>;
 378                         status = "okay";
 379                 };
 380
 381                 uart0: serial@10000000 {
 382                         compatible = "snps,dw-apb-uart";
 383                         reg = <0x0 0x10000000 0x0 0x10000>;
 384                         reg-io-width = <4>;
 385                         reg-shift = <2>;
 386                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 387                                         <&clkgen JH7110_UART0_CLK_APB>;
 388                         clock-names = "baudclk", "apb_pclk";
 389                         resets = <&rstgen RSTN_U0_DW_UART_APB>;
 390                         interrupts = <32>;
 391                         status = "disabled";
 392                 };
 393
 394                 uart1: serial@10010000 {
 395                         compatible = "snps,dw-apb-uart";
 396                         reg = <0x0 0x10010000 0x0 0x10000>;
 397                         reg-io-width = <4>;
 398                         reg-shift = <2>;
 399                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 400                                         <&clkgen JH7110_UART1_CLK_APB>;
 401                         clock-names = "baudclk", "apb_pclk";
 402                         resets = <&rstgen RSTN_U1_DW_UART_APB>;
 403                         interrupts = <33>;
 404                         status = "disabled";
 405                 };
 406
 407                 uart2: serial@10020000 {
 408                         compatible = "snps,dw-apb-uart";
 409                         reg = <0x0 0x10020000 0x0 0x10000>;
 410                         reg-io-width = <4>;
 411                         reg-shift = <2>;
 412                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 413                                         <&clkgen JH7110_UART2_CLK_APB>;
 414                         clock-names = "baudclk", "apb_pclk";
 415                         resets = <&rstgen RSTN_U2_DW_UART_APB>;
 416                         interrupts = <34>;
 417                         status = "disabled";
 418                 };
 419
 420                 uart3: serial@12000000 {
 421                         compatible = "snps,dw-apb-uart";
 422                         reg = <0x0 0x12000000 0x0 0x10000>;
 423                         reg-io-width = <4>;
 424                         reg-shift = <2>;
 425                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 426                                         <&clkgen JH7110_UART3_CLK_APB>;
 427                         clock-names = "baudclk", "apb_pclk";
 428                         resets = <&rstgen RSTN_U3_DW_UART_APB>;
 429                         interrupts = <45>;
 430                         status = "disabled";
 431                 };
 432
 433                 uart4: serial@12010000 {
 434                         compatible = "snps,dw-apb-uart";
 435                         reg = <0x0 0x12010000 0x0 0x10000>;
 436                         reg-io-width = <4>;
 437                         reg-shift = <2>;
 438                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 439                                         <&clkgen JH7110_UART4_CLK_APB>;
 440                         clock-names = "baudclk", "apb_pclk";
 441                         resets = <&rstgen RSTN_U4_DW_UART_APB>;
 442                         interrupts = <46>;
 443                         status = "disabled";
 444                 };
 445
 446                 uart5: serial@12020000 {
 447                         compatible = "snps,dw-apb-uart";
 448                         reg = <0x0 0x12020000 0x0 0x10000>;
 449                         reg-io-width = <4>;
 450                         reg-shift = <2>;
 451                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 452                                         <&clkgen JH7110_UART5_CLK_APB>;
 453                         clock-names = "baudclk", "apb_pclk";
 454                         resets = <&rstgen RSTN_U5_DW_UART_APB>;
 455                         interrupts = <47>;
 456                         status = "disabled";
 457                 };
 458
 459                 dma: dma-controller@16050000 {
 460                         compatible = "starfive,axi-dma";
 461                         reg = <0x0 0x16050000 0x0 0x10000>;
 462                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 463                                 <&clkgen JH7110_DMA1P_CLK_AHB>;
 464                         clock-names = "core-clk", "cfgr-clk";
 465                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 466                                 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 467                         reset-names = "rst_axi",
 468                                 "rst_ahb";
 469                         interrupts = <73>;
 470                         #dma-cells = <2>;
 471                         dma-channels = <4>;
 472                         snps,dma-masters = <1>;
 473                         snps,data-width = <3>;
 474                         snps,num-hs-if = <56>;
 475                         snps,block-size = <65536 65536 65536 65536>;
 476                         snps,priority = <0 1 2 3>;
 477                         snps,axi-max-burst-len = <16>;
 478                         status = "disabled";
 479                 };
 480
 481                 gpio: gpio@13040000 {
 482                         compatible = "starfive_jh7110-sys-pinctrl";
 483                         reg = <0x0 0x13040000 0x0 0x10000>;
 484                         reg-names = "control";
 485                         interrupts = <91>;
 486                         interrupt-controller;
 487                         #gpio-cells = <2>;
 488                         ngpios = <64>;
 489                         status = "okay";
 490                 };
 491
 492                 gpioa: gpio@17020000 {
 493                         compatible = "starfive_jh7110-aon-pinctrl";
 494                         reg = <0x0 0x17020000 0x0 0x10000>;
 495                         reg-names = "control";
 496                         interrupts = <90>;
 497                         interrupt-controller;
 498                         #gpio-cells = <2>;
 499                         ngpios = <4>;
 500                         status = "okay";
 501                 };
 502
 503                 trng: trng@1600C000 {
 504                         compatible = "starfive,trng";
 505                         reg = <0x0 0x1600C000 0x0 0x4000>;
 506                         clocks = <&clkgen JH7110_SEC_HCLK>,
 507                                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
 508                         clock-names = "hclk", "miscahb_clk";
 509                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 510                         interrupts = <30>;
 511                         status = "disabled";
 512                 };
 513
 514                 i2c6: i2c@12060000 {
 515                         compatible = "snps,designware-i2c";
 516                         reg = <0x0 0x12060000 0x0 0x10000>;
 517                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 518                                  <&clkgen JH7110_I2C6_CLK_APB>;
 519                         clock-names = "ref", "pclk";
 520                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 521                         interrupts = <51>;
 522                         #address-cells = <1>;
 523                         #size-cells = <0>;
 524                         status = "disabled";
 525                 };
 526
 527                 i2c0: i2c@10030000 {
 528                         compatible = "snps,designware-i2c";
 529                         reg = <0x0 0x10030000 0x0 0x10000>;
 530                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 531                                  <&clkgen JH7110_I2C0_CLK_APB>;
 532                         clock-names = "ref", "pclk";
 533                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 534                         interrupts = <35>;
 535                         #address-cells = <1>;
 536                         #size-cells = <0>;
 537                         status = "disabled";
 538                 };
 539
 540                 i2c1: i2c@10040000 {
 541                         compatible = "snps,designware-i2c";
 542                         reg = <0x0 0x10040000 0x0 0x10000>;
 543                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 544                                  <&clkgen JH7110_I2C1_CLK_APB>;
 545                         clock-names = "ref", "pclk";
 546                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 547                         interrupts = <36>;
 548                         #address-cells = <1>;
 549                         #size-cells = <0>;
 550                         status = "disabled";
 551                 };
 552
 553                 /* unremovable emmc as mmcblk0 */
 554                 sdio0: sdio0@16010000 {
 555                         compatible = "snps,dw-mshc";
 556                         reg = <0x0 0x16010000 0x0 0x10000>;
 557                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 558                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 559                         clock-names = "biu","ciu";
 560                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 561                         reset-names = "reset";
 562                         interrupts = <74>;
 563                         fifo-depth = <32>;
 564                         fifo-watermark-aligned;
 565                         data-addr = <0>;
 566                         status = "disabled";
 567                 };
 568
 569                 sdio1: sdio1@16020000 {
 570                         compatible = "snps,dw-mshc";
 571                         reg = <0x0 0x16020000 0x0 0x10000>;
 572                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 573                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 574                         clock-names = "biu","ciu";
 575                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 576                         reset-names = "reset";
 577                         interrupts = <75>;
 578                         fifo-depth = <32>;
 579                         fifo-watermark-aligned;
 580                         data-addr = <0>;
 581                         status = "disabled";
 582                 };
 583
 584                 vin_sysctl: vin_sysctl@19800000 {
 585                         compatible = "starfive,stf-vin";
 586                         reg = <0x0 0x19800000 0x0 0x10000>,
 587                                 <0x0 0x19810000 0x0 0x10000>,
 588                                 <0x0 0x19820000 0x0 0x10000>,
 589                                 <0x0 0x19830000 0x0 0x10000>,
 590                                 <0x0 0x19840000 0x0 0x10000>,
 591                                 <0x0 0x19870000 0x0 0x30000>,
 592                                 <0x0 0x198a0000 0x0 0x30000>,
 593                                 <0x0 0x11840000 0x0 0x10000>,
 594                                 <0x0 0x17030000 0x0 0x10000>,
 595                                 <0x0 0x13020000 0x0 0x10000>;
 596                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
 597                                 "isp0", "isp1", "trst", "pmu", "syscrg";
 598                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 599                                 <&clkisp JH7110_U0_VIN_PCLK>,
 600                                 <&clkisp JH7110_U0_VIN_SYS_CLK>,
 601                                 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 602                                 <&clkisp JH7110_DVP_INV>,
 603                                 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 604                                 <&clkisp JH7110_MIPI_RX0_PXL>,
 605                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 606                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 607                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 608                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>;
 609                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 610                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 611                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 612                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 613                                 "clk_pixel_clk_if3";
 614                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 615                                 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 616                                 <&rstgen RSTN_U0_VIN_N_PCLK>,
 617                                 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 618                                 <&rstgen RSTN_U0_VIN_P_AXIRD>,
 619                                 <&rstgen RSTN_U0_VIN_P_AXIWR>,
 620                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 621                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 622                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 623                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>;
 624                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 625                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 626                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3";
 627                         interrupts = <92 87 86>;
 628                         status = "disabled";
 629                 };
 630
 631                 jpu: jpu@11900000 {
 632                         compatible = "starfive,jpu";
 633                         reg = <0x0 0x13090000 0x0 0x300>;
 634                         interrupts = <14>;
 635                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 636                                 <&clkgen JH7110_CODAJ12_CLK_CORE>,
 637                                 <&clkgen JH7110_CODAJ12_CLK_APB>;
 638                         clock-names = "axi_clk", "core_clk", "apb_clk";
 639                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 640                                 <&rstgen RSTN_U0_CODAJ12_CORE>,
 641                                 <&rstgen RSTN_U0_CODAJ12_APB>;
 642                         reset-names = "rst_axi", "rst_core", "rst_apb";
 643                         status = "disabled";
 644                 };
 645
 646                 vpu_dec: vpu_dec@130A0000 {
 647                         compatible = "starfive,vdec";
 648                         reg = <0x0 0x130A0000 0x0 0x10000>;
 649                         interrupts = <13>;
 650                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 651                                 <&clkgen JH7110_WAVE511_CLK_BPU>,
 652                                 <&clkgen JH7110_WAVE511_CLK_VCE>,
 653                                 <&clkgen JH7110_WAVE511_CLK_APB>,
 654                                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 655                         clock-names = "axi_clk",
 656                                 "bpu_clk",
 657                                 "vce_clk",
 658                                 "apb_clk",
 659                                 "noc_bus";
 660                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 661                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 662                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 663                                 <&rstgen RSTN_U0_WAVE511_APB>,
 664                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 665                         reset-names = "rst_axi",
 666                                 "rst_bpu",
 667                                 "rst_vce",
 668                                 "rst_apb",
 669                                 "rst_sram";
 670                         starfive,vdec_noc_ctrl;
 671                         status = "disabled";
 672                 };
 673
 674                 vpu_enc: vpu_enc@130B0000 {
 675                         compatible = "starfive,venc";
 676                         reg = <0x0 0x130B0000 0x0 0x10000>;
 677                         interrupts = <15>;
 678                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 679                                 <&clkgen JH7110_WAVE420L_CLK_BPU>,
 680                                 <&clkgen JH7110_WAVE420L_CLK_VCE>,
 681                                 <&clkgen JH7110_WAVE420L_CLK_APB>,
 682                                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 683                         clock-names = "axi_clk",
 684                                 "bpu_clk",
 685                                 "vce_clk",
 686                                 "apb_clk",
 687                                 "noc_bus";
 688                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 689                                 <&rstgen RSTN_U0_WAVE420L_BPU>,
 690                                 <&rstgen RSTN_U0_WAVE420L_VCE>,
 691                                 <&rstgen RSTN_U0_WAVE420L_APB>,
 692                                 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 693                         reset-names = "rst_axi",
 694                                 "rst_bpu",
 695                                 "rst_vce",
 696                                 "rst_apb",
 697                                 "rst_sram";
 698                         starfive,venc_noc_ctrl;
 699                         status = "disabled";
 700                 };
 701
 702                 rstgen: reset-controller {
 703                         compatible = "starfive,jh7110-reset";
 704                         reg = <0x0 0x13020000 0x0 0x10000>,
 705                                 <0x0 0x10230000 0x0 0x10000>,
 706                                 <0x0 0x17000000 0x0 0x10000>,
 707                                 <0x0 0x19810000 0x0 0x10000>,
 708                                 <0x0 0x295C0000 0x0 0x10000>;
 709                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 710                         #reset-cells = <1>;
 711                         status = "okay";
 712                 };
 713
 714                 stmmac_axi_setup: stmmac-axi-config {
 715                         snps,wr_osr_lmt = <0xf>;
 716                         snps,rd_osr_lmt = <0xf>;
 717                         snps,blen = <256 128 64 32 0 0 0>;
 718                 };
 719
 720                 gmac0: ethernet@16030000 {
 721                         compatible = "starfive,jh7110-eqos-5.20";
 722                         reg = <0x0 0x16030000 0x0 0x10000>;
 723                         clock-names = "gtx",
 724                                 "tx",
 725                                 "ptp_ref",
 726                                 "stmmaceth",
 727                                 "pclk";
 728                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 729                                 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 730                                 <&clkgen JH7110_GMAC0_PTP>,
 731                                 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 732                                 <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
 733                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 734                                         <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 735                         reset-names = "ahb", "stmmaceth";
 736                         interrupts = <7>, <6>, <5> ;
 737                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 738                         max-frame-size = <9000>;
 739                         phy-mode = "rgmii-id";
 740                         snps,multicast-filter-bins = <256>;
 741                         snps,perfect-filter-entries = <128>;
 742                         rx-fifo-depth = <262144>;
 743                         tx-fifo-depth = <131072>;
 744                         snps,fixed-burst;
 745                         snps,no-pbl-x8;
 746                         snps,force_thresh_dma_mode;
 747                         snps,axi-config = <&stmmac_axi_setup>;
 748                         snps,tso;
 749                         snps,en-tx-lpi-clockgating;
 750                         snps,en-lpi;
 751                         snps,write-requests = <2>;
 752                         snps,read-requests = <16>;
 753                         snps,burst-map = <0x7>;
 754                         snps,txpbl = <16>;
 755                         snps,rxpbl = <16>;
 756                         status = "disabled";
 757                 };
 758
 759                 gmac1: ethernet@16040000 {
 760                         compatible = "starfive,jh7110-eqos-5.20";
 761                         reg = <0x0 0x16040000 0x0 0x10000>;
 762                         clock-names = "gtx",
 763                                 "tx",
 764                                 "ptp_ref",
 765                                 "stmmaceth",
 766                                 "pclk";
 767                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 768                                 <&clkgen JH7110_GMAC5_CLK_TX>,
 769                                 <&clkgen JH7110_GMAC5_CLK_PTP>,
 770                                 <&clkgen JH7110_GMAC5_CLK_AHB>,
 771                                 <&clkgen JH7110_GMAC5_CLK_AXI>;
 772                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
 773                                         <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 774                         reset-names = "ahb", "stmmaceth";
 775                         interrupts = <78>, <77>, <76> ;
 776                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 777                         max-frame-size = <9000>;
 778                         phy-mode = "rgmii-id";
 779                         snps,multicast-filter-bins = <256>;
 780                         snps,perfect-filter-entries = <128>;
 781                         rx-fifo-depth = <262144>;
 782                         tx-fifo-depth = <131072>;
 783                         snps,fixed-burst;
 784                         snps,no-pbl-x8;
 785                         snps,force_thresh_dma_mode;
 786                         snps,axi-config = <&stmmac_axi_setup>;
 787                         snps,tso;
 788                         snps,en-tx-lpi-clockgating;
 789                         snps,en-lpi;
 790                         snps,write-requests = <2>;
 791                         snps,read-requests = <16>;
 792                         snps,burst-map = <0x7>;
 793                         snps,txpbl = <16>;
 794                         snps,rxpbl = <16>;
 795                         status = "disabled";
 796                 };
 797
 798                 gpu: gpu@18000000 {
 799                         compatible = "img-gpu";
 800                         reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
 801                         clocks = <&gpu_core_clk>, <&gpu_sys_clk>;
 802                         clock-names = "gpu_core_clk","gpu_sys_clk";
 803                         interrupts = <82>;
 804                         current-clock = <8000000>;
 805                         status = "disabled";
 806                 };
 807
 808                 can0: can@130d0000 {
 809                         compatible = "ipms,can";
 810                         reg = <0x0 0x130d0000 0x0 0x1000>;
 811                         interrupts = <112>;
 812                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
 813                                 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
 814                                 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
 815                         clock-names = "apb_clk",
 816                                         "core_clk",
 817                                         "timer_clk";
 818                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
 819                                 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
 820                                 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
 821                         reset-names = "rst_apb",
 822                                         "rst_core",
 823                                         "rst_timer";
 824                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
 825                         syscon,can_or_canfd = <0>;
 826                         status = "disabled";
 827                 };
 828
 829                 can1: can@130e0000 {
 830                         compatible = "ipms,can";
 831                         reg = <0x0 0x130e0000 0x0 0x1000>;
 832                         interrupts = <113>;
 833                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
 834                                 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
 835                                 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
 836                         clock-names = "apb_clk",
 837                                         "core_clk",
 838                                         "timer_clk";
 839                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
 840                                 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
 841                                 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
 842                         reset-names = "rst_apb",
 843                                         "rst_core",
 844                                         "rst_timer";
 845                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
 846                         syscon,can_or_canfd = <0>;
 847                         status = "disabled";
 848                 };
 849
 850                 tdm: tdm@10090000 {
 851                         compatible = "starfive,tdm";
 852                         reg = <0x0 0x10090000 0x0 0x1000>;
 853                         reg-names = "tdm";
 854                         clocks = <&audioclk>;
 855                         clock-names = "audioclk";
 856                         dmas = <&dma 20 1>, <&dma 21 1>;
 857                         dma-names = "rx","tx";
 858                         #sound-dai-cells = <0>;
 859                         status = "disabled";
 860                 };
 861
 862                 spdif0: spdif0@100a0000 {
 863                         compatible = "starfive,sf-spdif";
 864                         reg = <0x0 0x100a0000 0x0 0x1000>;
 865                         clocks = <&audioclk>;
 866                         clock-names = "audioclk";
 867                         interrupts = <84>;
 868                         interrupt-names = "tx";
 869                         #sound-dai-cells = <0>;
 870                         status = "disabled";
 871                 };
 872
 873                 pwmdac: pwmdac@100b0000 {
 874                         compatible = "sf,pwmdac";
 875                         reg = <0x0 0x100b0000 0x0 0x1000>;
 876                         clocks = <&apb0clk>;
 877                         dmas = <&dma 22 1>;
 878                         dma-names = "tx";
 879                         #sound-dai-cells = <0>;
 880                         status = "disabled";
 881                 };
 882
 883                 i2stx: i2stx@100c0000 {
 884                         compatible = "snps,designware-i2stx";
 885                         reg = <0x0 0x100c0000 0x0 0x1000>;
 886                         clocks = <&apb0clk>;
 887                         clock-names = "i2sclk";
 888                         interrupt-names = "tx";
 889                         #sound-dai-cells = <0>;
 890                         dmas = <&dma 28 1>;
 891                         dma-names = "rx";
 892                         status = "disabled";
 893                 };
 894
 895                 pdm: pdm@100d0000 {
 896                         compatible = "starfive,sf-pdm";
 897                         reg = <0x0 0x100d0000 0x0 0x1000>;
 898                         reg-names = "pdm";
 899                         clocks = <&audioclk>;
 900                         clock-names = "audioclk";
 901                         #sound-dai-cells = <0>;
 902                         status = "disabled";
 903                 };
 904
 905                 i2srx_3ch: i2srx-3ch@100e0000 {
 906                         compatible = "snps,designware-i2srx";
 907                         reg = <0x0 0x100e0000 0x0 0x1000>;
 908                         clocks = <&apb0clk>;
 909                         clock-names = "i2sclk";
 910                         interrupts = <42>;
 911                         interrupt-names = "rx";
 912                         #sound-dai-cells = <0>;
 913                         status = "disabled";
 914                 };
 915
 916                 i2stx_4ch0: i2stx-4ch0@120b0000 {
 917                         compatible = "snps,designware-i2stx-4ch0";
 918                         reg = <0x0 0x120b0000 0x0 0x1000>;
 919                         clocks = <&apb0clk>;
 920                         clock-names = "i2sclk";
 921                         interrupts = <58>;
 922                         interrupt-names = "tx";
 923                         #sound-dai-cells = <0>;
 924                         status = "disabled";
 925                 };
 926
 927                 i2stx_4ch1: i2sdac1@120c0000 {
 928                         compatible = "snps,designware-i2stx-4ch1";
 929                         reg = <0x0 0x120c0000 0x0 0x1000>;
 930                         clocks = <&apb0clk>;
 931                         clock-names = "i2sclk";
 932                         interrupts = <59>;
 933                         interrupt-names = "tx";
 934                         #sound-dai-cells = <0>;
 935                         status = "disabled";
 936                 };
 937
 938                 ptc: pwm@120d0000 {
 939                         compatible = "starfive,pwm0";
 940                         reg = <0x0 0x120d0000 0x0 0x10000>;
 941                         reg-names = "control";
 942                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
 943                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
 944                         starfive,approx-period = <2000000>;
 945                         #pwm-cells=<3>;
 946                         starfive,npwm = <8>;
 947                         status = "disabled";
 948                 };
 949
 950                 spdif_transmitter: spdif_transmitter {
 951                         compatible = "linux,spdif-dit";
 952                         #sound-dai-cells = <0>;
 953                         status = "disabled";
 954                 };
 955
 956                 spdif_receiver: spdif_receiver {
 957                         compatible = "linux,spdif-dir";
 958                         #sound-dai-cells = <0>;
 959                         status = "disabled";
 960                 };
 961
 962                 pwmdac_codec: pwmdac-transmitter {
 963                         compatible = "linux,pwmdac-dit";
 964                         #sound-dai-cells = <0>;
 965                         status = "disabled";
 966                 };
 967
 968                 dmic_codec: dmic_codec {
 969                         compatible = "dmic-codec";
 970                         #sound-dai-cells = <0>;
 971                         status = "disabled";
 972                 };
 973
 974                 spi0: spi0@10060000 {
 975                         compatible = "arm,pl022", "arm,primecell";
 976                         reg = <0x0 0x10060000 0x0 0x10000>;
 977                         clocks = <&ahb1clk>;
 978                         clock-names = "apb_pclk";
 979                         interrupts = <38>;
 980                         dmas = <&dma 14 1>, <&dma 15 1>;
 981                         dma-names = "rx","tx";
 982                         arm,primecell-periphid = <0x00041022>;
 983                         num-cs = <1>;
 984                         #address-cells = <1>;
 985                         #size-cells = <0>;
 986                         status = "disabled";
 987                 };
 988
 989                 pcie0: pcie0@2B000000 {
 990                         compatible = "plda,pci-xpressrich3-axi";
 991                         reg = <0x0 0x2B000000 0x0 0x1000000
 992                                0x9 0x40000000 0x0 0x10000000>;
 993                         reg-names = "reg", "config";
 994                         interrupts = <56>;
 995                         interrupt-controller;
 996                         interrupt-names = "msi";
 997                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 998                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
 999                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1000                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1001                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1002                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1003                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1004                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1005                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1006                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1007                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1008                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1009                                       "rst_brg", "rst_core", "rst_apb";
1010                         clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
1011                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1012                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1013                         clock-names =  "tl", "axi_mst0", "apb";
1014                         #interrupt-cells = <1>;
1015                         device_type = "pci";
1016                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1017                         bus-range = <0x0 0xff>;
1018                         msi-parent = <&plic>;
1019                         #address-cells = <3>;
1020                         #size-cells = <2>;
1021                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
1022                         status = "disabled";
1023                 };
1024
1025                 pcie1:pcie1@2C000000 {
1026                         compatible = "plda,pci-xpressrich3-axi";
1027                         reg = <0x0 0x2C000000 0x0 0x1000000
1028                                0x9 0xc0000000 0x0 0x10000000>;
1029                         reg-names = "reg", "config";
1030                         device_type = "pci";
1031                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1032                         bus-range = <0x0 0xff>;
1033                         #address-cells = <3>;
1034                         #size-cells = <2>;
1035                         #interrupt-cells = <1>;
1036                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
1037                         msi-parent = <&plic>;
1038                         interrupts = <57>;
1039                         interrupt-controller;
1040                         interrupt-names = "msi";
1041                         interrupt-parent = <&plic>;
1042                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1043                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1044                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1045                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1046                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1047                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1048                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1049                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1050                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1051                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1052                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1053                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1054                                       "rst_brg", "rst_core", "rst_apb";
1055                         clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
1056                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1057                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1058                         clock-names =  "tl", "axi_mst0", "apb";
1059                         status = "disabled";
1060                 };
1061
1062                 mailbox_contrl0: mailbox@0 {
1063                         compatible = "starfive,mail_box";
1064                         reg = <0x0 0x13060000 0x0 0x0001000>;
1065                         interrupts = <26 27>;
1066                         #mbox-cells = <2>;
1067                         status = "disabled";
1068                 };
1069
1070                 mailbox_client0: mailbox_client@0 {
1071                         compatible = "starfive,mailbox-test";
1072                         mbox-names = "rx", "tx";
1073                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1074                         status = "disabled";
1075                 };
1076
1077                 display: display-subsystem {
1078                         compatible = "verisilicon,display-subsystem";
1079                         ports = <&dc_out_dpi0>;
1080                         status = "disabled";
1081                 };
1082
1083                 encoder: display-encoder {
1084                         compatible = "starfive,display-encoder";
1085                         status = "disabled";
1086                 };
1087
1088                 dc8200@29400000 {
1089                         compatible = "verisilicon,dc8200";
1090                         reg = <0x0 0x29400000 0x0 0x100>,<0x0 0x29400800 0x0 0x2000>;
1091                         interrupts = <95>;
1092
1093                         port {
1094                                 #address-cells = <1>;
1095                                 #size-cells = <0>;
1096                                 dc_out_dpi0: endpoint@0 {
1097                                         /*reg = <0>;
1098                                         remote-endpoint = <&hdmi_input>;*/
1099                                 };
1100                                 dc_out_dpi1: endpoint@1 {
1101                                         /*reg = <1>;
1102                                         remote-endpoint = <&vd_input>;*/
1103                                 };
1104                         };
1105                 };
1106
1107                 sound_pwmdac: snd-card_pwmdac {
1108                         compatible = "simple-audio-card";
1109                         simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
1110                         simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
1111                         simple-audio-card,frame-master = <&pwmdac_dailink_master>;
1112                         simple-audio-card,format = "left_j";
1113                         status = "disabled";
1114
1115                         pwmdac_dailink_master: simple-audio-card,cpu {
1116                                 sound-dai = <&pwmdac>;
1117                         };
1118
1119                         simple-audio-card,codec {
1120                                 sound-dai = <&pwmdac_codec>;
1121                         };
1122                 };
1123         };
1124 };