arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110_clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13
  14 / {
  15         compatible = "starfive,jh7110";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: cpu@0 {
  24                         compatible = "sifive,u74-mc", "riscv";
  25                         reg = <0>;
  26                         d-cache-block-size = <64>;
  27                         d-cache-sets = <64>;
  28                         d-cache-size = <8192>;
  29                         d-tlb-sets = <1>;
  30                         d-tlb-size = <40>;
  31                         device_type = "cpu";
  32                         i-cache-block-size = <64>;
  33                         i-cache-sets = <64>;
  34                         i-cache-size = <16384>;
  35                         i-tlb-sets = <1>;
  36                         i-tlb-size = <40>;
  37                         mmu-type = "riscv,sv39";
  38                         next-level-cache = <&cachectrl>;
  39                         riscv,isa = "rv64imac";
  40                         tlb-split;
  41                         status = "disabled";
  42
  43                         cpu0intctrl: interrupt-controller {
  44                                 #interrupt-cells = <1>;
  45                                 compatible = "riscv,cpu-intc";
  46                                 interrupt-controller;
  47                         };
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         compatible = "sifive,u74-mc", "riscv";
  52                         reg = <1>;
  53                         d-cache-block-size = <64>;
  54                         d-cache-sets = <64>;
  55                         d-cache-size = <32768>;
  56                         d-tlb-sets = <1>;
  57                         d-tlb-size = <40>;
  58                         device_type = "cpu";
  59                         i-cache-block-size = <64>;
  60                         i-cache-sets = <64>;
  61                         i-cache-size = <32768>;
  62                         i-tlb-sets = <1>;
  63                         i-tlb-size = <40>;
  64                         mmu-type = "riscv,sv39";
  65                         next-level-cache = <&cachectrl>;
  66                         riscv,isa = "rv64imafdc";
  67                         tlb-split;
  68                         status = "okay";
  69
  70                         cpu1intctrl: interrupt-controller {
  71                                 #interrupt-cells = <1>;
  72                                 compatible = "riscv,cpu-intc";
  73                                 interrupt-controller;
  74                         };
  75                 };
  76
  77                 cpu2: cpu@2 {
  78                         compatible = "sifive,u74-mc", "riscv";
  79                         reg = <2>;
  80                         d-cache-block-size = <64>;
  81                         d-cache-sets = <64>;
  82                         d-cache-size = <32768>;
  83                         d-tlb-sets = <1>;
  84                         d-tlb-size = <40>;
  85                         device_type = "cpu";
  86                         i-cache-block-size = <64>;
  87                         i-cache-sets = <64>;
  88                         i-cache-size = <32768>;
  89                         i-tlb-sets = <1>;
  90                         i-tlb-size = <40>;
  91                         mmu-type = "riscv,sv39";
  92                         next-level-cache = <&cachectrl>;
  93                         riscv,isa = "rv64imafdc";
  94                         tlb-split;
  95                         status = "okay";
  96
  97                         cpu2intctrl: interrupt-controller {
  98                                 #interrupt-cells = <1>;
  99                                 compatible = "riscv,cpu-intc";
 100                                 interrupt-controller;
 101                         };
 102                 };
 103
 104                 cpu3: cpu@3 {
 105                         compatible = "sifive,u74-mc", "riscv";
 106                         reg = <3>;
 107                         d-cache-block-size = <64>;
 108                         d-cache-sets = <64>;
 109                         d-cache-size = <32768>;
 110                         d-tlb-sets = <1>;
 111                         d-tlb-size = <40>;
 112                         device_type = "cpu";
 113                         i-cache-block-size = <64>;
 114                         i-cache-sets = <64>;
 115                         i-cache-size = <32768>;
 116                         i-tlb-sets = <1>;
 117                         i-tlb-size = <40>;
 118                         mmu-type = "riscv,sv39";
 119                         next-level-cache = <&cachectrl>;
 120                         riscv,isa = "rv64imafdc";
 121                         tlb-split;
 122                         status = "okay";
 123
 124                         cpu3intctrl: interrupt-controller {
 125                                 #interrupt-cells = <1>;
 126                                 compatible = "riscv,cpu-intc";
 127                                 interrupt-controller;
 128                         };
 129                 };
 130
 131                 cpu4: cpu@4 {
 132                         compatible = "sifive,u74-mc", "riscv";
 133                         reg = <4>;
 134                         d-cache-block-size = <64>;
 135                         d-cache-sets = <64>;
 136                         d-cache-size = <32768>;
 137                         d-tlb-sets = <1>;
 138                         d-tlb-size = <40>;
 139                         device_type = "cpu";
 140                         i-cache-block-size = <64>;
 141                         i-cache-sets = <64>;
 142                         i-cache-size = <32768>;
 143                         i-tlb-sets = <1>;
 144                         i-tlb-size = <40>;
 145                         mmu-type = "riscv,sv39";
 146                         next-level-cache = <&cachectrl>;
 147                         riscv,isa = "rv64imafdc";
 148                         tlb-split;
 149                         status = "okay";
 150
 151                         cpu4intctrl: interrupt-controller {
 152                                 #interrupt-cells = <1>;
 153                                 compatible = "riscv,cpu-intc";
 154                                 interrupt-controller;
 155                         };
 156                 };
 157         };
 158
 159         soc: soc {
 160                 compatible = "simple-bus";
 161                 interrupt-parent = <&plic>;
 162                 #address-cells = <2>;
 163                 #size-cells = <2>;
 164                 #clock-cells = <1>;
 165                 ranges;
 166
 167                 cachectrl: cache-controller@2010000 {
 168                         compatible = "sifive,fu740-c000-ccache", "cache";
 169                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 170                         reg-names = "control", "sideband";
 171                         interrupts = <1 3 4 2>;
 172                         cache-block-size = <64>;
 173                         cache-level = <2>;
 174                         cache-sets = <2048>;
 175                         cache-size = <2097152>;
 176                         cache-unified;
 177                 };
 178
 179                 aon_syscon: aon_syscon@17010000 {
 180                         compatible = "syscon";
 181                         reg = <0x0 0x17010000 0x0 0x1000>;
 182                 };
 183
 184                 stg_syscon: stg_syscon@10240000 {
 185                         compatible = "syscon";
 186                         reg = <0x0 0x10240000 0x0 0x1000>;
 187                 };
 188
 189                 sys_syscon: sys_syscon@13030000 {
 190                         compatible = "syscon";
 191                         reg = <0x0 0x13030000 0x0 0x1000>;
 192                 };
 193
 194                 clint: clint@2000000 {
 195                         compatible = "riscv,clint0";
 196                         reg = <0x0 0x2000000 0x0 0x10000>;
 197                         reg-names = "control";
 198                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 199                                                 &cpu1intctrl 3 &cpu1intctrl 7
 200                                                 &cpu2intctrl 3 &cpu2intctrl 7
 201                                                 &cpu3intctrl 3 &cpu3intctrl 7
 202                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 203                         #interrupt-cells = <1>;
 204                 };
 205
 206                 plic: plic@c000000 {
 207                         compatible = "riscv,plic0";
 208                         reg = <0x0 0xc000000 0x0 0x4000000>;
 209                         reg-names = "control";
 210                         interrupts-extended = <&cpu0intctrl 11
 211                                                 &cpu1intctrl 11 &cpu1intctrl 9
 212                                                 &cpu2intctrl 11 &cpu2intctrl 9
 213                                                 &cpu3intctrl 11 &cpu3intctrl 9
 214                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <1>;
 217                         riscv,max-priority = <7>;
 218                         riscv,ndev = <136>;
 219                 };
 220
 221                 clkgen: clock-controller {
 222                         compatible = "starfive,jh7110-clkgen";
 223                         reg = <0x0 0x13020000 0x0 0x10000>,
 224                                 <0x0 0x10230000 0x0 0x10000>,
 225                                 <0x0 0x17000000 0x0 0x10000>;
 226                         reg-names = "sys", "stg", "aon";
 227                         clocks = <&osc>, <&gmac1_rmii_refin>,
 228                                  <&gmac1_rgmii_rxin>,
 229                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 230                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 231                                  <&tdm_ext>, <&mclk_ext>,
 232                                  <&jtag_tck_inner>, <&bist_apb>,
 233                                  <&stg_apb>, <&clk_rtc>,
 234                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 235                         clock-names = "osc", "gmac1_rmii_refin",
 236                                 "gmac1_rgmii_rxin",
 237                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 238                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 239                                 "tdm_ext", "mclk_ext",
 240                                 "jtag_tck_inner", "bist_apb",
 241                                 "stg_apb", "clk_rtc",
 242                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 243                         #clock-cells = <1>;
 244                         status = "okay";
 245                 };
 246
 247                 clkvout: clock-controller@295C0000 {
 248                         compatible = "starfive,jh7110-clk-vout";
 249                         reg = <0x0 0x295C0000 0x0 0x10000>;
 250                         reg-names = "vout";
 251                         clocks = <&hdmitx0_pixelclk>,
 252                                  <&mipitx_dphy_rxesc>,
 253                                  <&mipitx_dphy_txbytehs>;
 254                         clock-names = "hdmitx0_pixelclk",
 255                                 "mipitx_dphy_rxesc",
 256                                 "mipitx_dphy_txbytehs";
 257                         #clock-cells = <1>;
 258                         status = "okay";
 259                 };
 260
 261                 clkisp: clock-controller@19810000 {
 262                         compatible = "starfive,jh7110-clk-isp";
 263                         reg = <0x0 0x19810000 0x0 0x10000>;
 264                         reg-names = "isp";
 265                         #clock-cells = <1>;
 266                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 267                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 268                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 269                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 270                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 271                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 272                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 273                                       "u0_sft7110_noc_bus_clk_isp_axi";
 274                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 275                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 276                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 277                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 278                                       "rst_isp_noc_bus_n";
 279                         status = "disabled";
 280                 };
 281
 282                 qspi: spi@13010000 {
 283                         compatible = "cdns,qspi-nor";
 284                         #address-cells = <1>;
 285                         #size-cells = <0>;
 286                         reg = <0x0 0x13010000 0x0 0x10000
 287                                 0x0 0x21000000 0x0 0x400000>;
 288                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 289                         clock-names = "clk_ref";
 290                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 291                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 292                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 293                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 294                         cdns,fifo-depth = <256>;
 295                         cdns,fifo-width = <4>;
 296                         spi-max-frequency = <250000000>;
 297
 298                         nor_flash: nor-flash@0 {
 299                                 compatible = "jedec,spi-nor";
 300                                 reg=<0>;
 301                                 spi-max-frequency = <100000000>;
 302                                 cdns,tshsl-ns = <1>;
 303                                 cdns,tsd2d-ns = <1>;
 304                                 cdns,tchsh-ns = <1>;
 305                                 cdns,tslch-ns = <1>;
 306                         };
 307                 };
 308
 309                 otp: otp@17050000 {
 310                         compatible = "starfive,jh7110-otp";
 311                         reg = <0x0 0x17050000 0x0 0x10000>;
 312                         clock-frequency = <4000000>;
 313                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 314                         clock-names = "apb";
 315                 };
 316
 317                 usbdrd30: usbdrd{
 318                         compatible = "starfive,jh7110-cdns3";
 319                         #address-cells = <2>;
 320                         #size-cells = <2>;
 321                         clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
 322                                  <&clkgen JH7110_USB0_CLK_LPM>,
 323                                  <&clkgen JH7110_USB0_CLK_STB>,
 324                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 325                                  <&clkgen JH7110_USB0_CLK_AXI>,
 326                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 327                         clock-names = "app","lpm","stb","apb","axi","utmi";
 328                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 329                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 330                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 331                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 332                         reset-names = "pwrup","apb","axi","utmi";
 333                         starfive,stg-syscon = <&stg_syscon 0x4>;
 334                         starfive,sys-syscon = <&sys_syscon 0x18>;
 335                         status = "disabled";
 336
 337                         usbdrd_cdns3: usb@10100000 {
 338                                 compatible = "cdns,usb3";
 339                                 reg = <0x0 0x10100000 0x0 0x10000>,
 340                                       <0x0 0x10110000 0x0 0x10000>,
 341                                       <0x0 0x10120000 0x0 0x10000>;
 342                                 reg-names = "otg", "xhci", "dev";
 343                                 interrupts = <108>, <109>, <110>;
 344                                 interrupt-names = "host", "peripheral", "otg";
 345                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 346                                 maximum-speed = "super-speed";
 347                         };
 348                 };
 349
 350                 timer: timer@13050000 {
 351                         compatible = "starfive,si5-timers";
 352                         reg = <0x0 0x13050000 0x0 0x10000>;
 353                         interrupts = <69>, <70>, <71> ,<72>;
 354                         interrupt-names = "timer0", "timer1",
 355                                           "timer2", "timer3";
 356                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 357                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 358                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 359                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 360                                  <&clkgen JH7110_TIMER_CLK_APB>;
 361                         clock-names = "timer0", "timer1",
 362                                       "timer2", "timer3", "apb_clk";
 363                         clock-frequency = <24000000>;
 364                         status = "okay";
 365                 };
 366
 367                 wdog: wdog@13070000 {
 368                         compatible = "starfive,dskit-wdt";
 369                         reg = <0x0 0x13070000 0x0 0x10000>;
 370                         interrupts = <68>;
 371                         interrupt-names = "wdog";
 372                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 373                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 374                         clock-names = "core_clk", "apb_clk";
 375                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 376                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 377                         reset-names = "rst_apb", "rst_core";
 378                         timeout-sec = <15>;
 379                         status = "okay";
 380                 };
 381
 382                 rtc: rtc@17040000 {
 383                         compatible = "starfive,rtc_hms";
 384                         reg = <0x0 0x17040000 0x0 0x10000>;
 385                         interrupts = <10>, <11>, <12>;
 386                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 387                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 388                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 389                         clock-names = "pclk", "cal_clk";
 390                         resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
 391                                  <&rstgen RSTN_U0_RTC_HMS_CAL>,
 392                                  <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
 393                         reset-names = "rst_apb", "rst_cal", "rst_osc";
 394                         rtc,cal-clock-freq = <1000000>;
 395                         status = "okay";
 396                 };
 397
 398                 pmu: pmu@17030000 {
 399                         compatible = "starfive,jh7110-pmu";
 400                         reg = <0x0 0x17030000 0x0 0x10000>;
 401                         interrupts = <111>;
 402                         status = "okay";
 403                 };
 404
 405                 uart0: serial@10000000 {
 406                         compatible = "snps,dw-apb-uart";
 407                         reg = <0x0 0x10000000 0x0 0x10000>;
 408                         reg-io-width = <4>;
 409                         reg-shift = <2>;
 410                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 411                                  <&clkgen JH7110_UART0_CLK_APB>;
 412                         clock-names = "baudclk", "apb_pclk";
 413                         resets = <&rstgen RSTN_U0_DW_UART_APB>;
 414                         interrupts = <32>;
 415                         status = "disabled";
 416                 };
 417
 418                 uart1: serial@10010000 {
 419                         compatible = "snps,dw-apb-uart";
 420                         reg = <0x0 0x10010000 0x0 0x10000>;
 421                         reg-io-width = <4>;
 422                         reg-shift = <2>;
 423                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 424                                  <&clkgen JH7110_UART1_CLK_APB>;
 425                         clock-names = "baudclk", "apb_pclk";
 426                         resets = <&rstgen RSTN_U1_DW_UART_APB>;
 427                         interrupts = <33>;
 428                         status = "disabled";
 429                 };
 430
 431                 uart2: serial@10020000 {
 432                         compatible = "snps,dw-apb-uart";
 433                         reg = <0x0 0x10020000 0x0 0x10000>;
 434                         reg-io-width = <4>;
 435                         reg-shift = <2>;
 436                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 437                                  <&clkgen JH7110_UART2_CLK_APB>;
 438                         clock-names = "baudclk", "apb_pclk";
 439                         resets = <&rstgen RSTN_U2_DW_UART_APB>;
 440                         interrupts = <34>;
 441                         status = "disabled";
 442                 };
 443
 444                 uart3: serial@12000000 {
 445                         compatible = "snps,dw-apb-uart";
 446                         reg = <0x0 0x12000000 0x0 0x10000>;
 447                         reg-io-width = <4>;
 448                         reg-shift = <2>;
 449                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 450                                  <&clkgen JH7110_UART3_CLK_APB>;
 451                         clock-names = "baudclk", "apb_pclk";
 452                         resets = <&rstgen RSTN_U3_DW_UART_APB>;
 453                         interrupts = <45>;
 454                         status = "disabled";
 455                 };
 456
 457                 uart4: serial@12010000 {
 458                         compatible = "snps,dw-apb-uart";
 459                         reg = <0x0 0x12010000 0x0 0x10000>;
 460                         reg-io-width = <4>;
 461                         reg-shift = <2>;
 462                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 463                                  <&clkgen JH7110_UART4_CLK_APB>;
 464                         clock-names = "baudclk", "apb_pclk";
 465                         resets = <&rstgen RSTN_U4_DW_UART_APB>;
 466                         interrupts = <46>;
 467                         status = "disabled";
 468                 };
 469
 470                 uart5: serial@12020000 {
 471                         compatible = "snps,dw-apb-uart";
 472                         reg = <0x0 0x12020000 0x0 0x10000>;
 473                         reg-io-width = <4>;
 474                         reg-shift = <2>;
 475                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 476                                  <&clkgen JH7110_UART5_CLK_APB>;
 477                         clock-names = "baudclk", "apb_pclk";
 478                         resets = <&rstgen RSTN_U5_DW_UART_APB>;
 479                         interrupts = <47>;
 480                         status = "disabled";
 481                 };
 482
 483                 dma: dma-controller@16050000 {
 484                         compatible = "starfive,axi-dma";
 485                         reg = <0x0 0x16050000 0x0 0x10000>;
 486                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 487                                  <&clkgen JH7110_DMA1P_CLK_AHB>;
 488                         clock-names = "core-clk", "cfgr-clk";
 489                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 490                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 491                         reset-names = "rst_axi", "rst_ahb";
 492                         interrupts = <73>;
 493                         #dma-cells = <2>;
 494                         dma-channels = <4>;
 495                         snps,dma-masters = <1>;
 496                         snps,data-width = <3>;
 497                         snps,num-hs-if = <56>;
 498                         snps,block-size = <65536 65536 65536 65536>;
 499                         snps,priority = <0 1 2 3>;
 500                         snps,axi-max-burst-len = <16>;
 501                         status = "disabled";
 502                 };
 503
 504                 gpio: gpio@13040000 {
 505                         compatible = "starfive_jh7110-sys-pinctrl";
 506                         reg = <0x0 0x13040000 0x0 0x10000>;
 507                         reg-names = "control";
 508                         interrupts = <91>;
 509                         interrupt-controller;
 510                         #gpio-cells = <2>;
 511                         ngpios = <64>;
 512                         status = "okay";
 513                 };
 514
 515                 gpioa: gpio@17020000 {
 516                         compatible = "starfive_jh7110-aon-pinctrl";
 517                         reg = <0x0 0x17020000 0x0 0x10000>;
 518                         reg-names = "control";
 519                         interrupts = <90>;
 520                         interrupt-controller;
 521                         #gpio-cells = <2>;
 522                         ngpios = <4>;
 523                         status = "okay";
 524                 };
 525
 526                 sfctemp: tmon@120e0000  {
 527                         compatible = "starfive,jh7110-temp";
 528                         reg = <0x0 0x120e0000 0x0 0x10000>;
 529                         interrupts = <81>;
 530                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 531                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 532                         clock-names = "sense", "bus";
 533                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 534                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 535                         reset-names = "sense", "bus";
 536                         #thermal-sensor-cells = <0>;
 537                         status = "disabled";
 538                 };
 539
 540                 thermal-zones {
 541                         cpu-thermal {
 542                                 polling-delay-passive = <250>;
 543                                 polling-delay = <15000>;
 544
 545                                 thermal-sensors = <&sfctemp>;
 546
 547                                 cooling-maps {
 548                                 };
 549
 550                                 trips {
 551                                         cpu_alert0: cpu_alert0 {
 552                                                 /* milliCelsius */
 553                                                 temperature = <75000>;
 554                                                 hysteresis = <2000>;
 555                                                 type = "passive";
 556                                         };
 557
 558                                         cpu_crit: cpu_crit {
 559                                                 /* milliCelsius */
 560                                                 temperature = <90000>;
 561                                                 hysteresis = <2000>;
 562                                                 type = "critical";
 563                                         };
 564                                 };
 565                         };
 566                 };
 567
 568                 trng: trng@1600C000 {
 569                         compatible = "starfive,trng";
 570                         reg = <0x0 0x1600C000 0x0 0x4000>;
 571                         clocks = <&clkgen JH7110_SEC_HCLK>,
 572                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 573                         clock-names = "hclk", "miscahb_clk";
 574                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 575                         interrupts = <30>;
 576                         status = "disabled";
 577                 };
 578
 579                 sec_dma: sec_dma@16008000 {
 580                         /*compatible = "arm,pl080", "arm,primecell";*/
 581                         compatible = "starfive,pl080";
 582                         reg = <0x0 0x16008000 0x0 0x4000>;
 583                         reg-names = "sec_dma";
 584                         interrupts = <29>;
 585                         clocks = <&clkgen JH7110_SEC_HCLK>,
 586                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 587                         clock-names = "sec_hclk","sec_ahb";
 588                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 589                         reset-names = "sec_hre";
 590                         lli-bus-interface-ahb1;
 591                         mem-bus-interface-ahb1;
 592                         memcpy-burst-size = <256>;
 593                         memcpy-bus-width = <32>;
 594                         #dma-cells = <2>;
 595                         status = "disabled";
 596                 };
 597
 598                 crypto: crypto@16000000 {
 599                         compatible = "starfive,jh7110-sec";
 600                         reg = <0x0 0x16000000 0x0 0x4000>,
 601                               <0x0 0x16008000 0x0 0x4000>;
 602                         reg-names = "secreg","secdma";
 603                         interrupts = <28>, <29>;
 604                         interrupt-names = "secirq", "dmairq";
 605                         clocks = <&clkgen JH7110_SEC_HCLK>,
 606                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 607                         clock-names = "sec_hclk","sec_ahb";
 608                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 609                         reset-names = "sec_hre";
 610                         enable-dma = "true";
 611                         dmas = <&sec_dma 1 2>,
 612                                <&sec_dma 0 2>;
 613                         dma-names = "sec_m","sec_p";
 614                         status = "disabled";
 615                 };
 616
 617                 i2c0: i2c@10030000 {
 618                         compatible = "snps,designware-i2c";
 619                         reg = <0x0 0x10030000 0x0 0x10000>;
 620                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 621                                  <&clkgen JH7110_I2C0_CLK_APB>;
 622                         clock-names = "ref", "pclk";
 623                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 624                         interrupts = <35>;
 625                         #address-cells = <1>;
 626                         #size-cells = <0>;
 627                         status = "disabled";
 628                 };
 629
 630                 i2c1: i2c@10040000 {
 631                         compatible = "snps,designware-i2c";
 632                         reg = <0x0 0x10040000 0x0 0x10000>;
 633                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 634                                  <&clkgen JH7110_I2C1_CLK_APB>;
 635                         clock-names = "ref", "pclk";
 636                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 637                         interrupts = <36>;
 638                         #address-cells = <1>;
 639                         #size-cells = <0>;
 640                         status = "disabled";
 641                 };
 642
 643                 i2c2: i2c@10050000 {
 644                         compatible = "snps,designware-i2c";
 645                         reg = <0x0 0x10050000 0x0 0x10000>;
 646                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 647                                  <&clkgen JH7110_I2C2_CLK_APB>;
 648                         clock-names = "ref", "pclk";
 649                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 650                         interrupts = <37>;
 651                         #address-cells = <1>;
 652                         #size-cells = <0>;
 653                         status = "disabled";
 654                 };
 655
 656                 i2c3: i2c@12030000 {
 657                         compatible = "snps,designware-i2c";
 658                         reg = <0x0 0x12030000 0x0 0x10000>;
 659                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 660                                  <&clkgen JH7110_I2C3_CLK_APB>;
 661                         clock-names = "ref", "pclk";
 662                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 663                         interrupts = <48>;
 664                         #address-cells = <1>;
 665                         #size-cells = <0>;
 666                         status = "disabled";
 667                 };
 668
 669                 i2c4: i2c@12040000 {
 670                         compatible = "snps,designware-i2c";
 671                         reg = <0x0 0x12040000 0x0 0x10000>;
 672                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 673                                  <&clkgen JH7110_I2C4_CLK_APB>;
 674                         clock-names = "ref", "pclk";
 675                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 676                         interrupts = <49>;
 677                         #address-cells = <1>;
 678                         #size-cells = <0>;
 679                         status = "disabled";
 680                 };
 681
 682                 i2c5: i2c@12050000 {
 683                         compatible = "snps,designware-i2c";
 684                         reg = <0x0 0x12050000 0x0 0x10000>;
 685                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 686                                  <&clkgen JH7110_I2C5_CLK_APB>;
 687                         clock-names = "ref", "pclk";
 688                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 689                         interrupts = <50>;
 690                         #address-cells = <1>;
 691                         #size-cells = <0>;
 692                         status = "disabled";
 693                 };
 694
 695                 i2c6: i2c@12060000 {
 696                         compatible = "snps,designware-i2c";
 697                         reg = <0x0 0x12060000 0x0 0x10000>;
 698                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 699                                  <&clkgen JH7110_I2C6_CLK_APB>;
 700                         clock-names = "ref", "pclk";
 701                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 702                         interrupts = <51>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         status = "disabled";
 706                 };
 707
 708                 /* unremovable emmc as mmcblk0 */
 709                 sdio0: sdio0@16010000 {
 710                         compatible = "snps,dw-mshc";
 711                         reg = <0x0 0x16010000 0x0 0x10000>;
 712                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 713                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 714                         clock-names = "biu","ciu";
 715                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 716                         reset-names = "reset";
 717                         interrupts = <74>;
 718                         fifo-depth = <32>;
 719                         fifo-watermark-aligned;
 720                         data-addr = <0>;
 721                         status = "disabled";
 722                 };
 723
 724                 sdio1: sdio1@16020000 {
 725                         compatible = "snps,dw-mshc";
 726                         reg = <0x0 0x16020000 0x0 0x10000>;
 727                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 728                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 729                         clock-names = "biu","ciu";
 730                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 731                         reset-names = "reset";
 732                         interrupts = <75>;
 733                         fifo-depth = <32>;
 734                         fifo-watermark-aligned;
 735                         data-addr = <0>;
 736                         status = "disabled";
 737                 };
 738
 739                 vin_sysctl: vin_sysctl@19800000 {
 740                         compatible = "starfive,stf-vin";
 741                         reg = <0x0 0x19800000 0x0 0x10000>,
 742                                 <0x0 0x19810000 0x0 0x10000>,
 743                                 <0x0 0x19820000 0x0 0x10000>,
 744                                 <0x0 0x19830000 0x0 0x10000>,
 745                                 <0x0 0x19840000 0x0 0x10000>,
 746                                 <0x0 0x19870000 0x0 0x30000>,
 747                                 <0x0 0x198a0000 0x0 0x30000>,
 748                                 <0x0 0x11840000 0x0 0x10000>,
 749                                 <0x0 0x17030000 0x0 0x10000>,
 750                                 <0x0 0x13020000 0x0 0x10000>;
 751                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
 752                                 "isp0", "isp1", "trst", "pmu", "syscrg";
 753                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 754                                  <&clkisp JH7110_U0_VIN_PCLK>,
 755                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 756                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 757                                  <&clkisp JH7110_DVP_INV>,
 758                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 759                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 760                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 761                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 762                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 763                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>;
 764                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 765                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 766                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 767                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 768                                 "clk_pixel_clk_if3";
 769                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 770                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 771                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 772                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 773                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 774                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 775                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 776                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 777                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 778                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 779                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 780                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>;
 781                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 782                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 783                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 784                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on";
 785                         interrupts = <92 87 86>;
 786                         status = "disabled";
 787                 };
 788
 789                 jpu: jpu@11900000 {
 790                         compatible = "starfive,jpu";
 791                         reg = <0x0 0x13090000 0x0 0x300>;
 792                         interrupts = <14>;
 793                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 794                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 795                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 796                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 797                         clock-names = "axi_clk", "core_clk",
 798                                       "apb_clk", "noc_bus";
 799                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 800                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 801                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 802                         reset-names = "rst_axi", "rst_core", "rst_apb";
 803                         status = "disabled";
 804                 };
 805
 806                 vpu_dec: vpu_dec@130A0000 {
 807                         compatible = "starfive,vdec";
 808                         reg = <0x0 0x130A0000 0x0 0x10000>;
 809                         interrupts = <13>;
 810                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 811                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 812                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 813                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 814                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 815                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 816                                       "apb_clk", "noc_bus";
 817                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 818                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 819                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 820                                 <&rstgen RSTN_U0_WAVE511_APB>,
 821                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 822                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 823                                       "rst_apb", "rst_sram";
 824                         starfive,vdec_noc_ctrl;
 825                         status = "disabled";
 826                 };
 827
 828                 vpu_enc: vpu_enc@130B0000 {
 829                         compatible = "starfive,venc";
 830                         reg = <0x0 0x130B0000 0x0 0x10000>;
 831                         interrupts = <15>;
 832                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 833                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 834                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 835                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 836                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 837                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 838                                       "apb_clk", "noc_bus";
 839                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 840                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 841                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 842                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 843                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 844                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 845                                       "rst_apb", "rst_sram";
 846                         starfive,venc_noc_ctrl;
 847                         status = "disabled";
 848                 };
 849
 850                 rstgen: reset-controller {
 851                         compatible = "starfive,jh7110-reset";
 852                         reg = <0x0 0x13020000 0x0 0x10000>,
 853                                 <0x0 0x10230000 0x0 0x10000>,
 854                                 <0x0 0x17000000 0x0 0x10000>,
 855                                 <0x0 0x19810000 0x0 0x10000>,
 856                                 <0x0 0x295C0000 0x0 0x10000>;
 857                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 858                         #reset-cells = <1>;
 859                         status = "okay";
 860                 };
 861
 862                 stmmac_axi_setup: stmmac-axi-config {
 863                         snps,wr_osr_lmt = <0xf>;
 864                         snps,rd_osr_lmt = <0xf>;
 865                         snps,blen = <256 128 64 32 0 0 0>;
 866                 };
 867
 868                 gmac0: ethernet@16030000 {
 869                         compatible = "starfive,jh7110-eqos-5.20";
 870                         reg = <0x0 0x16030000 0x0 0x10000>;
 871                         clock-names = "gtx",
 872                                 "tx",
 873                                 "ptp_ref",
 874                                 "stmmaceth",
 875                                 "pclk",
 876                                 "gtxc";
 877                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 878                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 879                                  <&clkgen JH7110_GMAC0_PTP>,
 880                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 881                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 882                                  <&clkgen JH7110_GMAC0_GTXC>;
 883                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 884                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 885                         reset-names = "ahb", "stmmaceth";
 886                         interrupts = <7>, <6>, <5> ;
 887                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 888                         max-frame-size = <9000>;
 889                         phy-mode = "rgmii-id";
 890                         snps,multicast-filter-bins = <64>;
 891                         snps,perfect-filter-entries = <128>;
 892                         rx-fifo-depth = <2048>;
 893                         tx-fifo-depth = <2048>;
 894                         snps,fixed-burst;
 895                         snps,no-pbl-x8;
 896                         snps,force_thresh_dma_mode;
 897                         snps,axi-config = <&stmmac_axi_setup>;
 898                         snps,tso;
 899                         snps,en-tx-lpi-clockgating;
 900                         snps,en-lpi;
 901                         snps,write-requests = <4>;
 902                         snps,read-requests = <4>;
 903                         snps,burst-map = <0x7>;
 904                         snps,txpbl = <16>;
 905                         snps,rxpbl = <16>;
 906                         status = "disabled";
 907                 };
 908
 909                 gmac1: ethernet@16040000 {
 910                         compatible = "starfive,jh7110-eqos-5.20";
 911                         reg = <0x0 0x16040000 0x0 0x10000>;
 912                         clock-names = "gtx",
 913                                 "tx",
 914                                 "ptp_ref",
 915                                 "stmmaceth",
 916                                 "pclk",
 917                                 "gtxc";
 918                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 919                                  <&clkgen JH7110_GMAC5_CLK_TX>,
 920                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
 921                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
 922                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
 923                                  <&clkgen JH7110_GMAC1_GTXC>;
 924                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
 925                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 926                         reset-names = "ahb", "stmmaceth";
 927                         interrupts = <78>, <77>, <76> ;
 928                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 929                         max-frame-size = <9000>;
 930                         phy-mode = "rgmii-id";
 931                         snps,multicast-filter-bins = <64>;
 932                         snps,perfect-filter-entries = <128>;
 933                         rx-fifo-depth = <2048>;
 934                         tx-fifo-depth = <2048>;
 935                         snps,fixed-burst;
 936                         snps,no-pbl-x8;
 937                         snps,force_thresh_dma_mode;
 938                         snps,axi-config = <&stmmac_axi_setup>;
 939                         snps,tso;
 940                         snps,en-tx-lpi-clockgating;
 941                         snps,en-lpi;
 942                         snps,write-requests = <4>;
 943                         snps,read-requests = <4>;
 944                         snps,burst-map = <0x7>;
 945                         snps,txpbl = <16>;
 946                         snps,rxpbl = <16>;
 947                         status = "disabled";
 948                 };
 949
 950                 gpu: gpu@18000000 {
 951                         compatible = "img-gpu";
 952                         reg = <0x0 0x18000000 0x0 0x100000>,
 953                                 <0x0 0x130C000 0x0 0x10000>;
 954                         clocks = <&clkgen JH7110_GPU_CLK_APB>,
 955                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
 956                                  <&clkgen JH7110_GPU_CORE_CLK>,
 957                                  <&clkgen JH7110_GPU_SYS_CLK>,
 958                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
 959                         clock-names = "clk_apb", "clk_rtc", "clk_core",
 960                                         "clk_sys", "clk_axi";
 961                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
 962                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
 963                         reset-names = "rst_apb", "rst_doma";
 964                         interrupts = <82>;
 965                         current-clock = <8000000>;
 966                         status = "disabled";
 967                 };
 968
 969                 can0: can@130d0000 {
 970                         compatible = "ipms,can";
 971                         reg = <0x0 0x130d0000 0x0 0x1000>;
 972                         interrupts = <112>;
 973                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
 974                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
 975                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
 976                         clock-names = "apb_clk", "core_clk", "timer_clk";
 977                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
 978                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
 979                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
 980                         reset-names = "rst_apb", "rst_core", "rst_timer";
 981                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
 982                         syscon,can_or_canfd = <0>;
 983                         status = "disabled";
 984                 };
 985
 986                 can1: can@130e0000 {
 987                         compatible = "ipms,can";
 988                         reg = <0x0 0x130e0000 0x0 0x1000>;
 989                         interrupts = <113>;
 990                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
 991                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
 992                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
 993                         clock-names = "apb_clk", "core_clk", "timer_clk";
 994                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
 995                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
 996                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
 997                         reset-names = "rst_apb", "rst_core", "rst_timer";
 998                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
 999                         syscon,can_or_canfd = <0>;
1000                         status = "disabled";
1001                 };
1002
1003                 tdm: tdm@10090000 {
1004                         compatible = "starfive,sf-tdm";
1005                         reg = <0x0 0x10090000 0x0 0x1000>;
1006                         reg-names = "tdm";
1007                         clocks = <&clkgen JH7110_AHB0>,
1008                                  <&clkgen JH7110_TDM_CLK_AHB>,
1009                                  <&clkgen JH7110_APB0>,
1010                                  <&clkgen JH7110_TDM_CLK_APB>,
1011                                  <&clkgen JH7110_TDM_INTERNAL>;
1012                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1013                                       "clk_apb0", "clk_tdm_apb",
1014                                       "clk_tdm_intl";
1015                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1016                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1017                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1018                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1019                         dmas = <&dma 20 1>, <&dma 21 1>;
1020                         dma-names = "rx","tx";
1021                         #sound-dai-cells = <0>;
1022                         status = "disabled";
1023                 };
1024
1025                 spdif0: spdif0@100a0000 {
1026                         compatible = "starfive,sf-spdif";
1027                         reg = <0x0 0x100a0000 0x0 0x1000>;
1028                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1029                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1030                                  <&clkgen JH7110_MCLK>;
1031                         clock-names = "spdif-apb", "spdif-core", "audioclk";
1032                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1033                         reset-names = "rst_apb";
1034                         interrupts = <84>;
1035                         interrupt-names = "tx";
1036                         #sound-dai-cells = <0>;
1037                         status = "disabled";
1038                 };
1039
1040                 pwmdac: pwmdac@100b0000 {
1041                         compatible = "starfive,pwmdac";
1042                         reg = <0x0 0x100b0000 0x0 0x1000>;
1043                         clocks = <&clkgen JH7110_APB0>,
1044                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1045                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1046                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1047                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1048                         reset-names = "rst-apb";
1049                         dmas = <&dma 22 1>;
1050                         dma-names = "tx";
1051                         #sound-dai-cells = <0>;
1052                         status = "disabled";
1053                 };
1054
1055                 i2stx: i2stx@100c0000 {
1056                         compatible = "snps,designware-i2stx";
1057                         reg = <0x0 0x100c0000 0x0 0x1000>;
1058                         interrupt-names = "tx";
1059                         #sound-dai-cells = <0>;
1060                         dmas = <&dma 28 1>;
1061                         dma-names = "rx";
1062                         status = "disabled";
1063                 };
1064
1065                 pdm: pdm@100d0000 {
1066                         compatible = "starfive,sf-pdm";
1067                         reg = <0x0 0x100d0000 0x0 0x1000>;
1068                         reg-names = "pdm";
1069                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1070                                  <&clkgen JH7110_APB0>,
1071                                  <&clkgen JH7110_PDM_CLK_APB>,
1072                                  <&clkgen JH7110_PDM_CLK_DMIC0_BCLK_SLV>,
1073                                  <&clkgen JH7110_PDM_CLK_DMIC0_LRCK_SLV>,
1074                                  <&clkgen JH7110_PDM_CLK_DMIC1_BCLK_SLV>,
1075                                  <&clkgen JH7110_PDM_CLK_DMIC1_LRCK_SLV>,
1076                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>;
1077                         clock-names = "pdm_dmic", "clk_apb0", "pdm_apb",
1078                                         "pdm_dmic0_bclk", "pdm_dmic0_lrck",
1079                                         "pdm_dmic1_bclk", "pdm_dmic1_lrck",
1080                                         "u0_i2srx_3ch_bclk";
1081                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1082                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1083                         reset-names = "pdm_dmic", "pdm_apb";
1084                         #sound-dai-cells = <0>;
1085                 };
1086
1087                 i2srx_3ch: i2srx_3ch@100e0000 {
1088                         compatible = "snps,designware-i2srx";
1089                         reg = <0x0 0x100e0000 0x0 0x1000>;
1090                         clocks = <&clkgen JH7110_APB0>,
1091                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1092                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>;
1093                         clock-names = "apb0", "3ch-apb",
1094                                         "3ch-bclk";
1095                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1096                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1097                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1098                         interrupts = <42>;
1099                         interrupt-names = "rx";
1100                         dmas = <&dma 24 1>;
1101                         dma-names = "rx";
1102                         #sound-dai-cells = <0>;
1103                         status = "disabled";
1104                 };
1105
1106                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1107                         compatible = "snps,designware-i2stx-4ch0";
1108                         reg = <0x0 0x120b0000 0x0 0x1000>;
1109                         clocks = <&clkgen JH7110_MCLK_INNER>,
1110                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1111                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1112                                  <&clkgen JH7110_MCLK>,
1113                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1114                                  <&clkgen JH7110_I2STX0_4CHLRCK>;
1115                         clock-names = "inner", "bclk-mst",
1116                                         "lrck-mst", "mclk",
1117                                         "bclk0", "lrck0";
1118                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1119                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1120                         reset-names = "rst_apb0", "rst_bclk0";
1121                         interrupts = <58>;
1122                         interrupt-names = "tx";
1123                         dmas = <&dma 47 1>;
1124                         dma-names = "tx";
1125                         #sound-dai-cells = <0>;
1126                         status = "disabled";
1127                 };
1128
1129                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1130                         compatible = "snps,designware-i2stx-4ch1";
1131                         reg = <0x0 0x120c0000 0x0 0x1000>;
1132                         clocks = <&clkgen JH7110_MCLK_INNER>,
1133                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1134                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1135                                  <&clkgen JH7110_MCLK>,
1136                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1137                                  <&clkgen JH7110_I2STX1_4CHLRCK>;
1138                         clock-names = "inner", "bclk-mst1",
1139                                         "lrck-mst1", "mclk",
1140                                         "bclk1", "lrck1";
1141                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1142                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1143                         reset-names = "rst_apb1", "rst_bclk1";
1144                         interrupts = <59>;
1145                         interrupt-names = "tx";
1146                         dmas = <&dma 48 1>;
1147                         dma-names = "tx";
1148                         #sound-dai-cells = <0>;
1149                         status = "disabled";
1150                 };
1151
1152                 ptc: pwm@120d0000 {
1153                         compatible = "starfive,pwm0";
1154                         reg = <0x0 0x120d0000 0x0 0x10000>;
1155                         reg-names = "control";
1156                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1157                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1158                         starfive,approx-period = <2000000>;
1159                         #pwm-cells=<3>;
1160                         starfive,npwm = <8>;
1161                         status = "disabled";
1162                 };
1163
1164                 spdif_transmitter: spdif_transmitter {
1165                         compatible = "linux,spdif-dit";
1166                         #sound-dai-cells = <0>;
1167                         status = "disabled";
1168                 };
1169
1170                 spdif_receiver: spdif_receiver {
1171                         compatible = "linux,spdif-dir";
1172                         #sound-dai-cells = <0>;
1173                         status = "disabled";
1174                 };
1175
1176                 pwmdac_codec: pwmdac-transmitter {
1177                         compatible = "linux,pwmdac-dit";
1178                         #sound-dai-cells = <0>;
1179                         status = "disabled";
1180                 };
1181
1182                 dmic_codec: dmic_codec {
1183                         compatible = "dmic-codec";
1184                         #sound-dai-cells = <0>;
1185                         status = "disabled";
1186                 };
1187
1188                 spi0: spi@10060000 {
1189                         compatible = "arm,pl022", "arm,primecell";
1190                         reg = <0x0 0x10060000 0x0 0x10000>;
1191                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1192                         clock-names = "apb_pclk";
1193                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1194                         reset-names = "rst_apb";
1195                         interrupts = <38>;
1196                         dmas = <&dma 14 1>, <&dma 15 1>;
1197                         dma-names = "rx","tx";
1198                         arm,primecell-periphid = <0x00041022>;
1199                         num-cs = <1>;
1200                         #address-cells = <1>;
1201                         #size-cells = <0>;
1202                         status = "disabled";
1203                 };
1204
1205                 pcie0: pcie@2B000000 {
1206                         compatible = "plda,pci-xpressrich3-axi";
1207                         #address-cells = <3>;
1208                         #size-cells = <2>;
1209                         #interrupt-cells = <1>;
1210                         reg = <0x0 0x2B000000 0x0 0x1000000
1211                                0x9 0x40000000 0x0 0x10000000>;
1212                         reg-names = "reg", "config";
1213                         device_type = "pci";
1214                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1215                         bus-range = <0x0 0xff>;
1216                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
1217                         msi-parent = <&plic>;
1218                         interrupts = <56>;
1219                         interrupt-controller;
1220                         interrupt-names = "msi";
1221                         interrupt-parent = <&plic>;
1222                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1223                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1224                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1225                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1226                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1227                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1228                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1229                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1230                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1231                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1232                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1233                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1234                                       "rst_brg", "rst_core", "rst_apb";
1235                         clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
1236                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1237                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1238                         clock-names =  "tl", "axi_mst0", "apb";
1239                         status = "disabled";
1240                 };
1241
1242                 pcie1: pcie@2C000000 {
1243                         compatible = "plda,pci-xpressrich3-axi";
1244                         #address-cells = <3>;
1245                         #size-cells = <2>;
1246                         #interrupt-cells = <1>;
1247                         reg = <0x0 0x2C000000 0x0 0x1000000
1248                                0x9 0xc0000000 0x0 0x10000000>;
1249                         reg-names = "reg", "config";
1250                         device_type = "pci";
1251                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1252                         bus-range = <0x0 0xff>;
1253                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
1254                         msi-parent = <&plic>;
1255                         interrupts = <57>;
1256                         interrupt-controller;
1257                         interrupt-names = "msi";
1258                         interrupt-parent = <&plic>;
1259                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1260                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1261                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1262                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1263                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1264                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1265                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1266                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1267                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1268                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1269                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1270                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1271                                       "rst_brg", "rst_core", "rst_apb";
1272                         clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
1273                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1274                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1275                         clock-names =  "tl", "axi_mst0", "apb";
1276                         status = "disabled";
1277                 };
1278
1279                 mailbox_contrl0: mailbox@0 {
1280                         compatible = "starfive,mail_box";
1281                         reg = <0x0 0x13060000 0x0 0x0001000>;
1282                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1283                         clock-names = "clk_apb";
1284                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1285                         reset-names = "mbx_rre";
1286                         interrupts = <26 27>;
1287                         #mbox-cells = <2>;
1288                         status = "disabled";
1289                 };
1290
1291                 mailbox_client0: mailbox_client@0 {
1292                         compatible = "starfive,mailbox-test";
1293                         mbox-names = "rx", "tx";
1294                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1295                         status = "disabled";
1296                 };
1297
1298                 display: display-subsystem {
1299                         compatible = "verisilicon,display-subsystem";
1300                         ports = <&dc_out_dpi0>;
1301                         status = "disabled";
1302                 };
1303
1304                 dssctrl: dssctrl@295B0000 {
1305                         compatible = "verisilicon,dss-ctrl", "syscon";
1306                         reg = <0 0x295B0000 0 0x90>;
1307                 };
1308
1309                 hdmi_output: hdmi-output {
1310                         compatible = "verisilicon,hdmi-encoder";
1311                         verisilicon,dss-syscon = <&dssctrl>;
1312                         verisilicon,mux-mask = <0x70 0x380>;
1313                         verisilicon,mux-val = <0x40 0x280>;
1314                         status = "disabled";
1315                 };
1316
1317                 dc8200: dc8200@29400000 {
1318                         compatible = "verisilicon,dc8200";
1319                         reg = <0x0 0x29400000 0x0 0x100>,
1320                               <0x0 0x29400800 0x0 0x2000>,
1321                               <0x0 0x17030000 0x0 0x1000>;
1322                         interrupts = <95>;
1323                         status = "disabled";
1324                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1325                                  <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1326                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1327                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1328                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1329                                  <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1330                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1331                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1332                                  <&clkgen JH7110_VOUT_SRC>,
1333                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1334                                  <&clkgen JH7110_AHB1>,
1335                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1336                                  <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1337                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1338                                  <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1339                                  <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1340                                  <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1341                                  <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1342                                  <&clkvout JH7110_U0_DC8200_CLK_AHB>;
1343                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1344                                         "noc_disp","noc_isp","noc_stg","vout_src",
1345                                         "top_vout_axi","ahb1","top_vout_ahb",
1346                                         "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1347                                         "axi_clk","core_clk","vout_ahb";
1348
1349                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1350                                  <&rstgen RSTN_U0_DC8200_AXI>,
1351                                  <&rstgen RSTN_U0_DC8200_AHB>,
1352                                  <&rstgen RSTN_U0_DC8200_CORE>,
1353                                  <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1354                                  <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1355                                  <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1356                                  <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
1357                                  <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
1358                                  <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
1359                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1360                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
1361                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
1362                                  <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
1363                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1364                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1365                                         "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
1366                                         "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
1367                 };
1368
1369                 mipi_dphy: mipi-dphy@295e0000{
1370                         compatible = "starfive,jh7100-mipi-dphy-tx";
1371                         reg = <0x0 0x295e0000 0x0 0x10000>;
1372                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1373                         clock-names = "dphy_txesc";
1374                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1375                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1376                         reset-names = "dphy_sys", "dphy_txbytehs";
1377                         #phy-cells = <0>;
1378                         status = "disabled";
1379                 };
1380
1381                  mipi_dsi: mipi@295d0000 {
1382                         compatible = "cdns,dsi";
1383                         reg = <0x0 0x295d0000 0x0 0x10000>;
1384                         reg-names = "dsi";
1385                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1386                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1387                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1388                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1389                         clock-names = "sys", "apb", "txesc", "dpi";
1390                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1391                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1392                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1393                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1394                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1395                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1396                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1397                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1398                         phys = <&mipi_dphy>;
1399                         phy-names = "dphy";
1400                         status = "disabled";
1401
1402                         port {
1403                                 dsi_out_port: endpoint {
1404                                         /*remote-endpoint = <&panel_dsi_port>;*/
1405                                 };
1406                         };
1407
1408                         mipi_panel: panel@0 {
1409                                 /*compatible = "";*/
1410                                 status = "disabled";
1411                         };
1412                 };
1413
1414                 hdmi: hdmi@29590000 {
1415                         compatible = "rockchip,rk3036-inno-hdmi";
1416                         reg = <0x0 0x29590000 0x0 0x4000>;
1417                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1418                         /*clocks = <&cru  PCLK_HDMI>;*/
1419                         /*clock-names = "pclk";*/
1420                         /*pinctrl-names = "default";*/
1421                         /*pinctrl-0 = <&hdmi_ctl>;*/
1422                         status = "disabled";
1423                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1424                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1425                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
1426                         clock-names = "sysclk", "mclk", "bclk";
1427                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1428                         reset-names = "hdmi_tx";
1429                 };
1430
1431                 sound: snd-card {
1432                         compatible = "simple-audio-card";
1433                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1434                         #address-cells = <1>;
1435                         #size-cells = <0>;
1436
1437                         simple-audio-card,dai-link@0 {
1438                                 reg = <0>;
1439                                 format = "left_j";
1440                                 bitclock-master = <&sndcpu0>;
1441                                 frame-master = <&sndcpu0>;
1442                                 status = "okay";
1443
1444                                 sndcpu0: cpu {
1445                                         sound-dai = <&pwmdac>;
1446                                 };
1447
1448                                 codec {
1449                                         sound-dai = <&pwmdac_codec>;
1450                                 };
1451                         };
1452                 };
1453
1454                 co_process: e24@0 {
1455                         compatible = "starfive,e24";
1456                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1457                                 <0x0 0xc0111000 0x0 0x0001f000>;
1458                         reg-names = "ecmd", "espace";
1459                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1460                                  <&clkgen JH7110_E2_CLK_CORE>,
1461                                  <&clkgen JH7110_E2_CLK_DBG>;
1462                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1463                         resets = <&rstgen RSTN_U0_E24_CORE>;
1464                         reset-names = "e24_core";
1465                         starfive,stg-syscon = <&stg_syscon>;
1466                         interrupt-parent = <&plic>;
1467                         firmware-name = "e24_elf";
1468                         irq-mode = <1>;
1469                         mbox-names = "tx", "rx";
1470                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1471                         #address-cells = <1>;
1472                         #size-cells = <1>;
1473                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1474                         status = "disabled";
1475                         dsp@0 {};
1476                 };
1477
1478                 xrp: xrp@0 {
1479                         compatible = "cdns,xrp";
1480                         reg = <0x0  0x10230000 0x0 0x00010000
1481                                 0x0  0x10240000 0x0 0x00010000>;
1482                         memory-region = <&xrp_reserved>;
1483                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1484                         clock-names = "core_clk";
1485                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1486                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1487                         reset-names = "rst_core","rst_axi";
1488                         firmware-name = "hifi4_elf";
1489                         #address-cells = <1>;
1490                         #size-cells = <1>;
1491                         ranges = <0x40000000 0x0 0x20000000 0x040000
1492                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1493                         status = "disabled";
1494                         dsp@0 {
1495                         };
1496                 };
1497         };
1498 };