arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110_clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13
  14 / {
  15         compatible = "starfive,jh7110";
  16         #address-cells = <2>;
  17         #size-cells = <2>;
  18
  19         cpus {
  20                 #address-cells = <1>;
  21                 #size-cells = <0>;
  22
  23                 cpu0: cpu@0 {
  24                         compatible = "sifive,u74-mc", "riscv";
  25                         reg = <0>;
  26                         d-cache-block-size = <64>;
  27                         d-cache-sets = <64>;
  28                         d-cache-size = <8192>;
  29                         d-tlb-sets = <1>;
  30                         d-tlb-size = <40>;
  31                         device_type = "cpu";
  32                         i-cache-block-size = <64>;
  33                         i-cache-sets = <64>;
  34                         i-cache-size = <16384>;
  35                         i-tlb-sets = <1>;
  36                         i-tlb-size = <40>;
  37                         mmu-type = "riscv,sv39";
  38                         next-level-cache = <&cachectrl>;
  39                         riscv,isa = "rv64imac";
  40                         tlb-split;
  41                         status = "disabled";
  42
  43                         cpu0intctrl: interrupt-controller {
  44                                 #interrupt-cells = <1>;
  45                                 compatible = "riscv,cpu-intc";
  46                                 interrupt-controller;
  47                         };
  48                 };
  49
  50                 cpu1: cpu@1 {
  51                         compatible = "sifive,u74-mc", "riscv";
  52                         reg = <1>;
  53                         d-cache-block-size = <64>;
  54                         d-cache-sets = <64>;
  55                         d-cache-size = <32768>;
  56                         d-tlb-sets = <1>;
  57                         d-tlb-size = <40>;
  58                         device_type = "cpu";
  59                         i-cache-block-size = <64>;
  60                         i-cache-sets = <64>;
  61                         i-cache-size = <32768>;
  62                         i-tlb-sets = <1>;
  63                         i-tlb-size = <40>;
  64                         mmu-type = "riscv,sv39";
  65                         next-level-cache = <&cachectrl>;
  66                         riscv,isa = "rv64imafdc";
  67                         tlb-split;
  68                         status = "okay";
  69
  70                         cpu1intctrl: interrupt-controller {
  71                                 #interrupt-cells = <1>;
  72                                 compatible = "riscv,cpu-intc";
  73                                 interrupt-controller;
  74                         };
  75                 };
  76
  77                 cpu2: cpu@2 {
  78                         compatible = "sifive,u74-mc", "riscv";
  79                         reg = <2>;
  80                         d-cache-block-size = <64>;
  81                         d-cache-sets = <64>;
  82                         d-cache-size = <32768>;
  83                         d-tlb-sets = <1>;
  84                         d-tlb-size = <40>;
  85                         device_type = "cpu";
  86                         i-cache-block-size = <64>;
  87                         i-cache-sets = <64>;
  88                         i-cache-size = <32768>;
  89                         i-tlb-sets = <1>;
  90                         i-tlb-size = <40>;
  91                         mmu-type = "riscv,sv39";
  92                         next-level-cache = <&cachectrl>;
  93                         riscv,isa = "rv64imafdc";
  94                         tlb-split;
  95                         status = "okay";
  96
  97                         cpu2intctrl: interrupt-controller {
  98                                 #interrupt-cells = <1>;
  99                                 compatible = "riscv,cpu-intc";
 100                                 interrupt-controller;
 101                         };
 102                 };
 103
 104                 cpu3: cpu@3 {
 105                         compatible = "sifive,u74-mc", "riscv";
 106                         reg = <3>;
 107                         d-cache-block-size = <64>;
 108                         d-cache-sets = <64>;
 109                         d-cache-size = <32768>;
 110                         d-tlb-sets = <1>;
 111                         d-tlb-size = <40>;
 112                         device_type = "cpu";
 113                         i-cache-block-size = <64>;
 114                         i-cache-sets = <64>;
 115                         i-cache-size = <32768>;
 116                         i-tlb-sets = <1>;
 117                         i-tlb-size = <40>;
 118                         mmu-type = "riscv,sv39";
 119                         next-level-cache = <&cachectrl>;
 120                         riscv,isa = "rv64imafdc";
 121                         tlb-split;
 122                         status = "okay";
 123
 124                         cpu3intctrl: interrupt-controller {
 125                                 #interrupt-cells = <1>;
 126                                 compatible = "riscv,cpu-intc";
 127                                 interrupt-controller;
 128                         };
 129                 };
 130
 131                 cpu4: cpu@4 {
 132                         compatible = "sifive,u74-mc", "riscv";
 133                         reg = <4>;
 134                         d-cache-block-size = <64>;
 135                         d-cache-sets = <64>;
 136                         d-cache-size = <32768>;
 137                         d-tlb-sets = <1>;
 138                         d-tlb-size = <40>;
 139                         device_type = "cpu";
 140                         i-cache-block-size = <64>;
 141                         i-cache-sets = <64>;
 142                         i-cache-size = <32768>;
 143                         i-tlb-sets = <1>;
 144                         i-tlb-size = <40>;
 145                         mmu-type = "riscv,sv39";
 146                         next-level-cache = <&cachectrl>;
 147                         riscv,isa = "rv64imafdc";
 148                         tlb-split;
 149                         status = "okay";
 150
 151                         cpu4intctrl: interrupt-controller {
 152                                 #interrupt-cells = <1>;
 153                                 compatible = "riscv,cpu-intc";
 154                                 interrupt-controller;
 155                         };
 156                 };
 157         };
 158
 159         soc: soc {
 160                 compatible = "simple-bus";
 161                 interrupt-parent = <&plic>;
 162                 #address-cells = <2>;
 163                 #size-cells = <2>;
 164                 #clock-cells = <1>;
 165                 ranges;
 166
 167                 cachectrl: cache-controller@2010000 {
 168                         compatible = "sifive,fu740-c000-ccache", "cache";
 169                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 170                         reg-names = "control", "sideband";
 171                         interrupts = <1 3 4 2>;
 172                         cache-block-size = <64>;
 173                         cache-level = <2>;
 174                         cache-sets = <2048>;
 175                         cache-size = <2097152>;
 176                         cache-unified;
 177                 };
 178
 179                 aon_syscon: aon_syscon@17010000 {
 180                         compatible = "syscon";
 181                         reg = <0x0 0x17010000 0x0 0x1000>;
 182                 };
 183
 184                 stg_syscon: stg_syscon@10240000 {
 185                         compatible = "syscon";
 186                         reg = <0x0 0x10240000 0x0 0x1000>;
 187                 };
 188
 189                 sys_syscon: sys_syscon@13030000 {
 190                         compatible = "syscon";
 191                         reg = <0x0 0x13030000 0x0 0x1000>;
 192                 };
 193
 194                 clint: clint@2000000 {
 195                         compatible = "riscv,clint0";
 196                         reg = <0x0 0x2000000 0x0 0x10000>;
 197                         reg-names = "control";
 198                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 199                                                 &cpu1intctrl 3 &cpu1intctrl 7
 200                                                 &cpu2intctrl 3 &cpu2intctrl 7
 201                                                 &cpu3intctrl 3 &cpu3intctrl 7
 202                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 203                         #interrupt-cells = <1>;
 204                 };
 205
 206                 plic: plic@c000000 {
 207                         compatible = "riscv,plic0";
 208                         reg = <0x0 0xc000000 0x0 0x4000000>;
 209                         reg-names = "control";
 210                         interrupts-extended = <&cpu0intctrl 11
 211                                                 &cpu1intctrl 11 &cpu1intctrl 9
 212                                                 &cpu2intctrl 11 &cpu2intctrl 9
 213                                                 &cpu3intctrl 11 &cpu3intctrl 9
 214                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 215                         interrupt-controller;
 216                         #interrupt-cells = <1>;
 217                         riscv,max-priority = <7>;
 218                         riscv,ndev = <136>;
 219                 };
 220
 221                 clkgen: clock-controller {
 222                         compatible = "starfive,jh7110-clkgen";
 223                         reg = <0x0 0x13020000 0x0 0x10000>,
 224                                 <0x0 0x10230000 0x0 0x10000>,
 225                                 <0x0 0x17000000 0x0 0x10000>;
 226                         reg-names = "sys", "stg", "aon";
 227                         clocks = <&osc>, <&gmac1_rmii_refin>,
 228                                 <&gmac1_rgmii_rxin>,
 229                                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 230                                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 231                                 <&tdm_ext>, <&mclk_ext>,
 232                                 <&jtag_tck_inner>, <&bist_apb>,
 233                                 <&stg_apb>, <&clk_rtc>,
 234                                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 235                         clock-names = "osc", "gmac1_rmii_refin",
 236                                 "gmac1_rgmii_rxin",
 237                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 238                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 239                                 "tdm_ext", "mclk_ext",
 240                                 "jtag_tck_inner", "bist_apb",
 241                                 "stg_apb", "clk_rtc",
 242                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 243                         #clock-cells = <1>;
 244                         status = "okay";
 245                 };
 246
 247                 clkvout: clock-controller@295C0000 {
 248                         compatible = "starfive,jh7110-clk-vout";
 249                         reg = <0x0 0x295C0000 0x0 0x10000>;
 250                         reg-names = "vout";
 251                         clocks = <&hdmitx0_pixelclk>,
 252                                 <&mipitx_dphy_rxesc>,
 253                                 <&mipitx_dphy_txbytehs>;
 254                         clock-names = "hdmitx0_pixelclk",
 255                                 "mipitx_dphy_rxesc",
 256                                 "mipitx_dphy_txbytehs";
 257                         #clock-cells = <1>;
 258                         status = "okay";
 259                 };
 260
 261                 clkisp: clock-controller@19810000 {
 262                         compatible = "starfive,jh7110-clk-isp";
 263                         reg = <0x0 0x19810000 0x0 0x10000>;
 264                         reg-names = "isp";
 265                         #clock-cells = <1>;
 266                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 267                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 268                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
 269                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 270                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 271                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi";
 272                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 273                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 274                         reset-names = "rst_isp_top_n", "rst_isp_top_axi";
 275                         status = "disabled";
 276                 };
 277
 278                 qspi: qspi@13010000 {
 279                         compatible = "cadence,qspi","cdns,qspi-nor";
 280                         #address-cells = <1>;
 281                         #size-cells = <0>;
 282                         reg = <0x0 0x13010000 0x0 0x10000
 283                                 0x0 0x21000000 0x0 0x400000>;
 284                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 285                         clock-names = "clk_ref";
 286                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 287                                         <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 288                                         <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 289                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 290                         cdns,fifo-depth = <256>;
 291                         cdns,fifo-width = <4>;
 292                         spi-max-frequency = <250000000>;
 293
 294                         nor_flash: nor-flash@0 {
 295                                 compatible = "jedec,spi-nor";
 296                                 reg=<0>;
 297                                 spi-max-frequency = <100000000>;
 298                                 cdns,tshsl-ns = <1>;
 299                                 cdns,tsd2d-ns = <1>;
 300                                 cdns,tchsh-ns = <1>;
 301                                 cdns,tslch-ns = <1>;
 302                         };
 303                 };
 304
 305                 otp: otp@17050000 {
 306                         compatible = "starfive,jh7110-otp";
 307                         reg = <0x0 0x17050000 0x0 0x10000>;
 308                         clock-frequency = <4000000>;
 309                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 310                         clock-names = "apb";
 311                 };
 312
 313                 USB30: usb@10100000 {
 314                         compatible = "cdns,usb3";
 315                         reg = <0x0 0x10100000 0x0 0x10000>,
 316                                 <0x0 0x10110000 0x0 0x10000>,
 317                                 <0x0 0x10120000 0x0 0x10000>;
 318                         reg-names = "otg", "xhci", "dev";
 319                         phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 320                         clocks = <&clkgen JH7110_USB0_CLK_APP_125>,
 321                                 <&clkgen JH7110_USB0_CLK_LPM>,
 322                                 <&clkgen JH7110_USB0_CLK_STB>,
 323                                 <&clkgen JH7110_USB0_CLK_USB_APB>,
 324                                 <&clkgen JH7110_USB0_CLK_AXI>,
 325                                 <&clkgen JH7110_USB0_CLK_UTMI_APB>;
 326                         clock-names = "app","lpm","stb","apb","axi","utmi";
 327                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 328                                         <&rstgen RSTN_U0_CDN_USB_APB>,
 329                                         <&rstgen RSTN_U0_CDN_USB_AXI>,
 330                                         <&rstgen RSTN_U0_CDN_USB_UTMI_APB>;
 331                         reset-names = "rst_pwrup","rst_apb","rst_axi","rst_utmi";
 332                 };
 333
 334                 timer: timer@13050000 {
 335                         compatible = "starfive,si5-timers";
 336                         reg = <0x0 0x13050000 0x0 0x10000>;
 337                         interrupts = <69>, <70>, <71> ,<72>;
 338                         interrupt-names = "timer0", "timer1",
 339                                           "timer2", "timer3";
 340                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 341                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 342                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 343                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 344                                  <&clkgen JH7110_TIMER_CLK_APB>;
 345                         clock-names = "timer0", "timer1",
 346                                       "timer2", "timer3", "apb_clk";
 347                         clock-frequency = <2000000>;
 348                         status = "okay";
 349                 };
 350
 351                 wdog: wdog@13070000 {
 352                         compatible = "starfive,dskit-wdt";
 353                         reg = <0x0 0x13070000 0x0 0x10000>;
 354                         interrupts = <68>;
 355                         interrupt-names = "wdog";
 356                         clock-frequency = <2000000>;
 357                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 358                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 359                         clock-names = "core_clk", "apb_clk";
 360                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 361                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 362                         reset-names = "rst_apb", "rst_core";
 363                         timeout-sec = <15>;
 364                         status = "okay";
 365                 };
 366
 367                 rtc: rtc@17040000 {
 368                         compatible = "starfive,rtc_hms";
 369                         reg = <0x0 0x17040000 0x0 0x10000>;
 370                         interrupts = <10>, <11>, <12>;
 371                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 372                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 373                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 374                         clock-names = "pclk", "cal_clk";
 375                         resets = <&rstgen RSTN_U0_RTC_HMS_APB>,
 376                                  <&rstgen RSTN_U0_RTC_HMS_CAL>,
 377                                  <&rstgen RSTN_U0_RTC_HMS_OSC32K>;
 378                         reset-names = "rst_apb", "rst_cal", "rst_osc";
 379                         rtc,cal-clock-freq = <1000000>;
 380                         status = "okay";
 381                 };
 382
 383                 pmu: pmu@17030000 {
 384                         compatible = "starfive,jh7110-pmu";
 385                         reg = <0x0 0x17030000 0x0 0x10000>;
 386                         interrupts = <111>;
 387                         status = "okay";
 388                 };
 389
 390                 uart0: serial@10000000 {
 391                         compatible = "snps,dw-apb-uart";
 392                         reg = <0x0 0x10000000 0x0 0x10000>;
 393                         reg-io-width = <4>;
 394                         reg-shift = <2>;
 395                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 396                                         <&clkgen JH7110_UART0_CLK_APB>;
 397                         clock-names = "baudclk", "apb_pclk";
 398                         resets = <&rstgen RSTN_U0_DW_UART_APB>;
 399                         interrupts = <32>;
 400                         status = "disabled";
 401                 };
 402
 403                 uart1: serial@10010000 {
 404                         compatible = "snps,dw-apb-uart";
 405                         reg = <0x0 0x10010000 0x0 0x10000>;
 406                         reg-io-width = <4>;
 407                         reg-shift = <2>;
 408                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 409                                         <&clkgen JH7110_UART1_CLK_APB>;
 410                         clock-names = "baudclk", "apb_pclk";
 411                         resets = <&rstgen RSTN_U1_DW_UART_APB>;
 412                         interrupts = <33>;
 413                         status = "disabled";
 414                 };
 415
 416                 uart2: serial@10020000 {
 417                         compatible = "snps,dw-apb-uart";
 418                         reg = <0x0 0x10020000 0x0 0x10000>;
 419                         reg-io-width = <4>;
 420                         reg-shift = <2>;
 421                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 422                                         <&clkgen JH7110_UART2_CLK_APB>;
 423                         clock-names = "baudclk", "apb_pclk";
 424                         resets = <&rstgen RSTN_U2_DW_UART_APB>;
 425                         interrupts = <34>;
 426                         status = "disabled";
 427                 };
 428
 429                 uart3: serial@12000000 {
 430                         compatible = "snps,dw-apb-uart";
 431                         reg = <0x0 0x12000000 0x0 0x10000>;
 432                         reg-io-width = <4>;
 433                         reg-shift = <2>;
 434                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 435                                         <&clkgen JH7110_UART3_CLK_APB>;
 436                         clock-names = "baudclk", "apb_pclk";
 437                         resets = <&rstgen RSTN_U3_DW_UART_APB>;
 438                         interrupts = <45>;
 439                         status = "disabled";
 440                 };
 441
 442                 uart4: serial@12010000 {
 443                         compatible = "snps,dw-apb-uart";
 444                         reg = <0x0 0x12010000 0x0 0x10000>;
 445                         reg-io-width = <4>;
 446                         reg-shift = <2>;
 447                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 448                                         <&clkgen JH7110_UART4_CLK_APB>;
 449                         clock-names = "baudclk", "apb_pclk";
 450                         resets = <&rstgen RSTN_U4_DW_UART_APB>;
 451                         interrupts = <46>;
 452                         status = "disabled";
 453                 };
 454
 455                 uart5: serial@12020000 {
 456                         compatible = "snps,dw-apb-uart";
 457                         reg = <0x0 0x12020000 0x0 0x10000>;
 458                         reg-io-width = <4>;
 459                         reg-shift = <2>;
 460                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 461                                         <&clkgen JH7110_UART5_CLK_APB>;
 462                         clock-names = "baudclk", "apb_pclk";
 463                         resets = <&rstgen RSTN_U5_DW_UART_APB>;
 464                         interrupts = <47>;
 465                         status = "disabled";
 466                 };
 467
 468                 dma: dma-controller@16050000 {
 469                         compatible = "starfive,axi-dma";
 470                         reg = <0x0 0x16050000 0x0 0x10000>;
 471                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 472                                 <&clkgen JH7110_DMA1P_CLK_AHB>;
 473                         clock-names = "core-clk", "cfgr-clk";
 474                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 475                                 <&rstgen RSTN_U0_DW_DMA1P_AHB>;
 476                         reset-names = "rst_axi",
 477                                 "rst_ahb";
 478                         interrupts = <73>;
 479                         #dma-cells = <2>;
 480                         dma-channels = <4>;
 481                         snps,dma-masters = <1>;
 482                         snps,data-width = <3>;
 483                         snps,num-hs-if = <56>;
 484                         snps,block-size = <65536 65536 65536 65536>;
 485                         snps,priority = <0 1 2 3>;
 486                         snps,axi-max-burst-len = <16>;
 487                         status = "disabled";
 488                 };
 489
 490                 gpio: gpio@13040000 {
 491                         compatible = "starfive_jh7110-sys-pinctrl";
 492                         reg = <0x0 0x13040000 0x0 0x10000>;
 493                         reg-names = "control";
 494                         interrupts = <91>;
 495                         interrupt-controller;
 496                         #gpio-cells = <2>;
 497                         ngpios = <64>;
 498                         status = "okay";
 499                 };
 500
 501                 gpioa: gpio@17020000 {
 502                         compatible = "starfive_jh7110-aon-pinctrl";
 503                         reg = <0x0 0x17020000 0x0 0x10000>;
 504                         reg-names = "control";
 505                         interrupts = <90>;
 506                         interrupt-controller;
 507                         #gpio-cells = <2>;
 508                         ngpios = <4>;
 509                         status = "okay";
 510                 };
 511
 512                 trng: trng@1600C000 {
 513                         compatible = "starfive,trng";
 514                         reg = <0x0 0x1600C000 0x0 0x4000>;
 515                         clocks = <&clkgen JH7110_SEC_HCLK>,
 516                                 <&clkgen JH7110_SEC_MISCAHB_CLK>;
 517                         clock-names = "hclk", "miscahb_clk";
 518                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 519                         interrupts = <30>;
 520                         status = "disabled";
 521                 };
 522
 523                 sec_dma: sec_dma@16008000 {
 524                         /*compatible = "arm,pl080", "arm,primecell";*/
 525                         compatible = "starfive,pl080";
 526                         reg = <0x0 0x16008000 0x0 0x4000>;
 527                         reg-names = "sec_dma";
 528                         interrupt-parent = <&plic>;
 529                         interrupts = <29>;
 530                         clocks = <&oscclk>;
 531                         clock-names = "apb_pclk";
 532                         lli-bus-interface-ahb1;
 533                         /*lli-bus-interface-ahb2;*/
 534                         mem-bus-interface-ahb1;
 535                         /*mem-bus-interface-ahb2;*/
 536                         memcpy-burst-size = <256>;
 537                         memcpy-bus-width = <32>;
 538                         #dma-cells = <2>;
 539                         /*status = "disabled";*/
 540                 };
 541
 542                 crypto: crypto@16000000 {
 543                         compatible = "starfive,jh7110-sec";
 544                         reg = <0x0 0x16000000 0x0 0x4000>,
 545                               <0x0 0x16008000 0x0 0x4000>;
 546                         reg-names = "secreg","secdma";
 547                         interrupts = <28>, <29>;
 548                         interrupt-names = "secirq",
 549                                         "dmairq";
 550                         clocks = <&clkgen JH7110_SEC_HCLK>,
 551                                         <&clkgen JH7110_SEC_MISCAHB_CLK>;
 552                         clock-names = "sec_hclk","sec_ahb";
 553                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 554                         reset-names = "sec_hre";
 555                         status = "disabled";
 556                 };
 557
 558                 i2c6: i2c@12060000 {
 559                         compatible = "snps,designware-i2c";
 560                         reg = <0x0 0x12060000 0x0 0x10000>;
 561                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 562                                  <&clkgen JH7110_I2C6_CLK_APB>;
 563                         clock-names = "ref", "pclk";
 564                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 565                         interrupts = <51>;
 566                         #address-cells = <1>;
 567                         #size-cells = <0>;
 568                         status = "disabled";
 569                 };
 570
 571                 i2c0: i2c@10030000 {
 572                         compatible = "snps,designware-i2c";
 573                         reg = <0x0 0x10030000 0x0 0x10000>;
 574                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 575                                  <&clkgen JH7110_I2C0_CLK_APB>;
 576                         clock-names = "ref", "pclk";
 577                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 578                         interrupts = <35>;
 579                         #address-cells = <1>;
 580                         #size-cells = <0>;
 581                         status = "disabled";
 582                 };
 583
 584                 i2c1: i2c@10040000 {
 585                         compatible = "snps,designware-i2c";
 586                         reg = <0x0 0x10040000 0x0 0x10000>;
 587                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 588                                  <&clkgen JH7110_I2C1_CLK_APB>;
 589                         clock-names = "ref", "pclk";
 590                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 591                         interrupts = <36>;
 592                         #address-cells = <1>;
 593                         #size-cells = <0>;
 594                         status = "disabled";
 595                 };
 596
 597                 /* unremovable emmc as mmcblk0 */
 598                 sdio0: sdio0@16010000 {
 599                         compatible = "snps,dw-mshc";
 600                         reg = <0x0 0x16010000 0x0 0x10000>;
 601                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 602                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 603                         clock-names = "biu","ciu";
 604                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 605                         reset-names = "reset";
 606                         interrupts = <74>;
 607                         fifo-depth = <32>;
 608                         fifo-watermark-aligned;
 609                         data-addr = <0>;
 610                         status = "disabled";
 611                 };
 612
 613                 sdio1: sdio1@16020000 {
 614                         compatible = "snps,dw-mshc";
 615                         reg = <0x0 0x16020000 0x0 0x10000>;
 616                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 617                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 618                         clock-names = "biu","ciu";
 619                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 620                         reset-names = "reset";
 621                         interrupts = <75>;
 622                         fifo-depth = <32>;
 623                         fifo-watermark-aligned;
 624                         data-addr = <0>;
 625                         status = "disabled";
 626                 };
 627
 628                 vin_sysctl: vin_sysctl@19800000 {
 629                         compatible = "starfive,stf-vin";
 630                         reg = <0x0 0x19800000 0x0 0x10000>,
 631                                 <0x0 0x19810000 0x0 0x10000>,
 632                                 <0x0 0x19820000 0x0 0x10000>,
 633                                 <0x0 0x19830000 0x0 0x10000>,
 634                                 <0x0 0x19840000 0x0 0x10000>,
 635                                 <0x0 0x19870000 0x0 0x30000>,
 636                                 <0x0 0x198a0000 0x0 0x30000>,
 637                                 <0x0 0x11840000 0x0 0x10000>,
 638                                 <0x0 0x17030000 0x0 0x10000>,
 639                                 <0x0 0x13020000 0x0 0x10000>;
 640                         reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
 641                                 "isp0", "isp1", "trst", "pmu", "syscrg";
 642                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 643                                 <&clkisp JH7110_U0_VIN_PCLK>,
 644                                 <&clkisp JH7110_U0_VIN_SYS_CLK>,
 645                                 <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 646                                 <&clkisp JH7110_DVP_INV>,
 647                                 <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 648                                 <&clkisp JH7110_MIPI_RX0_PXL>,
 649                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 650                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 651                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 652                                 <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>;
 653                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 654                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 655                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 656                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 657                                 "clk_pixel_clk_if3";
 658                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 659                                 <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 660                                 <&rstgen RSTN_U0_VIN_N_PCLK>,
 661                                 <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 662                                 <&rstgen RSTN_U0_VIN_P_AXIRD>,
 663                                 <&rstgen RSTN_U0_VIN_P_AXIWR>,
 664                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 665                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 666                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 667                                 <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>;
 668                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 669                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 670                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3";
 671                         interrupts = <92 87 86>;
 672                         status = "disabled";
 673                 };
 674
 675                 jpu: jpu@11900000 {
 676                         compatible = "starfive,jpu";
 677                         reg = <0x0 0x13090000 0x0 0x300>;
 678                         interrupts = <14>;
 679                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 680                                 <&clkgen JH7110_CODAJ12_CLK_CORE>,
 681                                 <&clkgen JH7110_CODAJ12_CLK_APB>;
 682                         clock-names = "axi_clk", "core_clk", "apb_clk";
 683                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 684                                 <&rstgen RSTN_U0_CODAJ12_CORE>,
 685                                 <&rstgen RSTN_U0_CODAJ12_APB>;
 686                         reset-names = "rst_axi", "rst_core", "rst_apb";
 687                         status = "disabled";
 688                 };
 689
 690                 vpu_dec: vpu_dec@130A0000 {
 691                         compatible = "starfive,vdec";
 692                         reg = <0x0 0x130A0000 0x0 0x10000>;
 693                         interrupts = <13>;
 694                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 695                                 <&clkgen JH7110_WAVE511_CLK_BPU>,
 696                                 <&clkgen JH7110_WAVE511_CLK_VCE>,
 697                                 <&clkgen JH7110_WAVE511_CLK_APB>,
 698                                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 699                         clock-names = "axi_clk",
 700                                 "bpu_clk",
 701                                 "vce_clk",
 702                                 "apb_clk",
 703                                 "noc_bus";
 704                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 705                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 706                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 707                                 <&rstgen RSTN_U0_WAVE511_APB>,
 708                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 709                         reset-names = "rst_axi",
 710                                 "rst_bpu",
 711                                 "rst_vce",
 712                                 "rst_apb",
 713                                 "rst_sram";
 714                         starfive,vdec_noc_ctrl;
 715                         status = "disabled";
 716                 };
 717
 718                 vpu_enc: vpu_enc@130B0000 {
 719                         compatible = "starfive,venc";
 720                         reg = <0x0 0x130B0000 0x0 0x10000>;
 721                         interrupts = <15>;
 722                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 723                                 <&clkgen JH7110_WAVE420L_CLK_BPU>,
 724                                 <&clkgen JH7110_WAVE420L_CLK_VCE>,
 725                                 <&clkgen JH7110_WAVE420L_CLK_APB>,
 726                                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 727                         clock-names = "axi_clk",
 728                                 "bpu_clk",
 729                                 "vce_clk",
 730                                 "apb_clk",
 731                                 "noc_bus";
 732                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 733                                 <&rstgen RSTN_U0_WAVE420L_BPU>,
 734                                 <&rstgen RSTN_U0_WAVE420L_VCE>,
 735                                 <&rstgen RSTN_U0_WAVE420L_APB>,
 736                                 <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 737                         reset-names = "rst_axi",
 738                                 "rst_bpu",
 739                                 "rst_vce",
 740                                 "rst_apb",
 741                                 "rst_sram";
 742                         starfive,venc_noc_ctrl;
 743                         status = "disabled";
 744                 };
 745
 746                 rstgen: reset-controller {
 747                         compatible = "starfive,jh7110-reset";
 748                         reg = <0x0 0x13020000 0x0 0x10000>,
 749                                 <0x0 0x10230000 0x0 0x10000>,
 750                                 <0x0 0x17000000 0x0 0x10000>,
 751                                 <0x0 0x19810000 0x0 0x10000>,
 752                                 <0x0 0x295C0000 0x0 0x10000>;
 753                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 754                         #reset-cells = <1>;
 755                         status = "okay";
 756                 };
 757
 758                 stmmac_axi_setup: stmmac-axi-config {
 759                         snps,wr_osr_lmt = <0xf>;
 760                         snps,rd_osr_lmt = <0xf>;
 761                         snps,blen = <256 128 64 32 0 0 0>;
 762                 };
 763
 764                 gmac0: ethernet@16030000 {
 765                         compatible = "starfive,jh7110-eqos-5.20";
 766                         reg = <0x0 0x16030000 0x0 0x10000>;
 767                         clock-names = "gtx",
 768                                 "tx",
 769                                 "ptp_ref",
 770                                 "stmmaceth",
 771                                 "pclk";
 772                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 773                                 <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 774                                 <&clkgen JH7110_GMAC0_PTP>,
 775                                 <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 776                                 <&clkgen JH7110_U0_GMAC5_CLK_AXI>;
 777                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 778                                         <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 779                         reset-names = "ahb", "stmmaceth";
 780                         interrupts = <7>, <6>, <5> ;
 781                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 782                         max-frame-size = <9000>;
 783                         phy-mode = "rgmii-id";
 784                         snps,multicast-filter-bins = <256>;
 785                         snps,perfect-filter-entries = <128>;
 786                         rx-fifo-depth = <262144>;
 787                         tx-fifo-depth = <131072>;
 788                         snps,fixed-burst;
 789                         snps,no-pbl-x8;
 790                         snps,force_thresh_dma_mode;
 791                         snps,axi-config = <&stmmac_axi_setup>;
 792                         snps,tso;
 793                         snps,en-tx-lpi-clockgating;
 794                         snps,en-lpi;
 795                         snps,write-requests = <2>;
 796                         snps,read-requests = <16>;
 797                         snps,burst-map = <0x7>;
 798                         snps,txpbl = <16>;
 799                         snps,rxpbl = <16>;
 800                         status = "disabled";
 801                 };
 802
 803                 gmac1: ethernet@16040000 {
 804                         compatible = "starfive,jh7110-eqos-5.20";
 805                         reg = <0x0 0x16040000 0x0 0x10000>;
 806                         clock-names = "gtx",
 807                                 "tx",
 808                                 "ptp_ref",
 809                                 "stmmaceth",
 810                                 "pclk";
 811                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
 812                                 <&clkgen JH7110_GMAC5_CLK_TX>,
 813                                 <&clkgen JH7110_GMAC5_CLK_PTP>,
 814                                 <&clkgen JH7110_GMAC5_CLK_AHB>,
 815                                 <&clkgen JH7110_GMAC5_CLK_AXI>;
 816                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
 817                                         <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
 818                         reset-names = "ahb", "stmmaceth";
 819                         interrupts = <78>, <77>, <76> ;
 820                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 821                         max-frame-size = <9000>;
 822                         phy-mode = "rgmii-id";
 823                         snps,multicast-filter-bins = <256>;
 824                         snps,perfect-filter-entries = <128>;
 825                         rx-fifo-depth = <262144>;
 826                         tx-fifo-depth = <131072>;
 827                         snps,fixed-burst;
 828                         snps,no-pbl-x8;
 829                         snps,force_thresh_dma_mode;
 830                         snps,axi-config = <&stmmac_axi_setup>;
 831                         snps,tso;
 832                         snps,en-tx-lpi-clockgating;
 833                         snps,en-lpi;
 834                         snps,write-requests = <2>;
 835                         snps,read-requests = <16>;
 836                         snps,burst-map = <0x7>;
 837                         snps,txpbl = <16>;
 838                         snps,rxpbl = <16>;
 839                         status = "disabled";
 840                 };
 841
 842                 gpu: gpu@18000000 {
 843                         compatible = "img-gpu";
 844                         reg = <0x0 0x18000000 0x0 0x100000 0x0 0x130C000 0x0 0x10000>;
 845                         clocks = <&gpu_core_clk>, <&gpu_sys_clk>;
 846                         clock-names = "gpu_core_clk","gpu_sys_clk";
 847                         interrupts = <82>;
 848                         current-clock = <8000000>;
 849                         status = "disabled";
 850                 };
 851
 852                 can0: can@130d0000 {
 853                         compatible = "ipms,can";
 854                         reg = <0x0 0x130d0000 0x0 0x1000>;
 855                         interrupts = <112>;
 856                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
 857                                 <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
 858                                 <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
 859                         clock-names = "apb_clk",
 860                                         "core_clk",
 861                                         "timer_clk";
 862                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
 863                                 <&rstgen RSTN_U0_CAN_CTRL_CORE>,
 864                                 <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
 865                         reset-names = "rst_apb",
 866                                         "rst_core",
 867                                         "rst_timer";
 868                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
 869                         syscon,can_or_canfd = <0>;
 870                         status = "disabled";
 871                 };
 872
 873                 can1: can@130e0000 {
 874                         compatible = "ipms,can";
 875                         reg = <0x0 0x130e0000 0x0 0x1000>;
 876                         interrupts = <113>;
 877                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
 878                                 <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
 879                                 <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
 880                         clock-names = "apb_clk",
 881                                         "core_clk",
 882                                         "timer_clk";
 883                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
 884                                 <&rstgen RSTN_U1_CAN_CTRL_CORE>,
 885                                 <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
 886                         reset-names = "rst_apb",
 887                                         "rst_core",
 888                                         "rst_timer";
 889                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
 890                         syscon,can_or_canfd = <0>;
 891                         status = "disabled";
 892                 };
 893
 894                 tdm: tdm@10090000 {
 895                         compatible = "starfive,tdm";
 896                         reg = <0x0 0x10090000 0x0 0x1000>;
 897                         reg-names = "tdm";
 898                         clocks = <&audioclk>;
 899                         clock-names = "audioclk";
 900                         dmas = <&dma 20 1>, <&dma 21 1>;
 901                         dma-names = "rx","tx";
 902                         #sound-dai-cells = <0>;
 903                         status = "disabled";
 904                 };
 905
 906                 spdif0: spdif0@100a0000 {
 907                         compatible = "starfive,sf-spdif";
 908                         reg = <0x0 0x100a0000 0x0 0x1000>;
 909                         clocks = <&audioclk>;
 910                         clock-names = "audioclk";
 911                         interrupts = <84>;
 912                         interrupt-names = "tx";
 913                         #sound-dai-cells = <0>;
 914                         status = "disabled";
 915                 };
 916
 917                 pwmdac: pwmdac@100b0000 {
 918                         compatible = "sf,pwmdac";
 919                         reg = <0x0 0x100b0000 0x0 0x1000>;
 920                         clocks = <&apb0clk>;
 921                         dmas = <&dma 22 1>;
 922                         dma-names = "tx";
 923                         #sound-dai-cells = <0>;
 924                         status = "disabled";
 925                 };
 926
 927                 i2stx: i2stx@100c0000 {
 928                         compatible = "snps,designware-i2stx";
 929                         reg = <0x0 0x100c0000 0x0 0x1000>;
 930                         clocks = <&apb0clk>;
 931                         clock-names = "i2sclk";
 932                         interrupt-names = "tx";
 933                         #sound-dai-cells = <0>;
 934                         dmas = <&dma 28 1>;
 935                         dma-names = "rx";
 936                         status = "disabled";
 937                 };
 938
 939                 pdm: pdm@100d0000 {
 940                         compatible = "starfive,sf-pdm";
 941                         reg = <0x0 0x100d0000 0x0 0x1000>;
 942                         reg-names = "pdm";
 943                         clocks = <&audioclk>;
 944                         clock-names = "audioclk";
 945                         #sound-dai-cells = <0>;
 946                         status = "disabled";
 947                 };
 948
 949                 i2srx_3ch: i2srx-3ch@100e0000 {
 950                         compatible = "snps,designware-i2srx";
 951                         reg = <0x0 0x100e0000 0x0 0x1000>;
 952                         clocks = <&apb0clk>;
 953                         clock-names = "i2sclk";
 954                         interrupts = <42>;
 955                         interrupt-names = "rx";
 956                         #sound-dai-cells = <0>;
 957                         status = "disabled";
 958                 };
 959
 960                 i2stx_4ch0: i2stx-4ch0@120b0000 {
 961                         compatible = "snps,designware-i2stx-4ch0";
 962                         reg = <0x0 0x120b0000 0x0 0x1000>;
 963                         clocks = <&apb0clk>;
 964                         clock-names = "i2sclk";
 965                         interrupts = <58>;
 966                         interrupt-names = "tx";
 967                         #sound-dai-cells = <0>;
 968                         status = "disabled";
 969                 };
 970
 971                 i2stx_4ch1: i2sdac1@120c0000 {
 972                         compatible = "snps,designware-i2stx-4ch1";
 973                         reg = <0x0 0x120c0000 0x0 0x1000>;
 974                         clocks = <&apb0clk>;
 975                         clock-names = "i2sclk";
 976                         interrupts = <59>;
 977                         interrupt-names = "tx";
 978                         #sound-dai-cells = <0>;
 979                         status = "disabled";
 980                 };
 981
 982                 ptc: pwm@120d0000 {
 983                         compatible = "starfive,pwm0";
 984                         reg = <0x0 0x120d0000 0x0 0x10000>;
 985                         reg-names = "control";
 986                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
 987                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
 988                         starfive,approx-period = <2000000>;
 989                         #pwm-cells=<3>;
 990                         starfive,npwm = <8>;
 991                         status = "disabled";
 992                 };
 993
 994                 spdif_transmitter: spdif_transmitter {
 995                         compatible = "linux,spdif-dit";
 996                         #sound-dai-cells = <0>;
 997                         status = "disabled";
 998                 };
 999
1000                 spdif_receiver: spdif_receiver {
1001                         compatible = "linux,spdif-dir";
1002                         #sound-dai-cells = <0>;
1003                         status = "disabled";
1004                 };
1005
1006                 pwmdac_codec: pwmdac-transmitter {
1007                         compatible = "linux,pwmdac-dit";
1008                         #sound-dai-cells = <0>;
1009                         status = "disabled";
1010                 };
1011
1012                 dmic_codec: dmic_codec {
1013                         compatible = "dmic-codec";
1014                         #sound-dai-cells = <0>;
1015                         status = "disabled";
1016                 };
1017
1018                 spi0: spi0@10060000 {
1019                         compatible = "arm,pl022", "arm,primecell";
1020                         reg = <0x0 0x10060000 0x0 0x10000>;
1021                         clocks = <&ahb1clk>;
1022                         clock-names = "apb_pclk";
1023                         interrupts = <38>;
1024                         dmas = <&dma 14 1>, <&dma 15 1>;
1025                         dma-names = "rx","tx";
1026                         arm,primecell-periphid = <0x00041022>;
1027                         num-cs = <1>;
1028                         #address-cells = <1>;
1029                         #size-cells = <0>;
1030                         status = "disabled";
1031                 };
1032
1033                 pcie0: pcie0@2B000000 {
1034                         compatible = "plda,pci-xpressrich3-axi";
1035                         reg = <0x0 0x2B000000 0x0 0x1000000
1036                                0x9 0x40000000 0x0 0x10000000>;
1037                         reg-names = "reg", "config";
1038                         interrupts = <56>;
1039                         interrupt-controller;
1040                         interrupt-names = "msi";
1041                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1042                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1043                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1044                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1045                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1046                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1047                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1048                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1049                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1050                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1051                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1052                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1053                                       "rst_brg", "rst_core", "rst_apb";
1054                         clocks = <&clkgen JH7110_PCIE0_CLK_TL>,
1055                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1056                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1057                         clock-names =  "tl", "axi_mst0", "apb";
1058                         #interrupt-cells = <1>;
1059                         device_type = "pci";
1060                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130>;
1061                         bus-range = <0x0 0xff>;
1062                         msi-parent = <&plic>;
1063                         #address-cells = <3>;
1064                         #size-cells = <2>;
1065                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x06000000>;
1066                         status = "disabled";
1067                 };
1068
1069                 pcie1:pcie1@2C000000 {
1070                         compatible = "plda,pci-xpressrich3-axi";
1071                         reg = <0x0 0x2C000000 0x0 0x1000000
1072                                0x9 0xc0000000 0x0 0x10000000>;
1073                         reg-names = "reg", "config";
1074                         device_type = "pci";
1075                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0>;
1076                         bus-range = <0x0 0xff>;
1077                         #address-cells = <3>;
1078                         #size-cells = <2>;
1079                         #interrupt-cells = <1>;
1080                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x06000000>;
1081                         msi-parent = <&plic>;
1082                         interrupts = <57>;
1083                         interrupt-controller;
1084                         interrupt-names = "msi";
1085                         interrupt-parent = <&plic>;
1086                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1087                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1088                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1089                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1090                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1091                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1092                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1093                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1094                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1095                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1096                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1097                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1098                                       "rst_brg", "rst_core", "rst_apb";
1099                         clocks = <&clkgen JH7110_PCIE1_CLK_TL>,
1100                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1101                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1102                         clock-names =  "tl", "axi_mst0", "apb";
1103                         status = "disabled";
1104                 };
1105
1106                 mailbox_contrl0: mailbox@0 {
1107                         compatible = "starfive,mail_box";
1108                         reg = <0x0 0x13060000 0x0 0x0001000>;
1109                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1110                         clock-names = "clk_apb";
1111                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1112                         reset-names = "mbx_rre";
1113                         interrupts = <26 27>;
1114                         #mbox-cells = <2>;
1115                         status = "disabled";
1116                 };
1117
1118                 mailbox_client0: mailbox_client@0 {
1119                         compatible = "starfive,mailbox-test";
1120                         mbox-names = "rx", "tx";
1121                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1122                         status = "disabled";
1123                 };
1124
1125                 display: display-subsystem {
1126                         compatible = "verisilicon,display-subsystem";
1127                         ports = <&dc_out_dpi0>;
1128                         status = "disabled";
1129                 };
1130
1131                 dssctrl: dssctrl@295B0000 {
1132                         compatible = "verisilicon,dss-ctrl", "syscon";
1133                         reg = <0 0x295B0000 0 0x90>;
1134                 };
1135
1136                 hdmi_output: hdmi-output {
1137                         compatible = "verisilicon,hdmi-encoder";
1138                         verisilicon,dss-syscon = <&dssctrl>;
1139                         verisilicon,mux-mask = <0x70 0x380>;
1140                         verisilicon,mux-val = <0x40 0x280>;
1141                         status = "disabled";
1142                 };
1143
1144                 dc8200: dc8200@29400000 {
1145                         compatible = "verisilicon,dc8200";
1146                         reg = <0x0 0x29400000 0x0 0x100>,
1147                               <0x0 0x29400800 0x0 0x2000>,
1148                               <0x0 0x17030000 0x0 0x1000>;
1149                         interrupts = <95>;
1150                         status = "disabled";
1151                         clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
1152                                 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
1153                                 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
1154                                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
1155                                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
1156                                 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1157                                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
1158                                 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1159                                 <&clkgen JH7110_VOUT_SRC>,
1160                                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1161                                 <&clkgen JH7110_AHB1>,
1162                                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1163                                 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
1164                                 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1165
1166                                 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1167                                 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1168                                 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1169                                 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1170                                 <&clkvout JH7110_U0_DC8200_CLK_AHB>;
1171                         clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
1172                                                   "noc_disp","noc_isp","noc_stg","vout_src",
1173                                                   "top_vout_axi","ahb1","top_vout_ahb",
1174                                                   "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1",
1175                                                   "axi_clk","core_clk","vout_ahb";
1176
1177                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1178                                 <&rstgen RSTN_U0_DC8200_AXI>,
1179                                 <&rstgen RSTN_U0_DC8200_AHB>,
1180                                 <&rstgen RSTN_U0_DC8200_CORE>,
1181                                 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
1182                                 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
1183                                 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
1184                                 <&rstgen RSTN_U0_NOC_BUS_GPU_AXI_N>,
1185                                 <&rstgen RSTN_U0_NOC_BUS_VDEC_AXI_N>,
1186                                 <&rstgen RSTN_U0_JTAG2APB_PRESETN>,
1187                                 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
1188                                 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>,
1189                                 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>,
1190                                 <&rstgen RSTN_U0_NOC_BUS_DDRC_N>;
1191                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1192                                         "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
1193                                         "rst_noc_gpu","rst_noc_vdec","rst_jtag2apb",
1194                                         "rst_noc_disp","rst_noc_isp","rst_noc_stg","rst_noc_ddrc";
1195
1196
1197                 };
1198
1199                 mipi_dphy: mipi-dphy@295e0000{
1200                         compatible = "starfive,jh7100-mipi-dphy-tx";
1201                         reg = <0x0 0x295e0000 0x0 0x10000>;
1202                         /*clocks = <&uartclk>, <&apb2clk>;*/
1203                         /*clock-names = "baudclk", "apb_pclk";*/
1204                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1205                         clock-names = "dphy_txesc";
1206                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1207                                         <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1208                         reset-names = "dphy_sys",
1209                                                 "dphy_txbytehs";
1210                         #phy-cells = <0>;
1211                         status = "disabled";
1212                 };
1213
1214                  mipi_dsi: mipi@295d0000 {
1215                         compatible = "cdns,dsi";
1216                         reg = <0x0 0x295d0000 0x0 0x10000>;
1217                         reg-names = "dsi";
1218                         /*clocks = <&apb1clk>, <&apb2clk>;*/
1219                         /*clock-names = "dsi_p_clk", "dsi_sys_clk";*/
1220                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1221                                         <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1222                                         <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1223                                         <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1224                         clock-names = "sys",
1225                                                 "apb",
1226                                                 "txesc",
1227                                                 "dpi";
1228                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1229                                         <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1230                                         <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1231                                         <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1232                                         <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1233                                         <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1234                         reset-names = "dsi_dpi",
1235                                                 "dsi_apb",
1236                                                 "dsi_rxesc",
1237                                                 "dsi_sys",
1238                                                 "dsi_txbytehs",
1239                                                 "dsi_txesc";
1240                         phys = <&mipi_dphy>;
1241                         phy-names = "dphy";
1242                         status = "disabled";
1243
1244                         port {
1245                                 dsi_out_port: endpoint {
1246                                         /*remote-endpoint = <&panel_dsi_port>;*/
1247                                 };
1248                         };
1249
1250                         mipi_panel: panel@0 {
1251                                 /*compatible = "";*/
1252                                 status = "disabled";
1253                         };
1254                 };
1255
1256                 hdmi: hdmi@29590000 {
1257                         compatible = "rockchip,rk3036-inno-hdmi";
1258                         reg = <0x29590000 0x4000>;
1259                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1260                         /*clocks = <&cru  PCLK_HDMI>;*/
1261                         /*clock-names = "pclk";*/
1262                         /*pinctrl-names = "default";*/
1263                         /*pinctrl-0 = <&hdmi_ctl>;*/
1264                         status = "disabled";
1265                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1266                                         <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1267                                         <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>;
1268                         clock-names = "sysclk",
1269                                                 "mclk",
1270                                                 "bclk";
1271                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1272                         reset-names = "hdmi_tx";
1273
1274                         hdmi_in: port {
1275                                         #address-cells = <1>;
1276                                         #size-cells = <0>;
1277                                         hdmi_in_lcdc: endpoint@0 {
1278                                                         reg = <0>;
1279                                                         remote-endpoint = <&dc_out_dpi0>;
1280                                         };
1281                         };
1282                 };
1283
1284                 sound_pwmdac: snd-card_pwmdac {
1285                         compatible = "simple-audio-card";
1286                         simple-audio-card,name = "Starfive-Pwmdac-Sound-Card";
1287                         simple-audio-card,bitclock-master = <&pwmdac_dailink_master>;
1288                         simple-audio-card,frame-master = <&pwmdac_dailink_master>;
1289                         simple-audio-card,format = "left_j";
1290                         status = "disabled";
1291
1292                         pwmdac_dailink_master: simple-audio-card,cpu {
1293                                 sound-dai = <&pwmdac>;
1294                         };
1295
1296                         simple-audio-card,codec {
1297                                 sound-dai = <&pwmdac_codec>;
1298                         };
1299                 };
1300
1301                 co_process: e24@0 {
1302                         compatible = "starfive,e24";
1303                         reg = <0x0 0xc0110000 0x0 0x00001000
1304                         0x0 0xc0111000 0x0 0x0001f000>;
1305                         reg-names = "ecmd","espace";
1306                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1307                                 <&clkgen JH7110_E2_CLK_CORE>,
1308                                 <&clkgen JH7110_E2_CLK_DBG>;
1309                         clock-names = "clk_rtc","clk_core","clk_dbg";
1310                         resets = <&rstgen RSTN_U0_E24_CORE>;
1311                         reset-names = "e24_core";
1312                         starfive,stg-syscon = <&stg_syscon>;
1313                         interrupt-parent = <&plic>;
1314                         firmware-name = "e24_elf";
1315                         irq-mode = <1>;
1316                         mbox-names = "tx", "rx";
1317                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1318                         #address-cells = <1>;
1319                         #size-cells = <1>;
1320                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1321                         status = "disabled";
1322                         dsp@0 {};
1323                 };
1324         };
1325 };