arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <800000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <800000>;
  30                         };
  31                         opp-750000000 {
  32                                         opp-hz = /bits/ 64 <750000000>;
  33                                         opp-microvolt = <800000>;
  34                         };
  35                         opp-1500000000 {
  36                                         opp-hz = /bits/ 64 <1500000000>;
  37                                         opp-microvolt = <1040000>;
  38                         };
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 cpu0: cpu@0 {
  46                         compatible = "sifive,u74-mc", "riscv";
  47                         reg = <0>;
  48                         d-cache-block-size = <64>;
  49                         d-cache-sets = <64>;
  50                         d-cache-size = <8192>;
  51                         d-tlb-sets = <1>;
  52                         d-tlb-size = <40>;
  53                         device_type = "cpu";
  54                         i-cache-block-size = <64>;
  55                         i-cache-sets = <64>;
  56                         i-cache-size = <16384>;
  57                         i-tlb-sets = <1>;
  58                         i-tlb-size = <40>;
  59                         mmu-type = "riscv,sv39";
  60                         next-level-cache = <&cachectrl>;
  61                         riscv,isa = "rv64imac";
  62                         tlb-split;
  63                         status = "disabled";
  64
  65                         cpu0intctrl: interrupt-controller {
  66                                 #interrupt-cells = <1>;
  67                                 compatible = "riscv,cpu-intc";
  68                                 interrupt-controller;
  69                         };
  70                 };
  71
  72                 cpu1: cpu@1 {
  73                         compatible = "sifive,u74-mc", "riscv";
  74                         reg = <1>;
  75                         d-cache-block-size = <64>;
  76                         d-cache-sets = <64>;
  77                         d-cache-size = <32768>;
  78                         d-tlb-sets = <1>;
  79                         d-tlb-size = <40>;
  80                         device_type = "cpu";
  81                         i-cache-block-size = <64>;
  82                         i-cache-sets = <64>;
  83                         i-cache-size = <32768>;
  84                         i-tlb-sets = <1>;
  85                         i-tlb-size = <40>;
  86                         mmu-type = "riscv,sv39";
  87                         next-level-cache = <&cachectrl>;
  88                         riscv,isa = "rv64imafdc";
  89                         tlb-split;
  90                         status = "okay";
  91                         operating-points-v2 = <&cluster0_opp>;
  92
  93                         cpu1intctrl: interrupt-controller {
  94                                 #interrupt-cells = <1>;
  95                                 compatible = "riscv,cpu-intc";
  96                                 interrupt-controller;
  97                         };
  98                 };
  99
 100                 cpu2: cpu@2 {
 101                         compatible = "sifive,u74-mc", "riscv";
 102                         reg = <2>;
 103                         d-cache-block-size = <64>;
 104                         d-cache-sets = <64>;
 105                         d-cache-size = <32768>;
 106                         d-tlb-sets = <1>;
 107                         d-tlb-size = <40>;
 108                         device_type = "cpu";
 109                         i-cache-block-size = <64>;
 110                         i-cache-sets = <64>;
 111                         i-cache-size = <32768>;
 112                         i-tlb-sets = <1>;
 113                         i-tlb-size = <40>;
 114                         mmu-type = "riscv,sv39";
 115                         next-level-cache = <&cachectrl>;
 116                         riscv,isa = "rv64imafdc";
 117                         tlb-split;
 118                         status = "okay";
 119                         operating-points-v2 = <&cluster0_opp>;
 120
 121                         cpu2intctrl: interrupt-controller {
 122                                 #interrupt-cells = <1>;
 123                                 compatible = "riscv,cpu-intc";
 124                                 interrupt-controller;
 125                         };
 126                 };
 127
 128                 cpu3: cpu@3 {
 129                         compatible = "sifive,u74-mc", "riscv";
 130                         reg = <3>;
 131                         d-cache-block-size = <64>;
 132                         d-cache-sets = <64>;
 133                         d-cache-size = <32768>;
 134                         d-tlb-sets = <1>;
 135                         d-tlb-size = <40>;
 136                         device_type = "cpu";
 137                         i-cache-block-size = <64>;
 138                         i-cache-sets = <64>;
 139                         i-cache-size = <32768>;
 140                         i-tlb-sets = <1>;
 141                         i-tlb-size = <40>;
 142                         mmu-type = "riscv,sv39";
 143                         next-level-cache = <&cachectrl>;
 144                         riscv,isa = "rv64imafdc";
 145                         tlb-split;
 146                         status = "okay";
 147                         operating-points-v2 = <&cluster0_opp>;
 148
 149                         cpu3intctrl: interrupt-controller {
 150                                 #interrupt-cells = <1>;
 151                                 compatible = "riscv,cpu-intc";
 152                                 interrupt-controller;
 153                         };
 154                 };
 155
 156                 cpu4: cpu@4 {
 157                         compatible = "sifive,u74-mc", "riscv";
 158                         reg = <4>;
 159                         d-cache-block-size = <64>;
 160                         d-cache-sets = <64>;
 161                         d-cache-size = <32768>;
 162                         d-tlb-sets = <1>;
 163                         d-tlb-size = <40>;
 164                         device_type = "cpu";
 165                         i-cache-block-size = <64>;
 166                         i-cache-sets = <64>;
 167                         i-cache-size = <32768>;
 168                         i-tlb-sets = <1>;
 169                         i-tlb-size = <40>;
 170                         mmu-type = "riscv,sv39";
 171                         next-level-cache = <&cachectrl>;
 172                         riscv,isa = "rv64imafdc";
 173                         tlb-split;
 174                         status = "okay";
 175                         operating-points-v2 = <&cluster0_opp>;
 176
 177                         cpu4intctrl: interrupt-controller {
 178                                 #interrupt-cells = <1>;
 179                                 compatible = "riscv,cpu-intc";
 180                                 interrupt-controller;
 181                         };
 182                 };
 183         };
 184
 185         soc: soc {
 186                 compatible = "simple-bus";
 187                 interrupt-parent = <&plic>;
 188                 #address-cells = <2>;
 189                 #size-cells = <2>;
 190                 #clock-cells = <1>;
 191                 ranges;
 192
 193                 cachectrl: cache-controller@2010000 {
 194                         compatible = "sifive,fu740-c000-ccache", "cache";
 195                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 196                         reg-names = "control", "sideband";
 197                         interrupts = <1 3 4 2>;
 198                         cache-block-size = <64>;
 199                         cache-level = <2>;
 200                         cache-sets = <2048>;
 201                         cache-size = <2097152>;
 202                         cache-unified;
 203                 };
 204
 205                 aon_syscon: aon_syscon@17010000 {
 206                         compatible = "syscon";
 207                         reg = <0x0 0x17010000 0x0 0x1000>;
 208                 };
 209
 210                 stg_syscon: stg_syscon@10240000 {
 211                         compatible = "syscon";
 212                         reg = <0x0 0x10240000 0x0 0x1000>;
 213                 };
 214
 215                 sys_syscon: sys_syscon@13030000 {
 216                         compatible = "syscon";
 217                         reg = <0x0 0x13030000 0x0 0x1000>;
 218                 };
 219
 220                 clint: clint@2000000 {
 221                         compatible = "riscv,clint0";
 222                         reg = <0x0 0x2000000 0x0 0x10000>;
 223                         reg-names = "control";
 224                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 225                                                 &cpu1intctrl 3 &cpu1intctrl 7
 226                                                 &cpu2intctrl 3 &cpu2intctrl 7
 227                                                 &cpu3intctrl 3 &cpu3intctrl 7
 228                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 229                         #interrupt-cells = <1>;
 230                 };
 231
 232                 plic: plic@c000000 {
 233                         compatible = "riscv,plic0";
 234                         reg = <0x0 0xc000000 0x0 0x4000000>;
 235                         reg-names = "control";
 236                         interrupts-extended = <&cpu0intctrl 11
 237                                                 &cpu1intctrl 11 &cpu1intctrl 9
 238                                                 &cpu2intctrl 11 &cpu2intctrl 9
 239                                                 &cpu3intctrl 11 &cpu3intctrl 9
 240                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 241                         interrupt-controller;
 242                         #interrupt-cells = <1>;
 243                         riscv,max-priority = <7>;
 244                         riscv,ndev = <136>;
 245                 };
 246
 247                 clkgen: clock-controller {
 248                         compatible = "starfive,jh7110-clkgen";
 249                         reg = <0x0 0x13020000 0x0 0x10000>,
 250                                 <0x0 0x10230000 0x0 0x10000>,
 251                                 <0x0 0x17000000 0x0 0x10000>;
 252                         reg-names = "sys", "stg", "aon";
 253                         clocks = <&osc>, <&gmac1_rmii_refin>,
 254                                  <&gmac1_rgmii_rxin>,
 255                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 256                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 257                                  <&tdm_ext>, <&mclk_ext>,
 258                                  <&jtag_tck_inner>, <&bist_apb>,
 259                                  <&clk_rtc>,
 260                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 261                         clock-names = "osc", "gmac1_rmii_refin",
 262                                 "gmac1_rgmii_rxin",
 263                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 264                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 265                                 "tdm_ext", "mclk_ext",
 266                                 "jtag_tck_inner", "bist_apb",
 267                                 "clk_rtc",
 268                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 269                         #clock-cells = <1>;
 270                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 271                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 272                         status = "okay";
 273                 };
 274
 275                 clkvout: clock-controller@295C0000 {
 276                         compatible = "starfive,jh7110-clk-vout";
 277                         reg = <0x0 0x295C0000 0x0 0x10000>;
 278                         reg-names = "vout";
 279                         clocks = <&hdmitx0_pixelclk>,
 280                                  <&mipitx_dphy_rxesc>,
 281                                  <&mipitx_dphy_txbytehs>,
 282                                  <&clkgen JH7110_VOUT_SRC>,
 283                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 284                         clock-names = "hdmitx0_pixelclk",
 285                                       "mipitx_dphy_rxesc",
 286                                       "mipitx_dphy_txbytehs",
 287                                       "vout_src",
 288                                       "vout_top_ahb";
 289                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 290                         reset-names = "vout_src";
 291                         #clock-cells = <1>;
 292                         power-domains = <&pwrc JH7110_PD_VOUT>;
 293                         status = "okay";
 294                 };
 295
 296                 clkisp: clock-controller@19810000 {
 297                         compatible = "starfive,jh7110-clk-isp";
 298                         reg = <0x0 0x19810000 0x0 0x10000>;
 299                         reg-names = "isp";
 300                         #clock-cells = <1>;
 301                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 302                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 303                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 304                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 305                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 306                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 307                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 308                                       "u0_sft7110_noc_bus_clk_isp_axi";
 309                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 310                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 311                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 312                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 313                                       "rst_isp_noc_bus_n";
 314                         power-domains = <&pwrc JH7110_PD_ISP>;
 315                         status = "okay";
 316                 };
 317
 318                 qspi: spi@13010000 {
 319                         compatible = "cdns,qspi-nor";
 320                         #address-cells = <1>;
 321                         #size-cells = <0>;
 322                         reg = <0x0 0x13010000 0x0 0x10000
 323                                 0x0 0x21000000 0x0 0x400000>;
 324                         interrupts = <25>;
 325                         clocks = <&clkgen JH7110_QSPI_CLK_REF>,
 326                                  <&clkgen JH7110_QSPI_CLK_APB>,
 327                                  <&clkgen JH7110_AHB1>,
 328                                  <&clkgen JH7110_QSPI_CLK_AHB>;
 329                         clock-names = "clk_ref",
 330                                       "clk_apb",
 331                                       "ahb1",
 332                                       "clk_ahb";
 333                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 334                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 335                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 336                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 337                         cdns,fifo-depth = <256>;
 338                         cdns,fifo-width = <4>;
 339                         cdns,trigger-address = <0x0>;
 340                         spi-max-frequency = <250000000>;
 341
 342                         nor_flash: nor-flash@0 {
 343                                 compatible = "jedec,spi-nor";
 344                                 reg=<0>;
 345                                 cdns,read-delay = <5>;
 346                                 spi-max-frequency = <100000000>;
 347                                 cdns,tshsl-ns = <1>;
 348                                 cdns,tsd2d-ns = <1>;
 349                                 cdns,tchsh-ns = <1>;
 350                                 cdns,tslch-ns = <1>;
 351
 352                                 partitions {
 353                                         compatible = "fixed-partitions";
 354                                         #address-cells = <1>;
 355                                         #size-cells = <1>;
 356
 357                                         spl@0 {
 358                                                 reg = <0x0 0x20000>;
 359                                         };
 360                                         uboot@100000 {
 361                                                 reg = <0x100000 0x300000>;
 362                                         };
 363                                         data@f00000 {
 364                                                 reg = <0xf00000 0x100000>;
 365                                         };
 366                                 };
 367                         };
 368                 };
 369
 370                 otp: otp@17050000 {
 371                         compatible = "starfive,jh7110-otp";
 372                         reg = <0x0 0x17050000 0x0 0x10000>;
 373                         clock-frequency = <4000000>;
 374                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 375                         clock-names = "apb";
 376                 };
 377
 378                 usbdrd30: usbdrd{
 379                         compatible = "starfive,jh7110-cdns3";
 380                         reg = <0x0 0x10210000 0x0 0x1000>,
 381                               <0x0 0x10200000 0x0 0x1000>;
 382                         clocks = <&clkgen JH7110_USB_125M>,
 383                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 384                                  <&clkgen JH7110_USB0_CLK_LPM>,
 385                                  <&clkgen JH7110_USB0_CLK_STB>,
 386                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 387                                  <&clkgen JH7110_USB0_CLK_AXI>,
 388                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 389                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 390                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 391                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 392                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 393                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 394                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 395                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 396                         reset-names = "pwrup","apb","axi","utmi", "phy";
 397                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 398                         starfive,sys-syscon = <&sys_syscon 0x18>;
 399                         status = "disabled";
 400                         #address-cells = <2>;
 401                         #size-cells = <2>;
 402                         #interrupt-cells = <1>;
 403                         ranges;
 404                         usbdrd_cdns3: usb@10100000 {
 405                                 compatible = "cdns,usb3";
 406                                 reg = <0x0 0x10100000 0x0 0x10000>,
 407                                       <0x0 0x10110000 0x0 0x10000>,
 408                                       <0x0 0x10120000 0x0 0x10000>;
 409                                 reg-names = "otg", "xhci", "dev";
 410                                 interrupts = <100>, <108>, <110>;
 411                                 interrupt-names = "host", "peripheral", "otg";
 412                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 413                                 maximum-speed = "super-speed";
 414                         };
 415                 };
 416
 417                 timer: timer@13050000 {
 418                         compatible = "starfive,jh7110-timers";
 419                         reg = <0x0 0x13050000 0x0 0x10000>;
 420                         interrupts = <69>, <70>, <71> ,<72>;
 421                         interrupt-names = "timer0", "timer1",
 422                                           "timer2", "timer3";
 423                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 424                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 425                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 426                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 427                                  <&clkgen JH7110_TIMER_CLK_APB>;
 428                         clock-names = "timer0", "timer1",
 429                                       "timer2", "timer3", "apb_clk";
 430                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 431                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 432                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 433                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 434                                  <&rstgen RSTN_U0_TIMER_APB>;
 435                         reset-names = "timer0", "timer1",
 436                                       "timer2", "timer3", "apb_rst";
 437                         clock-frequency = <24000000>;
 438                         status = "okay";
 439                 };
 440
 441                 wdog: wdog@13070000 {
 442                         compatible = "starfive,jh7110-wdt";
 443                         reg = <0x0 0x13070000 0x0 0x10000>;
 444                         interrupts = <68>;
 445                         interrupt-names = "wdog";
 446                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 447                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 448                         clock-names = "core_clk", "apb_clk";
 449                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 450                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 451                         reset-names = "rst_apb", "rst_core";
 452                         timeout-sec = <15>;
 453                         status = "okay";
 454                 };
 455
 456                 rtc: rtc@17040000 {
 457                         compatible = "starfive,jh7110-rtc";
 458                         reg = <0x0 0x17040000 0x0 0x10000>;
 459                         interrupts = <10>, <11>, <12>;
 460                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 461                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 462                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 463                         clock-names = "pclk", "cal_clk";
 464                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 465                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 466                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 467                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 468                         rtc,cal-clock-freq = <1000000>;
 469                         status = "okay";
 470                 };
 471
 472                 pwrc: power-controller@17030000 {
 473                         compatible = "starfive,jh7110-pmu";
 474                         reg = <0x0 0x17030000 0x0 0x10000>;
 475                         interrupts = <111>;
 476                         #power-domain-cells = <1>;
 477                         status = "okay";
 478                 };
 479
 480                 uart0: serial@10000000 {
 481                         compatible = "snps,dw-apb-uart";
 482                         reg = <0x0 0x10000000 0x0 0x10000>;
 483                         reg-io-width = <4>;
 484                         reg-shift = <2>;
 485                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 486                                  <&clkgen JH7110_UART0_CLK_APB>;
 487                         clock-names = "baudclk", "apb_pclk";
 488                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 489                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 490                         interrupts = <32>;
 491                         status = "disabled";
 492                 };
 493
 494                 uart1: serial@10010000 {
 495                         compatible = "snps,dw-apb-uart";
 496                         reg = <0x0 0x10010000 0x0 0x10000>;
 497                         reg-io-width = <4>;
 498                         reg-shift = <2>;
 499                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 500                                  <&clkgen JH7110_UART1_CLK_APB>;
 501                         clock-names = "baudclk", "apb_pclk";
 502                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 503                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 504                         interrupts = <33>;
 505                         status = "disabled";
 506                 };
 507
 508                 uart2: serial@10020000 {
 509                         compatible = "snps,dw-apb-uart";
 510                         reg = <0x0 0x10020000 0x0 0x10000>;
 511                         reg-io-width = <4>;
 512                         reg-shift = <2>;
 513                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 514                                  <&clkgen JH7110_UART2_CLK_APB>;
 515                         clock-names = "baudclk", "apb_pclk";
 516                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 517                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 518                         interrupts = <34>;
 519                         status = "disabled";
 520                 };
 521
 522                 uart3: serial@12000000 {
 523                         compatible = "snps,dw-apb-uart";
 524                         reg = <0x0 0x12000000 0x0 0x10000>;
 525                         reg-io-width = <4>;
 526                         reg-shift = <2>;
 527                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 528                                  <&clkgen JH7110_UART3_CLK_APB>;
 529                         clock-names = "baudclk", "apb_pclk";
 530                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 531                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 532                         interrupts = <45>;
 533                         status = "disabled";
 534                 };
 535
 536                 uart4: serial@12010000 {
 537                         compatible = "snps,dw-apb-uart";
 538                         reg = <0x0 0x12010000 0x0 0x10000>;
 539                         reg-io-width = <4>;
 540                         reg-shift = <2>;
 541                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 542                                  <&clkgen JH7110_UART4_CLK_APB>;
 543                         clock-names = "baudclk", "apb_pclk";
 544                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 545                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 546                         interrupts = <46>;
 547                         status = "disabled";
 548                 };
 549
 550                 uart5: serial@12020000 {
 551                         compatible = "snps,dw-apb-uart";
 552                         reg = <0x0 0x12020000 0x0 0x10000>;
 553                         reg-io-width = <4>;
 554                         reg-shift = <2>;
 555                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 556                                  <&clkgen JH7110_UART5_CLK_APB>;
 557                         clock-names = "baudclk", "apb_pclk";
 558                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 559                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 560                         interrupts = <47>;
 561                         status = "disabled";
 562                 };
 563
 564                 dma: dma-controller@16050000 {
 565                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 566                         reg = <0x0 0x16050000 0x0 0x10000>;
 567                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 568                                  <&clkgen JH7110_DMA1P_CLK_AHB>,
 569                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
 570                         clock-names = "core-clk", "cfgr-clk", "stg_clk";
 571                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 572                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>,
 573                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
 574                         reset-names = "rst_axi", "rst_ahb", "rst_stg";
 575                         interrupts = <73>;
 576                         #dma-cells = <2>;
 577                         dma-channels = <4>;
 578                         snps,dma-masters = <1>;
 579                         snps,data-width = <3>;
 580                         snps,num-hs-if = <56>;
 581                         snps,block-size = <65536 65536 65536 65536>;
 582                         snps,priority = <0 1 2 3>;
 583                         snps,axi-max-burst-len = <16>;
 584                         status = "disabled";
 585                 };
 586
 587                 gpio: gpio@13040000 {
 588                         compatible = "starfive,jh7110-sys-pinctrl";
 589                         reg = <0x0 0x13040000 0x0 0x10000>;
 590                         reg-names = "control";
 591                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 592                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 593                         interrupts = <86>;
 594                         interrupt-controller;
 595                         #gpio-cells = <2>;
 596                         ngpios = <64>;
 597                         status = "okay";
 598                 };
 599
 600                 gpioa: gpio@17020000 {
 601                         compatible = "starfive,jh7110-aon-pinctrl";
 602                         reg = <0x0 0x17020000 0x0 0x10000>;
 603                         reg-names = "control";
 604                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 605                         interrupts = <85>;
 606                         interrupt-controller;
 607                         #gpio-cells = <2>;
 608                         ngpios = <4>;
 609                         status = "okay";
 610                 };
 611
 612                 sfctemp: tmon@120e0000  {
 613                         compatible = "starfive,jh7110-temp";
 614                         reg = <0x0 0x120e0000 0x0 0x10000>;
 615                         interrupts = <81>;
 616                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 617                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 618                         clock-names = "sense", "bus";
 619                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 620                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 621                         reset-names = "sense", "bus";
 622                         #thermal-sensor-cells = <0>;
 623                         status = "disabled";
 624                 };
 625
 626                 thermal-zones {
 627                         cpu-thermal {
 628                                 polling-delay-passive = <250>;
 629                                 polling-delay = <15000>;
 630
 631                                 thermal-sensors = <&sfctemp>;
 632
 633                                 cooling-maps {
 634                                 };
 635
 636                                 trips {
 637                                         cpu_alert0: cpu_alert0 {
 638                                                 /* milliCelsius */
 639                                                 temperature = <75000>;
 640                                                 hysteresis = <2000>;
 641                                                 type = "passive";
 642                                         };
 643
 644                                         cpu_crit: cpu_crit {
 645                                                 /* milliCelsius */
 646                                                 temperature = <90000>;
 647                                                 hysteresis = <2000>;
 648                                                 type = "critical";
 649                                         };
 650                                 };
 651                         };
 652                 };
 653
 654                 trng: trng@1600C000 {
 655                         compatible = "starfive,jh7110-trng";
 656                         reg = <0x0 0x1600C000 0x0 0x4000>;
 657                         clocks = <&clkgen JH7110_SEC_HCLK>,
 658                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 659                         clock-names = "hclk", "miscahb_clk";
 660                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 661                         interrupts = <30>;
 662                         status = "disabled";
 663                 };
 664
 665                 sec_dma: sec_dma@16008000 {
 666                         compatible = "arm,pl080", "arm,primecell";
 667                         arm,primecell-periphid = <0x00041080>;
 668                         reg = <0x0 0x16008000 0x0 0x4000>;
 669                         reg-names = "sec_dma";
 670                         interrupts = <29>;
 671                         clocks = <&clkgen JH7110_SEC_HCLK>,
 672                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 673                         clock-names = "sec_hclk","apb_pclk";
 674                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 675                         reset-names = "sec_hre";
 676                         lli-bus-interface-ahb1;
 677                         mem-bus-interface-ahb1;
 678                         memcpy-burst-size = <256>;
 679                         memcpy-bus-width = <32>;
 680                         #dma-cells = <2>;
 681                         status = "disabled";
 682                 };
 683
 684                 crypto: crypto@16000000 {
 685                         compatible = "starfive,jh7110-sec";
 686                         reg = <0x0 0x16000000 0x0 0x4000>,
 687                               <0x0 0x16008000 0x0 0x4000>;
 688                         reg-names = "secreg","secdma";
 689                         interrupts = <28>, <29>;
 690                         interrupt-names = "secirq", "dmairq";
 691                         clocks = <&clkgen JH7110_SEC_HCLK>,
 692                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 693                         clock-names = "sec_hclk","sec_ahb";
 694                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 695                         reset-names = "sec_hre";
 696                         enable-side-channel-mitigation = "true";
 697                         enable-dma = "true";
 698                         dmas = <&sec_dma 1 2>,
 699                                <&sec_dma 0 2>;
 700                         dma-names = "sec_m","sec_p";
 701                         status = "disabled";
 702                 };
 703
 704                 i2c0: i2c@10030000 {
 705                         compatible = "snps,designware-i2c";
 706                         reg = <0x0 0x10030000 0x0 0x10000>;
 707                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 708                                  <&clkgen JH7110_I2C0_CLK_APB>;
 709                         clock-names = "ref", "pclk";
 710                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 711                         interrupts = <35>;
 712                         #address-cells = <1>;
 713                         #size-cells = <0>;
 714                         status = "disabled";
 715                 };
 716
 717                 i2c1: i2c@10040000 {
 718                         compatible = "snps,designware-i2c";
 719                         reg = <0x0 0x10040000 0x0 0x10000>;
 720                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 721                                  <&clkgen JH7110_I2C1_CLK_APB>;
 722                         clock-names = "ref", "pclk";
 723                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 724                         interrupts = <36>;
 725                         #address-cells = <1>;
 726                         #size-cells = <0>;
 727                         status = "disabled";
 728                 };
 729
 730                 i2c2: i2c@10050000 {
 731                         compatible = "snps,designware-i2c";
 732                         reg = <0x0 0x10050000 0x0 0x10000>;
 733                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 734                                  <&clkgen JH7110_I2C2_CLK_APB>;
 735                         clock-names = "ref", "pclk";
 736                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 737                         interrupts = <37>;
 738                         #address-cells = <1>;
 739                         #size-cells = <0>;
 740                         status = "disabled";
 741                 };
 742
 743                 i2c3: i2c@12030000 {
 744                         compatible = "snps,designware-i2c";
 745                         reg = <0x0 0x12030000 0x0 0x10000>;
 746                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 747                                  <&clkgen JH7110_I2C3_CLK_APB>;
 748                         clock-names = "ref", "pclk";
 749                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 750                         interrupts = <48>;
 751                         #address-cells = <1>;
 752                         #size-cells = <0>;
 753                         status = "disabled";
 754                 };
 755
 756                 i2c4: i2c@12040000 {
 757                         compatible = "snps,designware-i2c";
 758                         reg = <0x0 0x12040000 0x0 0x10000>;
 759                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 760                                  <&clkgen JH7110_I2C4_CLK_APB>;
 761                         clock-names = "ref", "pclk";
 762                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 763                         interrupts = <49>;
 764                         #address-cells = <1>;
 765                         #size-cells = <0>;
 766                         status = "disabled";
 767                 };
 768
 769                 i2c5: i2c@12050000 {
 770                         compatible = "snps,designware-i2c";
 771                         reg = <0x0 0x12050000 0x0 0x10000>;
 772                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 773                                  <&clkgen JH7110_I2C5_CLK_APB>;
 774                         clock-names = "ref", "pclk";
 775                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 776                         interrupts = <50>;
 777                         #address-cells = <1>;
 778                         #size-cells = <0>;
 779                         status = "disabled";
 780                 };
 781
 782                 i2c6: i2c@12060000 {
 783                         compatible = "snps,designware-i2c";
 784                         reg = <0x0 0x12060000 0x0 0x10000>;
 785                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 786                                  <&clkgen JH7110_I2C6_CLK_APB>;
 787                         clock-names = "ref", "pclk";
 788                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 789                         interrupts = <51>;
 790                         #address-cells = <1>;
 791                         #size-cells = <0>;
 792                         status = "disabled";
 793                 };
 794
 795                 /* unremovable emmc as mmcblk0 */
 796                 sdio0: sdio0@16010000 {
 797                         compatible = "starfive,jh7110-sdio";
 798                         reg = <0x0 0x16010000 0x0 0x10000>;
 799                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 800                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 801                         clock-names = "biu","ciu";
 802                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 803                         reset-names = "reset";
 804                         interrupts = <74>;
 805                         fifo-depth = <32>;
 806                         fifo-watermark-aligned;
 807                         data-addr = <0>;
 808                         starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
 809                         status = "disabled";
 810                 };
 811
 812                 sdio1: sdio1@16020000 {
 813                         compatible = "starfive,jh7110-sdio";
 814                         reg = <0x0 0x16020000 0x0 0x10000>;
 815                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 816                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 817                         clock-names = "biu","ciu";
 818                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 819                         reset-names = "reset";
 820                         interrupts = <75>;
 821                         fifo-depth = <32>;
 822                         fifo-watermark-aligned;
 823                         data-addr = <0>;
 824                         starfive,sys-syscon = <&sys_syscon 0x9c 0x1 0x3e>;
 825                         status = "disabled";
 826                 };
 827
 828                 vin_sysctl: vin_sysctl@19800000 {
 829                         compatible = "starfive,jh7110-vin";
 830                         reg = <0x0 0x19800000 0x0 0x10000>,
 831                                 <0x0 0x19810000 0x0 0x10000>,
 832                                 <0x0 0x19820000 0x0 0x10000>,
 833                                 <0x0 0x19840000 0x0 0x10000>,
 834                                 <0x0 0x19870000 0x0 0x30000>,
 835                                 <0x0 0x11840000 0x0 0x10000>,
 836                                 <0x0 0x17030000 0x0 0x10000>,
 837                                 <0x0 0x13020000 0x0 0x10000>;
 838                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 839                                 "isp", "trst", "pmu", "syscrg";
 840                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 841                                  <&clkisp JH7110_U0_VIN_PCLK>,
 842                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 843                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 844                                  <&clkisp JH7110_DVP_INV>,
 845                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 846                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 847                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 848                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 849                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 850                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 851                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 852                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 853                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 854                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 855                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
 856                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 857                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 858                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 859                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 860                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 861                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 862                                 "clk_ispcore_2x", "clk_isp_axi";
 863                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 864                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 865                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 866                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 867                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 868                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 869                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 870                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 871                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 872                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 873                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 874                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 875                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 876                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 877                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 878                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 879                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 880                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 881                                 "rst_isp_top_n", "rst_isp_top_axi";
 882                         starfive,aon-syscon = <&aon_syscon 0x00>;
 883                         power-domains = <&pwrc JH7110_PD_ISP>;
 884                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 885                         interrupts = <92 87 88 89 90>;
 886                         status = "disabled";
 887                 };
 888
 889                 jpu: jpu@11900000 {
 890                         compatible = "starfive,jpu";
 891                         reg = <0x0 0x13090000 0x0 0x300>;
 892                         interrupts = <14>;
 893                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 894                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 895                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 896                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 897                         clock-names = "axi_clk", "core_clk",
 898                                       "apb_clk", "noc_bus";
 899                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 900                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 901                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 902                         reset-names = "rst_axi", "rst_core", "rst_apb";
 903                         power-domains = <&pwrc JH7110_PD_VDEC>;
 904                         status = "disabled";
 905                 };
 906
 907                 vpu_dec: vpu_dec@130A0000 {
 908                         compatible = "starfive,vdec";
 909                         reg = <0x0 0x130A0000 0x0 0x10000>;
 910                         interrupts = <13>;
 911                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 912                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 913                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 914                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 915                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 916                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 917                                       "apb_clk", "noc_bus";
 918                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 919                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 920                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 921                                 <&rstgen RSTN_U0_WAVE511_APB>,
 922                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 923                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 924                                       "rst_apb", "rst_sram";
 925                         starfive,vdec_noc_ctrl;
 926                         power-domains = <&pwrc JH7110_PD_VDEC>;
 927                         status = "disabled";
 928                 };
 929
 930                 vpu_enc: vpu_enc@130B0000 {
 931                         compatible = "starfive,venc";
 932                         reg = <0x0 0x130B0000 0x0 0x10000>;
 933                         interrupts = <15>;
 934                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 935                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 936                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 937                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 938                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 939                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 940                                       "apb_clk", "noc_bus";
 941                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 942                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 943                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 944                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 945                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 946                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 947                                       "rst_apb", "rst_sram";
 948                         starfive,venc_noc_ctrl;
 949                         power-domains = <&pwrc JH7110_PD_VENC>;
 950                         status = "disabled";
 951                 };
 952
 953                 rstgen: reset-controller {
 954                         compatible = "starfive,jh7110-reset";
 955                         reg = <0x0 0x13020000 0x0 0x10000>,
 956                                 <0x0 0x10230000 0x0 0x10000>,
 957                                 <0x0 0x17000000 0x0 0x10000>,
 958                                 <0x0 0x19810000 0x0 0x10000>,
 959                                 <0x0 0x295C0000 0x0 0x10000>;
 960                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 961                         #reset-cells = <1>;
 962                         status = "okay";
 963                 };
 964
 965                 stmmac_axi_setup: stmmac-axi-config {
 966                         snps,wr_osr_lmt = <0xf>;
 967                         snps,rd_osr_lmt = <0xf>;
 968                         snps,blen = <256 128 64 32 0 0 0>;
 969                 };
 970
 971                 gmac0: ethernet@16030000 {
 972                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
 973                         reg = <0x0 0x16030000 0x0 0x10000>;
 974                         clock-names = "gtx",
 975                                 "tx",
 976                                 "ptp_ref",
 977                                 "stmmaceth",
 978                                 "pclk",
 979                                 "gtxc";
 980                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 981                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 982                                  <&clkgen JH7110_GMAC0_PTP>,
 983                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 984                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 985                                  <&clkgen JH7110_GMAC0_GTXC>;
 986                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 987                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 988                         reset-names = "ahb", "stmmaceth";
 989                         interrupts = <7>, <6>, <5> ;
 990                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 991                         max-frame-size = <9000>;
 992                         phy-mode = "rgmii-id";
 993                         snps,multicast-filter-bins = <64>;
 994                         snps,perfect-filter-entries = <128>;
 995                         rx-fifo-depth = <2048>;
 996                         tx-fifo-depth = <2048>;
 997                         snps,fixed-burst;
 998                         snps,no-pbl-x8;
 999                         snps,force_thresh_dma_mode;
1000                         snps,axi-config = <&stmmac_axi_setup>;
1001                         snps,tso;
1002                         snps,en-tx-lpi-clockgating;
1003                         snps,en-lpi;
1004                         snps,write-requests = <4>;
1005                         snps,read-requests = <4>;
1006                         snps,burst-map = <0x7>;
1007                         snps,txpbl = <16>;
1008                         snps,rxpbl = <16>;
1009                         status = "disabled";
1010                 };
1011
1012                 gmac1: ethernet@16040000 {
1013                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
1014                         reg = <0x0 0x16040000 0x0 0x10000>;
1015                         clock-names = "gtx",
1016                                 "tx",
1017                                 "ptp_ref",
1018                                 "stmmaceth",
1019                                 "pclk",
1020                                 "gtxc";
1021                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1022                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1023                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1024                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1025                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1026                                  <&clkgen JH7110_GMAC1_GTXC>;
1027                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1028                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1029                         reset-names = "ahb", "stmmaceth";
1030                         interrupts = <78>, <77>, <76> ;
1031                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1032                         max-frame-size = <9000>;
1033                         phy-mode = "rgmii-id";
1034                         snps,multicast-filter-bins = <64>;
1035                         snps,perfect-filter-entries = <128>;
1036                         rx-fifo-depth = <2048>;
1037                         tx-fifo-depth = <2048>;
1038                         snps,fixed-burst;
1039                         snps,no-pbl-x8;
1040                         snps,force_thresh_dma_mode;
1041                         snps,axi-config = <&stmmac_axi_setup>;
1042                         snps,tso;
1043                         snps,en-tx-lpi-clockgating;
1044                         snps,en-lpi;
1045                         snps,write-requests = <4>;
1046                         snps,read-requests = <4>;
1047                         snps,burst-map = <0x7>;
1048                         snps,txpbl = <16>;
1049                         snps,rxpbl = <16>;
1050                         status = "disabled";
1051                 };
1052
1053                 gpu: gpu@18000000 {
1054                         compatible = "img-gpu";
1055                         reg = <0x0 0x18000000 0x0 0x100000>,
1056                                 <0x0 0x130C000 0x0 0x10000>;
1057                         clocks = <&clkgen JH7110_GPU_CORE>,
1058                                  <&clkgen JH7110_GPU_CLK_APB>,
1059                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1060                                  <&clkgen JH7110_GPU_CORE_CLK>,
1061                                  <&clkgen JH7110_GPU_SYS_CLK>,
1062                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1063                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1064                                         "clk_core", "clk_sys", "clk_axi";
1065                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1066                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1067                         reset-names = "rst_apb", "rst_doma";
1068                         power-domains = <&pwrc JH7110_PD_GPUA>;
1069                         interrupts = <82>;
1070                         current-clock = <8000000>;
1071                         status = "disabled";
1072                 };
1073
1074                 can0: can@130d0000 {
1075                         compatible = "starfive,jh7110-can", "ipms,can";
1076                         reg = <0x0 0x130d0000 0x0 0x1000>;
1077                         interrupts = <112>;
1078                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1079                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1080                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1081                         clock-names = "apb_clk", "core_clk", "timer_clk";
1082                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1083                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1084                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1085                         reset-names = "rst_apb", "rst_core", "rst_timer";
1086                         frequency = <40000000>;
1087                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1088                         syscon,can_or_canfd = <0>;
1089                         status = "disabled";
1090                 };
1091
1092                 can1: can@130e0000 {
1093                         compatible = "starfive,jh7110-can", "ipms,can";
1094                         reg = <0x0 0x130e0000 0x0 0x1000>;
1095                         interrupts = <113>;
1096                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1097                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1098                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1099                         clock-names = "apb_clk", "core_clk", "timer_clk";
1100                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1101                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1102                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1103                         reset-names = "rst_apb", "rst_core", "rst_timer";
1104                         frequency = <40000000>;
1105                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1106                         syscon,can_or_canfd = <1>;
1107                         status = "disabled";
1108                 };
1109
1110                 tdm: tdm@10090000 {
1111                         compatible = "starfive,jh7110-tdm";
1112                         reg = <0x0 0x10090000 0x0 0x1000>;
1113                         reg-names = "tdm";
1114                         clocks = <&clkgen JH7110_AHB0>,
1115                                  <&clkgen JH7110_TDM_CLK_AHB>,
1116                                  <&clkgen JH7110_APB0>,
1117                                  <&clkgen JH7110_TDM_CLK_APB>,
1118                                  <&clkgen JH7110_TDM_INTERNAL>,
1119                                  <&tdm_ext>,
1120                                  <&clkgen JH7110_TDM_CLK_TDM>,
1121                                  <&clkgen JH7110_MCLK_INNER>;
1122                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1123                                       "clk_apb0", "clk_tdm_apb",
1124                                       "clk_tdm_internal", "clk_tdm_ext",
1125                                       "clk_tdm", "mclk_inner";
1126                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1127                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1128                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1129                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1130                         dmas = <&dma 20 1>, <&dma 21 1>;
1131                         dma-names = "rx","tx";
1132                         #sound-dai-cells = <0>;
1133                         status = "disabled";
1134                 };
1135
1136                 spdif0: spdif0@100a0000 {
1137                         compatible = "starfive,jh7110-spdif";
1138                         reg = <0x0 0x100a0000 0x0 0x1000>;
1139                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1140                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1141                                  <&clkgen JH7110_AUDIO_ROOT>,
1142                                  <&clkgen JH7110_MCLK_INNER>,
1143                                  <&mclk_ext>, <&clkgen JH7110_MCLK>;
1144                         clock-names = "spdif-apb", "spdif-core",
1145                                       "audroot", "mclk_inner",
1146                                       "mclk_ext", "mclk";
1147                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1148                         reset-names = "rst_apb";
1149                         interrupts = <84>;
1150                         interrupt-names = "tx";
1151                         #sound-dai-cells = <0>;
1152                         status = "disabled";
1153                 };
1154
1155                 pwmdac: pwmdac@100b0000 {
1156                         compatible = "starfive,jh7110-pwmdac";
1157                         reg = <0x0 0x100b0000 0x0 0x1000>;
1158                         clocks = <&clkgen JH7110_APB0>,
1159                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1160                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1161                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1162                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1163                         reset-names = "rst-apb";
1164                         dmas = <&dma 22 1>;
1165                         dma-names = "tx";
1166                         #sound-dai-cells = <0>;
1167                         status = "disabled";
1168                 };
1169
1170                 i2stx: i2stx@100c0000 {
1171                         compatible = "snps,designware-i2stx";
1172                         reg = <0x0 0x100c0000 0x0 0x1000>;
1173                         interrupt-names = "tx";
1174                         #sound-dai-cells = <0>;
1175                         dmas = <&dma 28 1>;
1176                         dma-names = "rx";
1177                         status = "disabled";
1178                 };
1179
1180                 pdm: pdm@100d0000 {
1181                         compatible = "starfive,jh7110-pdm";
1182                         reg = <0x0 0x100d0000 0x0 0x1000>;
1183                         reg-names = "pdm";
1184                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1185                                  <&clkgen JH7110_APB0>,
1186                                  <&clkgen JH7110_PDM_CLK_APB>,
1187                                  <&clkgen JH7110_MCLK>,
1188                                  <&mclk_ext>;
1189                         clock-names = "pdm_mclk", "clk_apb0",
1190                                       "pdm_apb", "clk_mclk",
1191                                       "mclk_ext";
1192                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1193                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1194                         reset-names = "pdm_dmic", "pdm_apb";
1195                         #sound-dai-cells = <0>;
1196                 };
1197
1198                 i2srx_mst: i2srx_mst@100e0000 {
1199                         compatible = "starfive,jh7110-i2srx-master";
1200                         reg = <0x0 0x100e0000 0x0 0x1000>;
1201                         clocks = <&clkgen JH7110_APB0>,
1202                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1203                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1204                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1205                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1206                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1207                         clock-names = "apb0", "i2srx_apb",
1208                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1209                                       "i2srx_bclk", "i2srx_lrck";
1210                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1211                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1212                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1213                         dmas = <&dma 24 1>;
1214                         dma-names = "rx";
1215                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1216                         #sound-dai-cells = <0>;
1217                         status = "disabled";
1218                 };
1219
1220                 i2srx_3ch: i2srx_3ch@100e0000 {
1221                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1222                         reg = <0x0 0x100e0000 0x0 0x1000>;
1223                         clocks = <&clkgen JH7110_APB0>,
1224                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1225                                  <&clkgen JH7110_AUDIO_ROOT>,
1226                                  <&clkgen JH7110_MCLK_INNER>,
1227                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1228                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1229                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1230                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1231                                  <&clkgen JH7110_MCLK>,
1232                                  <&i2srx_bclk_ext>,
1233                                  <&i2srx_lrck_ext>;
1234                         clock-names = "apb0", "3ch-apb",
1235                                       "audioroot", "mclk-inner",
1236                                       "bclk_mst", "3ch-lrck",
1237                                       "rx-bclk", "rx-lrck",
1238                                       "mclk", "bclk-ext",
1239                                       "lrck-ext";
1240                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1241                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1242                         dmas = <&dma 24 1>;
1243                         dma-names = "rx";
1244                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1245                         #sound-dai-cells = <0>;
1246                         status = "disabled";
1247                 };
1248
1249                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1250                         compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1251                         reg = <0x0 0x120b0000 0x0 0x1000>;
1252                         clocks = <&clkgen JH7110_MCLK_INNER>,
1253                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1254                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1255                                  <&clkgen JH7110_MCLK>,
1256                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1257                                  <&clkgen JH7110_I2STX0_4CHLRCK>,
1258                                  <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1259                                  <&mclk_ext>;
1260                         clock-names = "inner", "bclk-mst",
1261                                         "lrck-mst", "mclk",
1262                                         "bclk0", "lrck0",
1263                                         "i2s_apb", "mclk_ext";
1264                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1265                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1266                         reset-names = "rst_apb", "rst_bclk";
1267                         dmas = <&dma 47 1>;
1268                         dma-names = "tx";
1269                         #sound-dai-cells = <0>;
1270                         status = "disabled";
1271                 };
1272
1273                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1274                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1275                         reg = <0x0 0x120c0000 0x0 0x1000>;
1276                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1277                                  <&clkgen JH7110_MCLK_INNER>,
1278                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1279                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1280                                  <&clkgen JH7110_MCLK>,
1281                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1282                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1283                                  <&clkgen JH7110_MCLK_OUT>,
1284                                  <&clkgen JH7110_APB0>,
1285                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1286                                  <&mclk_ext>,
1287                                  <&i2stx_bclk_ext>,
1288                                  <&i2stx_lrck_ext>;
1289                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1290                                       "lrck_mst", "mclk", "4chbclk",
1291                                       "4chlrck", "mclk_out",
1292                                       "apb0", "clk_apb",
1293                                       "mclk_ext", "bclk_ext", "lrck_ext";
1294                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1295                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1296                         dmas = <&dma 48 1>;
1297                         dma-names = "tx";
1298                         #sound-dai-cells = <0>;
1299                         status = "disabled";
1300                 };
1301
1302                 ptc: pwm@120d0000 {
1303                         compatible = "starfive,jh7110-pwm";
1304                         reg = <0x0 0x120d0000 0x0 0x10000>;
1305                         reg-names = "control";
1306                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1307                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1308                         starfive,approx-freq = <2000000>;
1309                         #pwm-cells=<3>;
1310                         starfive,npwm = <8>;
1311                         status = "disabled";
1312                 };
1313
1314                 spdif_transmitter: spdif_transmitter {
1315                         compatible = "linux,spdif-dit";
1316                         #sound-dai-cells = <0>;
1317                         status = "disabled";
1318                 };
1319
1320                 pwmdac_codec: pwmdac-transmitter {
1321                         compatible = "starfive,jh7110-pwmdac-dit";
1322                         #sound-dai-cells = <0>;
1323                         status = "disabled";
1324                 };
1325
1326                 dmic_codec: dmic_codec {
1327                         compatible = "dmic-codec";
1328                         #sound-dai-cells = <0>;
1329                         status = "disabled";
1330                 };
1331
1332                 spi0: spi@10060000 {
1333                         compatible = "arm,pl022", "arm,primecell";
1334                         reg = <0x0 0x10060000 0x0 0x10000>;
1335                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1336                         clock-names = "apb_pclk";
1337                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1338                         reset-names = "rst_apb";
1339                         interrupts = <38>;
1340                         /* shortage of dma channel that not be used */
1341                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1342                         /*dma-names = "rx","tx";*/
1343                         arm,primecell-periphid = <0x00041022>;
1344                         num-cs = <1>;
1345                         #address-cells = <1>;
1346                         #size-cells = <0>;
1347                         status = "disabled";
1348                 };
1349
1350                 spi1: spi@10070000 {
1351                         compatible = "arm,pl022", "arm,primecell";
1352                         reg = <0x0 0x10070000 0x0 0x10000>;
1353                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1354                         clock-names = "apb_pclk";
1355                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1356                         reset-names = "rst_apb";
1357                         interrupts = <39>;
1358                         /* shortage of dma channel that not be used */
1359                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1360                         /*dma-names = "rx","tx";*/
1361                         arm,primecell-periphid = <0x00041022>;
1362                         num-cs = <1>;
1363                         #address-cells = <1>;
1364                         #size-cells = <0>;
1365                         status = "disabled";
1366                 };
1367
1368                 spi2: spi@10080000 {
1369                         compatible = "arm,pl022", "arm,primecell";
1370                         reg = <0x0 0x10080000 0x0 0x10000>;
1371                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1372                         clock-names = "apb_pclk";
1373                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1374                         reset-names = "rst_apb";
1375                         interrupts = <40>;
1376                         /* shortage of dma channel that not be used */
1377                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1378                         /*dma-names = "rx","tx";*/
1379                         arm,primecell-periphid = <0x00041022>;
1380                         num-cs = <1>;
1381                         #address-cells = <1>;
1382                         #size-cells = <0>;
1383                         status = "disabled";
1384                 };
1385
1386                 spi3: spi@12070000 {
1387                         compatible = "arm,pl022", "arm,primecell";
1388                         reg = <0x0 0x12070000 0x0 0x10000>;
1389                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1390                         clock-names = "apb_pclk";
1391                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1392                         reset-names = "rst_apb";
1393                         interrupts = <52>;
1394                         /* shortage of dma channel that not be used */
1395                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1396                         /*dma-names = "rx","tx";*/
1397                         arm,primecell-periphid = <0x00041022>;
1398                         num-cs = <1>;
1399                         #address-cells = <1>;
1400                         #size-cells = <0>;
1401                         status = "disabled";
1402                 };
1403
1404                 spi4: spi@12080000 {
1405                         compatible = "arm,pl022", "arm,primecell";
1406                         reg = <0x0 0x12080000 0x0 0x10000>;
1407                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1408                         clock-names = "apb_pclk";
1409                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1410                         reset-names = "rst_apb";
1411                         interrupts = <53>;
1412                         /* shortage of dma channel that not be used */
1413                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1414                         /*dma-names = "rx","tx";*/
1415                         arm,primecell-periphid = <0x00041022>;
1416                         num-cs = <1>;
1417                         #address-cells = <1>;
1418                         #size-cells = <0>;
1419                         status = "disabled";
1420                 };
1421
1422                 spi5: spi@12090000 {
1423                         compatible = "arm,pl022", "arm,primecell";
1424                         reg = <0x0 0x12090000 0x0 0x10000>;
1425                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1426                         clock-names = "apb_pclk";
1427                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1428                         reset-names = "rst_apb";
1429                         interrupts = <54>;
1430                         /* shortage of dma channel that not be used */
1431                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1432                         /*dma-names = "rx","tx";*/
1433                         arm,primecell-periphid = <0x00041022>;
1434                         num-cs = <1>;
1435                         #address-cells = <1>;
1436                         #size-cells = <0>;
1437                         status = "disabled";
1438                 };
1439
1440                 spi6: spi@120A0000 {
1441                         compatible = "arm,pl022", "arm,primecell";
1442                         reg = <0x0 0x120A0000 0x0 0x10000>;
1443                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1444                         clock-names = "apb_pclk";
1445                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1446                         reset-names = "rst_apb";
1447                         interrupts = <55>;
1448                         /* shortage of dma channel that not be used */
1449                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1450                         /*dma-names = "rx","tx";*/
1451                         arm,primecell-periphid = <0x00041022>;
1452                         num-cs = <1>;
1453                         #address-cells = <1>;
1454                         #size-cells = <0>;
1455                         status = "disabled";
1456                 };
1457
1458                 pcie0: pcie@2B000000 {
1459                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1460                         #address-cells = <3>;
1461                         #size-cells = <2>;
1462                         #interrupt-cells = <1>;
1463                         reg = <0x0 0x2B000000 0x0 0x1000000
1464                                0x9 0x40000000 0x0 0x10000000>;
1465                         reg-names = "reg", "config";
1466                         device_type = "pci";
1467                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1468                         bus-range = <0x0 0xff>;
1469                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1470                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1471                         msi-parent = <&plic>;
1472                         interrupts = <56>;
1473                         interrupt-controller;
1474                         interrupt-names = "msi";
1475                         interrupt-parent = <&plic>;
1476                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1477                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1478                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1479                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1480                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1481                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1482                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1483                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1484                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1485                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1486                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1487                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1488                                       "rst_brg", "rst_core", "rst_apb";
1489                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1490                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1491                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1492                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1493                         clock-names = "noc", "tl", "axi_mst0", "apb";
1494                         status = "disabled";
1495                 };
1496
1497                 pcie1: pcie@2C000000 {
1498                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1499                         #address-cells = <3>;
1500                         #size-cells = <2>;
1501                         #interrupt-cells = <1>;
1502                         reg = <0x0 0x2C000000 0x0 0x1000000
1503                                0x9 0xc0000000 0x0 0x10000000>;
1504                         reg-names = "reg", "config";
1505                         device_type = "pci";
1506                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1507                         bus-range = <0x0 0xff>;
1508                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1509                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1510                         msi-parent = <&plic>;
1511                         interrupts = <57>;
1512                         interrupt-controller;
1513                         interrupt-names = "msi";
1514                         interrupt-parent = <&plic>;
1515                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1516                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1517                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1518                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1519                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1520                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1521                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1522                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1523                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1524                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1525                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1526                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1527                                       "rst_brg", "rst_core", "rst_apb";
1528                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1529                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1530                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1531                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1532                         clock-names = "noc", "tl", "axi_mst0", "apb";
1533                         status = "disabled";
1534                 };
1535
1536                 mailbox_contrl0: mailbox@0 {
1537                         compatible = "starfive,mail_box";
1538                         reg = <0x0 0x13060000 0x0 0x0001000>;
1539                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1540                         clock-names = "clk_apb";
1541                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1542                         reset-names = "mbx_rre";
1543                         interrupts = <26 27>;
1544                         #mbox-cells = <2>;
1545                         status = "disabled";
1546                 };
1547
1548                 mailbox_client0: mailbox_client@0 {
1549                         compatible = "starfive,mailbox-test";
1550                         mbox-names = "rx", "tx";
1551                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1552                         status = "disabled";
1553                 };
1554
1555                 display: display-subsystem {
1556                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1557                         ports = <&dc_out_dpi0>;
1558                         status = "disabled";
1559                 };
1560
1561                 dssctrl: dssctrl@295B0000 {
1562                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1563                         reg = <0 0x295B0000 0 0x90>;
1564                 };
1565
1566                 tda988x_pin: tda988x_pin {
1567                         compatible = "starfive,tda998x_rgb_pin";
1568                         status = "disabled";
1569                 };
1570
1571                 rgb_output: rgb-output {
1572                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1573                         //verisilicon,dss-syscon = <&dssctrl>;
1574                         //verisilicon,mux-mask = <0x70 0x380>;
1575                         //verisilicon,mux-val = <0x40 0x280>;
1576                         status = "disabled";
1577                 };
1578
1579                 dc8200: dc8200@29400000 {
1580                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1581                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1582                         reg = <0x0 0x29400000 0x0 0x100>,
1583                               <0x0 0x29400800 0x0 0x2000>,
1584                               <0x0 0x17030000 0x0 0x1000>;
1585                         interrupts = <95>;
1586                         status = "disabled";
1587                         clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1588                         <&clkgen JH7110_VOUT_SRC>,
1589                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1590                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1591                         <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1592                         <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1593                         <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1594                         <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1595                         <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1596                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1597                         <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1598                         <&hdmitx0_pixelclk>,
1599                         <&clkvout JH7110_DC8200_PIX0>,
1600                         <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1601                         <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1602                         clock-names = "noc_disp","vout_src",
1603                            "top_vout_axi","top_vout_ahb",
1604                            "pix_clk","vout_pix1",
1605                            "axi_clk","core_clk","vout_ahb",
1606                            "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1607                            "dc8200_pix0_out","dc8200_pix1_out";
1608                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1609                                  <&rstgen RSTN_U0_DC8200_AXI>,
1610                                  <&rstgen RSTN_U0_DC8200_AHB>,
1611                                  <&rstgen RSTN_U0_DC8200_CORE>,
1612                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
1613                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1614                                         "rst_noc_disp";
1615                 };
1616
1617                 dsi_output: dsi-output {
1618                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1619                         status = "disabled";
1620                 };
1621
1622                 mipi_dphy: mipi-dphy@295e0000{
1623                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1624                         reg = <0x0 0x295e0000 0x0 0x10000>;
1625                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1626                         clock-names = "dphy_txesc";
1627                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1628                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1629                         reset-names = "dphy_sys", "dphy_txbytehs";
1630                         #phy-cells = <0>;
1631                         status = "disabled";
1632                 };
1633
1634                  mipi_dsi: mipi@295d0000 {
1635                         compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1636                         reg = <0x0 0x295d0000 0x0 0x10000>;
1637                         interrupts = <98>;
1638                         reg-names = "dsi";
1639                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1640                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1641                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1642                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1643                         clock-names = "sys", "apb", "txesc", "dpi";
1644                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1645                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1646                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1647                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1648                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1649                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1650                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1651                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1652                         phys = <&mipi_dphy>;
1653                         phy-names = "dphy";
1654                         status = "disabled";
1655
1656                         port {
1657                                 dsi_out_port: endpoint@0 {
1658                                         remote-endpoint = <&panel_dsi_port>;
1659                                 };
1660                                 dsi_in_port: endpoint@1 {
1661                                         remote-endpoint = <&mipi_out>;
1662                                 };
1663                         };
1664
1665                         mipi_panel: panel@0 {
1666                                 /*compatible = "";*/
1667                                 status = "okay";
1668                         };
1669                 };
1670
1671                 hdmi: hdmi@29590000 {
1672                         compatible = "starfive,jh7110-hdmi","inno,hdmi";
1673                         reg = <0x0 0x29590000 0x0 0x4000>;
1674                         interrupts = <99>;
1675                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1676                         /*clocks = <&cru  PCLK_HDMI>;*/
1677                         /*clock-names = "pclk";*/
1678                         /*pinctrl-names = "default";*/
1679                         /*pinctrl-0 = <&hdmi_ctl>;*/
1680                         status = "disabled";
1681                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1682                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1683                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1684                                  <&hdmitx0_pixelclk>;
1685                         clock-names = "sysclk", "mclk","bclk","pclk";
1686                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1687                         reset-names = "hdmi_tx";
1688                         #sound-dai-cells = <0>;
1689                 };
1690
1691                 sound0: snd-card0 {
1692                         compatible = "simple-audio-card";
1693                         simple-audio-card,name = "Starfive-AC108-Sound-Card";
1694                         #address-cells = <1>;
1695                         #size-cells = <0>;
1696                 };
1697
1698                 sound1: snd-card1 {
1699                         compatible = "simple-audio-card";
1700                         simple-audio-card,name = "Starfive-HDMI-Sound-Card";
1701                         #address-cells = <1>;
1702                         #size-cells = <0>;
1703                 };
1704
1705                 sound2: snd-card2 {
1706                         compatible = "simple-audio-card";
1707                         simple-audio-card,name = "Starfive-PDM-Sound-Card";
1708                         #address-cells = <1>;
1709                         #size-cells = <0>;
1710                 };
1711
1712                 sound3: snd-card3 {
1713                         compatible = "simple-audio-card";
1714                         simple-audio-card,name = "Starfive-PWMDAC-Sound-Card";
1715                         #address-cells = <1>;
1716                         #size-cells = <0>;
1717                 };
1718
1719                 sound4: snd-card4 {
1720                         compatible = "simple-audio-card";
1721                         simple-audio-card,name = "Starfive-SPDIF-Sound-Card";
1722                         #address-cells = <1>;
1723                         #size-cells = <0>;
1724                 };
1725
1726                 sound5: snd-card5 {
1727                         compatible = "simple-audio-card";
1728                         simple-audio-card,name = "Starfive-TDM-Sound-Card";
1729                         #address-cells = <1>;
1730                         #size-cells = <0>;
1731                 };
1732
1733                 sound6: snd-card6 {
1734                         compatible = "simple-audio-card";
1735                         simple-audio-card,name = "Starfive-WM8960-Sound-Card";
1736                         #address-cells = <1>;
1737                         #size-cells = <0>;
1738                 };
1739
1740                 co_process: e24@0 {
1741                         compatible = "starfive,e24";
1742                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1743                                 <0x0 0xc0111000 0x0 0x0001f000>;
1744                         reg-names = "ecmd", "espace";
1745                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1746                                  <&clkgen JH7110_E2_CLK_CORE>,
1747                                  <&clkgen JH7110_E2_CLK_DBG>;
1748                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1749                         resets = <&rstgen RSTN_U0_E24_CORE>;
1750                         reset-names = "e24_core";
1751                         starfive,stg-syscon = <&stg_syscon>;
1752                         interrupt-parent = <&plic>;
1753                         firmware-name = "e24_elf";
1754                         irq-mode = <1>;
1755                         mbox-names = "tx", "rx";
1756                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1757                         #address-cells = <1>;
1758                         #size-cells = <1>;
1759                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1760                         status = "disabled";
1761                         dsp@0 {};
1762                 };
1763
1764                 xrp: xrp@0 {
1765                         compatible = "cdns,xrp";
1766                         reg = <0x0  0x10230000 0x0 0x00010000
1767                                 0x0  0x10240000 0x0 0x00010000>;
1768                         memory-region = <&xrp_reserved>;
1769                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1770                         clock-names = "core_clk";
1771                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1772                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1773                         reset-names = "rst_core","rst_axi";
1774                         starfive,stg-syscon = <&stg_syscon>;
1775                         firmware-name = "hifi4_elf";
1776                         #address-cells = <1>;
1777                         #size-cells = <1>;
1778                         ranges = <0x40000000 0x0 0x20000000 0x040000
1779                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1780                         status = "disabled";
1781                         dsp@0 {
1782                         };
1783                 };
1784
1785                 starfive_cpufreq: starfive,jh7110-cpufreq {
1786                         compatible = "starfive,jh7110-cpufreq";
1787                         clocks = <&clkgen JH7110_CPU_CORE>;
1788                         clock-names = "cpu_clk";
1789                 };
1790         };
1791 };