arch/riscv/boot/dts/starfive/jh7110.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2022 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2022 Hal Feng <hal.feng@starfivetech.com>
   5  */
   6
   7 /dts-v1/;
   8 #include "jh7110-clk.dtsi"
   9 #include <dt-bindings/reset/starfive-jh7110.h>
  10 #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
  11 #include <dt-bindings/clock/starfive-jh7110-vout.h>
  12 #include <dt-bindings/clock/starfive-jh7110-isp.h>
  13 #include <dt-bindings/power/jh7110-power.h>
  14
  15 / {
  16         compatible = "starfive,jh7110";
  17         #address-cells = <2>;
  18         #size-cells = <2>;
  19
  20         cluster0_opp: opp-table-0 {
  21                         compatible = "operating-points-v2";
  22                         opp-shared;
  23                         opp-375000000 {
  24                                         opp-hz = /bits/ 64 <375000000>;
  25                                         opp-microvolt = <880000>;
  26                         };
  27                         opp-500000000 {
  28                                         opp-hz = /bits/ 64 <500000000>;
  29                                         opp-microvolt = <880000>;
  30                         };
  31                         opp-750000000 {
  32                                         opp-hz = /bits/ 64 <750000000>;
  33                                         opp-microvolt = <880000>;
  34                         };
  35                         opp-1500000000 {
  36                                         opp-hz = /bits/ 64 <1500000000>;
  37                                         opp-microvolt = <1000000>;
  38                         };
  39         };
  40
  41         cpus {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44
  45                 cpu0: cpu@0 {
  46                         compatible = "sifive,u74-mc", "riscv";
  47                         reg = <0>;
  48                         d-cache-block-size = <64>;
  49                         d-cache-sets = <64>;
  50                         d-cache-size = <8192>;
  51                         d-tlb-sets = <1>;
  52                         d-tlb-size = <40>;
  53                         device_type = "cpu";
  54                         i-cache-block-size = <64>;
  55                         i-cache-sets = <64>;
  56                         i-cache-size = <16384>;
  57                         i-tlb-sets = <1>;
  58                         i-tlb-size = <40>;
  59                         mmu-type = "riscv,sv39";
  60                         cpu-idle-states = <&CPU_NONRET_0_0>;
  61                         next-level-cache = <&cachectrl>;
  62                         riscv,isa = "rv64imac";
  63                         tlb-split;
  64                         status = "disabled";
  65
  66                         cpu0intctrl: interrupt-controller {
  67                                 #interrupt-cells = <1>;
  68                                 compatible = "riscv,cpu-intc";
  69                                 interrupt-controller;
  70                         };
  71                 };
  72
  73                 cpu1: cpu@1 {
  74                         compatible = "sifive,u74-mc", "riscv";
  75                         reg = <1>;
  76                         d-cache-block-size = <64>;
  77                         d-cache-sets = <64>;
  78                         d-cache-size = <32768>;
  79                         d-tlb-sets = <1>;
  80                         d-tlb-size = <40>;
  81                         device_type = "cpu";
  82                         i-cache-block-size = <64>;
  83                         i-cache-sets = <64>;
  84                         i-cache-size = <32768>;
  85                         i-tlb-sets = <1>;
  86                         i-tlb-size = <40>;
  87                         mmu-type = "riscv,sv39";
  88                         cpu-idle-states = <&CPU_NONRET_0_0>;
  89                         next-level-cache = <&cachectrl>;
  90                         riscv,isa = "rv64imafdc";
  91                         tlb-split;
  92                         status = "okay";
  93                         operating-points-v2 = <&cluster0_opp>;
  94
  95                         cpu1intctrl: interrupt-controller {
  96                                 #interrupt-cells = <1>;
  97                                 compatible = "riscv,cpu-intc";
  98                                 interrupt-controller;
  99                         };
 100                 };
 101
 102                 cpu2: cpu@2 {
 103                         compatible = "sifive,u74-mc", "riscv";
 104                         reg = <2>;
 105                         d-cache-block-size = <64>;
 106                         d-cache-sets = <64>;
 107                         d-cache-size = <32768>;
 108                         d-tlb-sets = <1>;
 109                         d-tlb-size = <40>;
 110                         device_type = "cpu";
 111                         i-cache-block-size = <64>;
 112                         i-cache-sets = <64>;
 113                         i-cache-size = <32768>;
 114                         i-tlb-sets = <1>;
 115                         i-tlb-size = <40>;
 116                         mmu-type = "riscv,sv39";
 117                         cpu-idle-states = <&CPU_NONRET_0_0>;
 118                         next-level-cache = <&cachectrl>;
 119                         riscv,isa = "rv64imafdc";
 120                         tlb-split;
 121                         status = "okay";
 122                         operating-points-v2 = <&cluster0_opp>;
 123
 124                         cpu2intctrl: interrupt-controller {
 125                                 #interrupt-cells = <1>;
 126                                 compatible = "riscv,cpu-intc";
 127                                 interrupt-controller;
 128                         };
 129                 };
 130
 131                 cpu3: cpu@3 {
 132                         compatible = "sifive,u74-mc", "riscv";
 133                         reg = <3>;
 134                         d-cache-block-size = <64>;
 135                         d-cache-sets = <64>;
 136                         d-cache-size = <32768>;
 137                         d-tlb-sets = <1>;
 138                         d-tlb-size = <40>;
 139                         device_type = "cpu";
 140                         i-cache-block-size = <64>;
 141                         i-cache-sets = <64>;
 142                         i-cache-size = <32768>;
 143                         i-tlb-sets = <1>;
 144                         i-tlb-size = <40>;
 145                         mmu-type = "riscv,sv39";
 146                         cpu-idle-states = <&CPU_NONRET_0_0>;
 147                         next-level-cache = <&cachectrl>;
 148                         riscv,isa = "rv64imafdc";
 149                         tlb-split;
 150                         status = "okay";
 151                         operating-points-v2 = <&cluster0_opp>;
 152
 153                         cpu3intctrl: interrupt-controller {
 154                                 #interrupt-cells = <1>;
 155                                 compatible = "riscv,cpu-intc";
 156                                 interrupt-controller;
 157                         };
 158                 };
 159
 160                 cpu4: cpu@4 {
 161                         compatible = "sifive,u74-mc", "riscv";
 162                         reg = <4>;
 163                         d-cache-block-size = <64>;
 164                         d-cache-sets = <64>;
 165                         d-cache-size = <32768>;
 166                         d-tlb-sets = <1>;
 167                         d-tlb-size = <40>;
 168                         device_type = "cpu";
 169                         i-cache-block-size = <64>;
 170                         i-cache-sets = <64>;
 171                         i-cache-size = <32768>;
 172                         i-tlb-sets = <1>;
 173                         i-tlb-size = <40>;
 174                         mmu-type = "riscv,sv39";
 175                         cpu-idle-states = <&CPU_NONRET_0_0>;
 176                         next-level-cache = <&cachectrl>;
 177                         riscv,isa = "rv64imafdc";
 178                         tlb-split;
 179                         status = "okay";
 180                         operating-points-v2 = <&cluster0_opp>;
 181
 182                         cpu4intctrl: interrupt-controller {
 183                                 #interrupt-cells = <1>;
 184                                 compatible = "riscv,cpu-intc";
 185                                 interrupt-controller;
 186                         };
 187                 };
 188         };
 189
 190         idle-states {
 191                 CPU_NONRET_0_0: cpu-nonretentive-0-0 {
 192                         compatible = "riscv,idle-state";
 193                         riscv,sbi-suspend-param = <0x80000000>;
 194                         entry-latency-us = <600>;
 195                         exit-latency-us = <1100>;
 196                         min-residency-us = <2700>;
 197                         wakeup-latency-us = <1500>;
 198                 };
 199         };
 200
 201         soc: soc {
 202                 compatible = "simple-bus";
 203                 interrupt-parent = <&plic>;
 204                 #address-cells = <2>;
 205                 #size-cells = <2>;
 206                 #clock-cells = <1>;
 207                 ranges;
 208
 209                 cachectrl: cache-controller@2010000 {
 210                         compatible = "sifive,fu740-c000-ccache", "cache";
 211                         reg = <0x0 0x2010000 0x0 0x4000 0x0 0x8000000 0x0 0x2000000>;
 212                         reg-names = "control", "sideband";
 213                         interrupts = <1 3 4 2>;
 214                         cache-block-size = <64>;
 215                         cache-level = <2>;
 216                         cache-sets = <2048>;
 217                         cache-size = <2097152>;
 218                         cache-unified;
 219                 };
 220
 221                 aon_syscon: aon_syscon@17010000 {
 222                         compatible = "syscon";
 223                         reg = <0x0 0x17010000 0x0 0x1000>;
 224                 };
 225
 226                 stg_syscon: stg_syscon@10240000 {
 227                         compatible = "syscon";
 228                         reg = <0x0 0x10240000 0x0 0x1000>;
 229                 };
 230
 231                 sys_syscon: sys_syscon@13030000 {
 232                         compatible = "syscon";
 233                         reg = <0x0 0x13030000 0x0 0x1000>;
 234                 };
 235
 236                 clint: clint@2000000 {
 237                         compatible = "riscv,clint0";
 238                         reg = <0x0 0x2000000 0x0 0x10000>;
 239                         reg-names = "control";
 240                         interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 241                                                 &cpu1intctrl 3 &cpu1intctrl 7
 242                                                 &cpu2intctrl 3 &cpu2intctrl 7
 243                                                 &cpu3intctrl 3 &cpu3intctrl 7
 244                                                 &cpu4intctrl 3 &cpu4intctrl 7>;
 245                         #interrupt-cells = <1>;
 246                 };
 247
 248                 plic: plic@c000000 {
 249                         compatible = "riscv,plic0";
 250                         reg = <0x0 0xc000000 0x0 0x4000000>;
 251                         reg-names = "control";
 252                         interrupts-extended = <&cpu0intctrl 11
 253                                                 &cpu1intctrl 11 &cpu1intctrl 9
 254                                                 &cpu2intctrl 11 &cpu2intctrl 9
 255                                                 &cpu3intctrl 11 &cpu3intctrl 9
 256                                                 &cpu4intctrl 11 &cpu4intctrl 9>;
 257                         interrupt-controller;
 258                         #interrupt-cells = <1>;
 259                         riscv,max-priority = <7>;
 260                         riscv,ndev = <136>;
 261                 };
 262
 263                 clkgen: clock-controller {
 264                         compatible = "starfive,jh7110-clkgen";
 265                         reg = <0x0 0x13020000 0x0 0x10000>,
 266                                 <0x0 0x10230000 0x0 0x10000>,
 267                                 <0x0 0x17000000 0x0 0x10000>;
 268                         reg-names = "sys", "stg", "aon";
 269                         clocks = <&osc>, <&gmac1_rmii_refin>,
 270                                  <&gmac1_rgmii_rxin>,
 271                                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 272                                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
 273                                  <&tdm_ext>, <&mclk_ext>,
 274                                  <&jtag_tck_inner>, <&bist_apb>,
 275                                  <&clk_rtc>,
 276                                  <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
 277                         clock-names = "osc", "gmac1_rmii_refin",
 278                                 "gmac1_rgmii_rxin",
 279                                 "i2stx_bclk_ext", "i2stx_lrck_ext",
 280                                 "i2srx_bclk_ext", "i2srx_lrck_ext",
 281                                 "tdm_ext", "mclk_ext",
 282                                 "jtag_tck_inner", "bist_apb",
 283                                 "clk_rtc",
 284                                 "gmac0_rmii_refin", "gmac0_rgmii_rxin";
 285                         #clock-cells = <1>;
 286                         starfive,sys-syscon = <&sys_syscon 0x18 0x1c
 287                                         0x20 0x24 0x28 0x2c 0x30 0x34>;
 288                         status = "okay";
 289                 };
 290
 291                 clkvout: clock-controller@295C0000 {
 292                         compatible = "starfive,jh7110-clk-vout";
 293                         reg = <0x0 0x295C0000 0x0 0x10000>;
 294                         reg-names = "vout";
 295                         clocks = <&hdmitx0_pixelclk>,
 296                                  <&mipitx_dphy_rxesc>,
 297                                  <&mipitx_dphy_txbytehs>,
 298                                  <&clkgen JH7110_VOUT_SRC>,
 299                                  <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
 300                         clock-names = "hdmitx0_pixelclk",
 301                                       "mipitx_dphy_rxesc",
 302                                       "mipitx_dphy_txbytehs",
 303                                       "vout_src",
 304                                       "vout_top_ahb";
 305                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
 306                         reset-names = "vout_src";
 307                         #clock-cells = <1>;
 308                         power-domains = <&pwrc JH7110_PD_VOUT>;
 309                         status = "okay";
 310                 };
 311
 312                 clkisp: clock-controller@19810000 {
 313                         compatible = "starfive,jh7110-clk-isp";
 314                         reg = <0x0 0x19810000 0x0 0x10000>;
 315                         reg-names = "isp";
 316                         #clock-cells = <1>;
 317                         clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
 318                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 319                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
 320                                  <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
 321                         clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
 322                                       "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
 323                                       "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
 324                                       "u0_sft7110_noc_bus_clk_isp_axi";
 325                         resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 326                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
 327                                  <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
 328                         reset-names = "rst_isp_top_n", "rst_isp_top_axi",
 329                                       "rst_isp_noc_bus_n";
 330                         power-domains = <&pwrc JH7110_PD_ISP>;
 331                         status = "okay";
 332                 };
 333
 334                 qspi: spi@13010000 {
 335                         compatible = "cdns,qspi-nor";
 336                         #address-cells = <1>;
 337                         #size-cells = <0>;
 338                         reg = <0x0 0x13010000 0x0 0x10000
 339                                 0x0 0x21000000 0x0 0x400000>;
 340                         clocks = <&clkgen JH7110_QSPI_CLK_REF>;
 341                         clock-names = "clk_ref";
 342                         resets = <&rstgen RSTN_U0_CDNS_QSPI_APB>,
 343                                  <&rstgen RSTN_U0_CDNS_QSPI_AHB>,
 344                                  <&rstgen RSTN_U0_CDNS_QSPI_REF>;
 345                         resets-names = "rst_apb", "rst_ahb", "rst_ref";
 346                         cdns,fifo-depth = <256>;
 347                         cdns,fifo-width = <4>;
 348                         spi-max-frequency = <250000000>;
 349
 350                         nor_flash: nor-flash@0 {
 351                                 compatible = "jedec,spi-nor";
 352                                 reg=<0>;
 353                                 spi-max-frequency = <100000000>;
 354                                 cdns,tshsl-ns = <1>;
 355                                 cdns,tsd2d-ns = <1>;
 356                                 cdns,tchsh-ns = <1>;
 357                                 cdns,tslch-ns = <1>;
 358                         };
 359                 };
 360
 361                 otp: otp@17050000 {
 362                         compatible = "starfive,jh7110-otp";
 363                         reg = <0x0 0x17050000 0x0 0x10000>;
 364                         clock-frequency = <4000000>;
 365                         clocks = <&clkgen JH7110_OTPC_CLK_APB>;
 366                         clock-names = "apb";
 367                 };
 368
 369                 usbdrd30: usbdrd{
 370                         compatible = "starfive,jh7110-cdns3";
 371                         reg = <0x0 0x10210000 0x0 0x1000>,
 372                               <0x0 0x10200000 0x0 0x1000>;
 373                         clocks = <&clkgen JH7110_USB_125M>,
 374                                  <&clkgen JH7110_USB0_CLK_APP_125>,
 375                                  <&clkgen JH7110_USB0_CLK_LPM>,
 376                                  <&clkgen JH7110_USB0_CLK_STB>,
 377                                  <&clkgen JH7110_USB0_CLK_USB_APB>,
 378                                  <&clkgen JH7110_USB0_CLK_AXI>,
 379                                  <&clkgen JH7110_USB0_CLK_UTMI_APB>,
 380                                  <&clkgen JH7110_PCIE0_CLK_APB>;
 381                         clock-names = "125m","app","lpm","stb","apb","axi","utmi", "phy";
 382                         resets = <&rstgen RSTN_U0_CDN_USB_PWRUP>,
 383                                  <&rstgen RSTN_U0_CDN_USB_APB>,
 384                                  <&rstgen RSTN_U0_CDN_USB_AXI>,
 385                                  <&rstgen RSTN_U0_CDN_USB_UTMI_APB>,
 386                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
 387                         reset-names = "pwrup","apb","axi","utmi", "phy";
 388                         starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
 389                         starfive,sys-syscon = <&sys_syscon 0x18>;
 390                         status = "disabled";
 391                         #address-cells = <2>;
 392                         #size-cells = <2>;
 393                         #interrupt-cells = <1>;
 394                         ranges;
 395                         usbdrd_cdns3: usb@10100000 {
 396                                 compatible = "cdns,usb3";
 397                                 reg = <0x0 0x10100000 0x0 0x10000>,
 398                                       <0x0 0x10110000 0x0 0x10000>,
 399                                       <0x0 0x10120000 0x0 0x10000>;
 400                                 reg-names = "otg", "xhci", "dev";
 401                                 interrupts = <100>, <108>, <110>;
 402                                 interrupt-names = "host", "peripheral", "otg";
 403                                 phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
 404                                 maximum-speed = "super-speed";
 405                         };
 406                 };
 407
 408                 timer: timer@13050000 {
 409                         compatible = "starfive,jh7110-timers";
 410                         reg = <0x0 0x13050000 0x0 0x10000>;
 411                         interrupts = <69>, <70>, <71> ,<72>;
 412                         interrupt-names = "timer0", "timer1",
 413                                           "timer2", "timer3";
 414                         clocks = <&clkgen JH7110_TIMER_CLK_TIMER0>,
 415                                  <&clkgen JH7110_TIMER_CLK_TIMER1>,
 416                                  <&clkgen JH7110_TIMER_CLK_TIMER2>,
 417                                  <&clkgen JH7110_TIMER_CLK_TIMER3>,
 418                                  <&clkgen JH7110_TIMER_CLK_APB>;
 419                         clock-names = "timer0", "timer1",
 420                                       "timer2", "timer3", "apb_clk";
 421                         resets = <&rstgen RSTN_U0_TIMER_TIMER0>,
 422                                  <&rstgen RSTN_U0_TIMER_TIMER1>,
 423                                  <&rstgen RSTN_U0_TIMER_TIMER2>,
 424                                  <&rstgen RSTN_U0_TIMER_TIMER3>,
 425                                  <&rstgen RSTN_U0_TIMER_APB>;
 426                         reset-names = "timer0", "timer1",
 427                                       "timer2", "timer3", "apb_rst";
 428                         clock-frequency = <24000000>;
 429                         status = "okay";
 430                 };
 431
 432                 wdog: wdog@13070000 {
 433                         compatible = "starfive,jh7110-wdt";
 434                         reg = <0x0 0x13070000 0x0 0x10000>;
 435                         interrupts = <68>;
 436                         interrupt-names = "wdog";
 437                         clocks = <&clkgen JH7110_DSKIT_WDT_CLK_WDT>,
 438                                  <&clkgen JH7110_DSKIT_WDT_CLK_APB>;
 439                         clock-names = "core_clk", "apb_clk";
 440                         resets = <&rstgen RSTN_U0_DSKIT_WDT_APB>,
 441                                  <&rstgen RSTN_U0_DSKIT_WDT_CORE>;
 442                         reset-names = "rst_apb", "rst_core";
 443                         timeout-sec = <15>;
 444                         status = "okay";
 445                 };
 446
 447                 rtc: rtc@17040000 {
 448                         compatible = "starfive,jh7110-rtc";
 449                         reg = <0x0 0x17040000 0x0 0x10000>;
 450                         interrupts = <10>, <11>, <12>;
 451                         interrupt-names = "rtc_ms_pulse", "rtc_sec_pulse", "rtc";
 452                         clocks = <&clkgen JH7110_RTC_HMS_CLK_APB>,
 453                                  <&clkgen JH7110_RTC_HMS_CLK_CAL>;
 454                         clock-names = "pclk", "cal_clk";
 455                         resets = <&rstgen RSTN_U0_RTC_HMS_OSC32K>,
 456                                  <&rstgen RSTN_U0_RTC_HMS_APB>,
 457                                  <&rstgen RSTN_U0_RTC_HMS_CAL>;
 458                         reset-names = "rst_osc", "rst_apb", "rst_cal";
 459                         rtc,cal-clock-freq = <1000000>;
 460                         status = "okay";
 461                 };
 462
 463                 pwrc: power-controller@17030000 {
 464                         compatible = "starfive,jh7110-pmu";
 465                         reg = <0x0 0x17030000 0x0 0x10000>;
 466                         interrupts = <111>;
 467                         #power-domain-cells = <1>;
 468                         status = "okay";
 469                 };
 470
 471                 uart0: serial@10000000 {
 472                         compatible = "snps,dw-apb-uart";
 473                         reg = <0x0 0x10000000 0x0 0x10000>;
 474                         reg-io-width = <4>;
 475                         reg-shift = <2>;
 476                         clocks = <&clkgen JH7110_UART0_CLK_CORE>,
 477                                  <&clkgen JH7110_UART0_CLK_APB>;
 478                         clock-names = "baudclk", "apb_pclk";
 479                         resets = <&rstgen RSTN_U0_DW_UART_APB>,
 480                                 <&rstgen RSTN_U0_DW_UART_CORE>;
 481                         interrupts = <32>;
 482                         status = "disabled";
 483                 };
 484
 485                 uart1: serial@10010000 {
 486                         compatible = "snps,dw-apb-uart";
 487                         reg = <0x0 0x10010000 0x0 0x10000>;
 488                         reg-io-width = <4>;
 489                         reg-shift = <2>;
 490                         clocks = <&clkgen JH7110_UART1_CLK_CORE>,
 491                                  <&clkgen JH7110_UART1_CLK_APB>;
 492                         clock-names = "baudclk", "apb_pclk";
 493                         resets = <&rstgen RSTN_U1_DW_UART_APB>,
 494                                 <&rstgen RSTN_U1_DW_UART_CORE>;
 495                         interrupts = <33>;
 496                         status = "disabled";
 497                 };
 498
 499                 uart2: serial@10020000 {
 500                         compatible = "snps,dw-apb-uart";
 501                         reg = <0x0 0x10020000 0x0 0x10000>;
 502                         reg-io-width = <4>;
 503                         reg-shift = <2>;
 504                         clocks = <&clkgen JH7110_UART2_CLK_CORE>,
 505                                  <&clkgen JH7110_UART2_CLK_APB>;
 506                         clock-names = "baudclk", "apb_pclk";
 507                         resets = <&rstgen RSTN_U2_DW_UART_APB>,
 508                                 <&rstgen RSTN_U2_DW_UART_CORE>;
 509                         interrupts = <34>;
 510                         status = "disabled";
 511                 };
 512
 513                 uart3: serial@12000000 {
 514                         compatible = "snps,dw-apb-uart";
 515                         reg = <0x0 0x12000000 0x0 0x10000>;
 516                         reg-io-width = <4>;
 517                         reg-shift = <2>;
 518                         clocks = <&clkgen JH7110_UART3_CLK_CORE>,
 519                                  <&clkgen JH7110_UART3_CLK_APB>;
 520                         clock-names = "baudclk", "apb_pclk";
 521                         resets = <&rstgen RSTN_U3_DW_UART_APB>,
 522                                 <&rstgen RSTN_U3_DW_UART_CORE>;
 523                         interrupts = <45>;
 524                         status = "disabled";
 525                 };
 526
 527                 uart4: serial@12010000 {
 528                         compatible = "snps,dw-apb-uart";
 529                         reg = <0x0 0x12010000 0x0 0x10000>;
 530                         reg-io-width = <4>;
 531                         reg-shift = <2>;
 532                         clocks = <&clkgen JH7110_UART4_CLK_CORE>,
 533                                  <&clkgen JH7110_UART4_CLK_APB>;
 534                         clock-names = "baudclk", "apb_pclk";
 535                         resets = <&rstgen RSTN_U4_DW_UART_APB>,
 536                                 <&rstgen RSTN_U4_DW_UART_CORE>;
 537                         interrupts = <46>;
 538                         status = "disabled";
 539                 };
 540
 541                 uart5: serial@12020000 {
 542                         compatible = "snps,dw-apb-uart";
 543                         reg = <0x0 0x12020000 0x0 0x10000>;
 544                         reg-io-width = <4>;
 545                         reg-shift = <2>;
 546                         clocks = <&clkgen JH7110_UART5_CLK_CORE>,
 547                                  <&clkgen JH7110_UART5_CLK_APB>;
 548                         clock-names = "baudclk", "apb_pclk";
 549                         resets = <&rstgen RSTN_U5_DW_UART_APB>,
 550                                 <&rstgen RSTN_U5_DW_UART_CORE>;
 551                         interrupts = <47>;
 552                         status = "disabled";
 553                 };
 554
 555                 dma: dma-controller@16050000 {
 556                         compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
 557                         reg = <0x0 0x16050000 0x0 0x10000>;
 558                         clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
 559                                  <&clkgen JH7110_DMA1P_CLK_AHB>,
 560                                  <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
 561                         clock-names = "core-clk", "cfgr-clk", "stg_clk";
 562                         resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
 563                                  <&rstgen RSTN_U0_DW_DMA1P_AHB>,
 564                                  <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
 565                         reset-names = "rst_axi", "rst_ahb", "rst_stg";
 566                         interrupts = <73>;
 567                         #dma-cells = <2>;
 568                         dma-channels = <4>;
 569                         snps,dma-masters = <1>;
 570                         snps,data-width = <3>;
 571                         snps,num-hs-if = <56>;
 572                         snps,block-size = <65536 65536 65536 65536>;
 573                         snps,priority = <0 1 2 3>;
 574                         snps,axi-max-burst-len = <16>;
 575                         status = "disabled";
 576                 };
 577
 578                 gpio: gpio@13040000 {
 579                         compatible = "starfive,jh7110-sys-pinctrl";
 580                         reg = <0x0 0x13040000 0x0 0x10000>;
 581                         reg-names = "control";
 582                         clocks = <&clkgen JH7110_SYS_IOMUX_PCLK>;
 583                         resets = <&rstgen RSTN_U0_SYS_IOMUX_PRESETN>;
 584                         interrupts = <86>;
 585                         interrupt-controller;
 586                         #gpio-cells = <2>;
 587                         ngpios = <64>;
 588                         status = "okay";
 589                 };
 590
 591                 gpioa: gpio@17020000 {
 592                         compatible = "starfive,jh7110-aon-pinctrl";
 593                         reg = <0x0 0x17020000 0x0 0x10000>;
 594                         reg-names = "control";
 595                         resets = <&rstgen RSTN_U0_AON_IOMUX_PRESETN>;
 596                         interrupts = <85>;
 597                         interrupt-controller;
 598                         #gpio-cells = <2>;
 599                         ngpios = <4>;
 600                         status = "okay";
 601                 };
 602
 603                 sfctemp: tmon@120e0000  {
 604                         compatible = "starfive,jh7110-temp";
 605                         reg = <0x0 0x120e0000 0x0 0x10000>;
 606                         interrupts = <81>;
 607                         clocks = <&clkgen JH7110_TEMP_SENSOR_CLK_TEMP>,
 608                                  <&clkgen JH7110_TEMP_SENSOR_CLK_APB>;
 609                         clock-names = "sense", "bus";
 610                         resets = <&rstgen RSTN_U0_TEMP_SENSOR_TEMP>,
 611                                  <&rstgen RSTN_U0_TEMP_SENSOR_APB>;
 612                         reset-names = "sense", "bus";
 613                         #thermal-sensor-cells = <0>;
 614                         status = "disabled";
 615                 };
 616
 617                 thermal-zones {
 618                         cpu-thermal {
 619                                 polling-delay-passive = <250>;
 620                                 polling-delay = <15000>;
 621
 622                                 thermal-sensors = <&sfctemp>;
 623
 624                                 cooling-maps {
 625                                 };
 626
 627                                 trips {
 628                                         cpu_alert0: cpu_alert0 {
 629                                                 /* milliCelsius */
 630                                                 temperature = <75000>;
 631                                                 hysteresis = <2000>;
 632                                                 type = "passive";
 633                                         };
 634
 635                                         cpu_crit: cpu_crit {
 636                                                 /* milliCelsius */
 637                                                 temperature = <90000>;
 638                                                 hysteresis = <2000>;
 639                                                 type = "critical";
 640                                         };
 641                                 };
 642                         };
 643                 };
 644
 645                 trng: trng@1600C000 {
 646                         compatible = "starfive,jh7110-trng";
 647                         reg = <0x0 0x1600C000 0x0 0x4000>;
 648                         clocks = <&clkgen JH7110_SEC_HCLK>,
 649                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 650                         clock-names = "hclk", "miscahb_clk";
 651                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 652                         interrupts = <30>;
 653                         status = "disabled";
 654                 };
 655
 656                 sec_dma: sec_dma@16008000 {
 657                         compatible = "arm,pl080", "arm,primecell";
 658                         arm,primecell-periphid = <0x00041080>;
 659                         reg = <0x0 0x16008000 0x0 0x4000>;
 660                         reg-names = "sec_dma";
 661                         interrupts = <29>;
 662                         clocks = <&clkgen JH7110_SEC_HCLK>,
 663                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 664                         clock-names = "sec_hclk","apb_pclk";
 665                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 666                         reset-names = "sec_hre";
 667                         lli-bus-interface-ahb1;
 668                         mem-bus-interface-ahb1;
 669                         memcpy-burst-size = <256>;
 670                         memcpy-bus-width = <32>;
 671                         #dma-cells = <2>;
 672                         status = "disabled";
 673                 };
 674
 675                 crypto: crypto@16000000 {
 676                         compatible = "starfive,jh7110-sec";
 677                         reg = <0x0 0x16000000 0x0 0x4000>,
 678                               <0x0 0x16008000 0x0 0x4000>;
 679                         reg-names = "secreg","secdma";
 680                         interrupts = <28>, <29>;
 681                         interrupt-names = "secirq", "dmairq";
 682                         clocks = <&clkgen JH7110_SEC_HCLK>,
 683                                  <&clkgen JH7110_SEC_MISCAHB_CLK>;
 684                         clock-names = "sec_hclk","sec_ahb";
 685                         resets = <&rstgen RSTN_U0_SEC_TOP_HRESETN>;
 686                         reset-names = "sec_hre";
 687                         enable-side-channel-mitigation = "true";
 688                         enable-dma = "true";
 689                         dmas = <&sec_dma 1 2>,
 690                                <&sec_dma 0 2>;
 691                         dma-names = "sec_m","sec_p";
 692                         status = "disabled";
 693                 };
 694
 695                 i2c0: i2c@10030000 {
 696                         compatible = "snps,designware-i2c";
 697                         reg = <0x0 0x10030000 0x0 0x10000>;
 698                         clocks = <&clkgen JH7110_I2C0_CLK_CORE>,
 699                                  <&clkgen JH7110_I2C0_CLK_APB>;
 700                         clock-names = "ref", "pclk";
 701                         resets = <&rstgen RSTN_U0_DW_I2C_APB>;
 702                         interrupts = <35>;
 703                         #address-cells = <1>;
 704                         #size-cells = <0>;
 705                         status = "disabled";
 706                 };
 707
 708                 i2c1: i2c@10040000 {
 709                         compatible = "snps,designware-i2c";
 710                         reg = <0x0 0x10040000 0x0 0x10000>;
 711                         clocks = <&clkgen JH7110_I2C1_CLK_CORE>,
 712                                  <&clkgen JH7110_I2C1_CLK_APB>;
 713                         clock-names = "ref", "pclk";
 714                         resets = <&rstgen RSTN_U1_DW_I2C_APB>;
 715                         interrupts = <36>;
 716                         #address-cells = <1>;
 717                         #size-cells = <0>;
 718                         status = "disabled";
 719                 };
 720
 721                 i2c2: i2c@10050000 {
 722                         compatible = "snps,designware-i2c";
 723                         reg = <0x0 0x10050000 0x0 0x10000>;
 724                         clocks = <&clkgen JH7110_I2C2_CLK_CORE>,
 725                                  <&clkgen JH7110_I2C2_CLK_APB>;
 726                         clock-names = "ref", "pclk";
 727                         resets = <&rstgen RSTN_U2_DW_I2C_APB>;
 728                         interrupts = <37>;
 729                         #address-cells = <1>;
 730                         #size-cells = <0>;
 731                         status = "disabled";
 732                 };
 733
 734                 i2c3: i2c@12030000 {
 735                         compatible = "snps,designware-i2c";
 736                         reg = <0x0 0x12030000 0x0 0x10000>;
 737                         clocks = <&clkgen JH7110_I2C3_CLK_CORE>,
 738                                  <&clkgen JH7110_I2C3_CLK_APB>;
 739                         clock-names = "ref", "pclk";
 740                         resets = <&rstgen RSTN_U3_DW_I2C_APB>;
 741                         interrupts = <48>;
 742                         #address-cells = <1>;
 743                         #size-cells = <0>;
 744                         status = "disabled";
 745                 };
 746
 747                 i2c4: i2c@12040000 {
 748                         compatible = "snps,designware-i2c";
 749                         reg = <0x0 0x12040000 0x0 0x10000>;
 750                         clocks = <&clkgen JH7110_I2C4_CLK_CORE>,
 751                                  <&clkgen JH7110_I2C4_CLK_APB>;
 752                         clock-names = "ref", "pclk";
 753                         resets = <&rstgen RSTN_U4_DW_I2C_APB>;
 754                         interrupts = <49>;
 755                         #address-cells = <1>;
 756                         #size-cells = <0>;
 757                         status = "disabled";
 758                 };
 759
 760                 i2c5: i2c@12050000 {
 761                         compatible = "snps,designware-i2c";
 762                         reg = <0x0 0x12050000 0x0 0x10000>;
 763                         clocks = <&clkgen JH7110_I2C5_CLK_CORE>,
 764                                  <&clkgen JH7110_I2C5_CLK_APB>;
 765                         clock-names = "ref", "pclk";
 766                         resets = <&rstgen RSTN_U5_DW_I2C_APB>;
 767                         interrupts = <50>;
 768                         #address-cells = <1>;
 769                         #size-cells = <0>;
 770                         status = "disabled";
 771                 };
 772
 773                 i2c6: i2c@12060000 {
 774                         compatible = "snps,designware-i2c";
 775                         reg = <0x0 0x12060000 0x0 0x10000>;
 776                         clocks = <&clkgen JH7110_I2C6_CLK_CORE>,
 777                                  <&clkgen JH7110_I2C6_CLK_APB>;
 778                         clock-names = "ref", "pclk";
 779                         resets = <&rstgen RSTN_U6_DW_I2C_APB>;
 780                         interrupts = <51>;
 781                         #address-cells = <1>;
 782                         #size-cells = <0>;
 783                         status = "disabled";
 784                 };
 785
 786                 /* unremovable emmc as mmcblk0 */
 787                 sdio0: sdio0@16010000 {
 788                         compatible = "starfive,jh7110-sdio";
 789                         reg = <0x0 0x16010000 0x0 0x10000>;
 790                         clocks = <&clkgen JH7110_SDIO0_CLK_AHB>,
 791                                  <&clkgen JH7110_SDIO0_CLK_SDCARD>;
 792                         clock-names = "biu","ciu";
 793                         resets = <&rstgen RSTN_U0_DW_SDIO_AHB>;
 794                         reset-names = "reset";
 795                         interrupts = <74>;
 796                         fifo-depth = <32>;
 797                         fifo-watermark-aligned;
 798                         data-addr = <0>;
 799                         starfive,sys-syscon = <&sys_syscon 0x14 0x1a 0x7c000000>;
 800                         status = "disabled";
 801                 };
 802
 803                 sdio1: sdio1@16020000 {
 804                         compatible = "starfive,jh7110-sdio";
 805                         reg = <0x0 0x16020000 0x0 0x10000>;
 806                         clocks = <&clkgen JH7110_SDIO1_CLK_AHB>,
 807                                  <&clkgen JH7110_SDIO1_CLK_SDCARD>;
 808                         clock-names = "biu","ciu";
 809                         resets = <&rstgen RSTN_U1_DW_SDIO_AHB>;
 810                         reset-names = "reset";
 811                         interrupts = <75>;
 812                         fifo-depth = <32>;
 813                         fifo-watermark-aligned;
 814                         data-addr = <0>;
 815                         status = "disabled";
 816                 };
 817
 818                 vin_sysctl: vin_sysctl@19800000 {
 819                         compatible = "starfive,jh7110-vin";
 820                         reg = <0x0 0x19800000 0x0 0x10000>,
 821                                 <0x0 0x19810000 0x0 0x10000>,
 822                                 <0x0 0x19820000 0x0 0x10000>,
 823                                 <0x0 0x19840000 0x0 0x10000>,
 824                                 <0x0 0x19870000 0x0 0x30000>,
 825                                 <0x0 0x11840000 0x0 0x10000>,
 826                                 <0x0 0x17030000 0x0 0x10000>,
 827                                 <0x0 0x13020000 0x0 0x10000>;
 828                         reg-names = "csi2rx", "vclk", "vrst", "sctrl",
 829                                 "isp", "trst", "pmu", "syscrg";
 830                         clocks = <&clkisp JH7110_DOM4_APB_FUNC>,
 831                                  <&clkisp JH7110_U0_VIN_PCLK>,
 832                                  <&clkisp JH7110_U0_VIN_SYS_CLK>,
 833                                  <&clkisp JH7110_U0_ISPV2_TOP_WRAPPER_CLK_C>,
 834                                  <&clkisp JH7110_DVP_INV>,
 835                                  <&clkisp JH7110_U0_VIN_CLK_P_AXIWR>,
 836                                  <&clkisp JH7110_MIPI_RX0_PXL>,
 837                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF0>,
 838                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF1>,
 839                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF2>,
 840                                  <&clkisp JH7110_U0_VIN_PIXEL_CLK_IF3>,
 841                                  <&clkisp JH7110_U0_M31DPHY_CFGCLK_IN>,
 842                                  <&clkisp JH7110_U0_M31DPHY_REFCLK_IN>,
 843                                  <&clkisp JH7110_U0_M31DPHY_TXCLKESC_LAN0>,
 844                                  <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
 845                                  <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>;
 846                         clock-names = "clk_apb_func", "clk_pclk", "clk_sys_clk",
 847                                 "clk_wrapper_clk_c", "clk_dvp_inv", "clk_axiwr",
 848                                 "clk_mipi_rx0_pxl", "clk_pixel_clk_if0",
 849                                 "clk_pixel_clk_if1", "clk_pixel_clk_if2",
 850                                 "clk_pixel_clk_if3", "clk_m31dphy_cfgclk_in",
 851                                 "clk_m31dphy_refclk_in", "clk_m31dphy_txclkesc_lan0",
 852                                 "clk_ispcore_2x", "clk_isp_axi";
 853                         resets = <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_P>,
 854                                  <&rstgen RSTN_U0_ISPV2_TOP_WRAPPER_C>,
 855                                  <&rstgen RSTN_U0_VIN_N_PCLK>,
 856                                  <&rstgen RSTN_U0_VIN_N_SYS_CLK>,
 857                                  <&rstgen RSTN_U0_VIN_P_AXIRD>,
 858                                  <&rstgen RSTN_U0_VIN_P_AXIWR>,
 859                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF0>,
 860                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF1>,
 861                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF2>,
 862                                  <&rstgen RSTN_U0_VIN_N_PIXEL_CLK_IF3>,
 863                                  <&rstgen RSTN_U0_M31DPHY_HW>,
 864                                  <&rstgen RSTN_U0_M31DPHY_B09_ALWAYS_ON>,
 865                                  <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
 866                                  <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>;
 867                         reset-names = "rst_wrapper_p", "rst_wrapper_c", "rst_pclk",
 868                                 "rst_sys_clk", "rst_axird", "rst_axiwr", "rst_pixel_clk_if0",
 869                                 "rst_pixel_clk_if1", "rst_pixel_clk_if2", "rst_pixel_clk_if3",
 870                                 "rst_m31dphy_hw", "rst_m31dphy_b09_always_on",
 871                                 "rst_isp_top_n", "rst_isp_top_axi";
 872                         starfive,aon-syscon = <&aon_syscon 0x00>;
 873                         power-domains = <&pwrc JH7110_PD_ISP>;
 874                         /* irq nr: vin, isp, isp_csi, isp_scd, isp_csiline */
 875                         interrupts = <92 87 88 89 90>;
 876                         status = "disabled";
 877                 };
 878
 879                 jpu: jpu@11900000 {
 880                         compatible = "starfive,jpu";
 881                         reg = <0x0 0x13090000 0x0 0x300>;
 882                         interrupts = <14>;
 883                         clocks = <&clkgen JH7110_CODAJ12_CLK_AXI>,
 884                                  <&clkgen JH7110_CODAJ12_CLK_CORE>,
 885                                  <&clkgen JH7110_CODAJ12_CLK_APB>,
 886                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 887                         clock-names = "axi_clk", "core_clk",
 888                                       "apb_clk", "noc_bus";
 889                         resets = <&rstgen RSTN_U0_CODAJ12_AXI>,
 890                                  <&rstgen RSTN_U0_CODAJ12_CORE>,
 891                                  <&rstgen RSTN_U0_CODAJ12_APB>;
 892                         reset-names = "rst_axi", "rst_core", "rst_apb";
 893                         power-domains = <&pwrc JH7110_PD_VDEC>;
 894                         status = "disabled";
 895                 };
 896
 897                 vpu_dec: vpu_dec@130A0000 {
 898                         compatible = "starfive,vdec";
 899                         reg = <0x0 0x130A0000 0x0 0x10000>;
 900                         interrupts = <13>;
 901                         clocks = <&clkgen JH7110_WAVE511_CLK_AXI>,
 902                                  <&clkgen JH7110_WAVE511_CLK_BPU>,
 903                                  <&clkgen JH7110_WAVE511_CLK_VCE>,
 904                                  <&clkgen JH7110_WAVE511_CLK_APB>,
 905                                  <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>;
 906                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 907                                       "apb_clk", "noc_bus";
 908                         resets = <&rstgen RSTN_U0_WAVE511_AXI>,
 909                                 <&rstgen RSTN_U0_WAVE511_BPU>,
 910                                 <&rstgen RSTN_U0_WAVE511_VCE>,
 911                                 <&rstgen RSTN_U0_WAVE511_APB>,
 912                                 <&rstgen RSTN_U0_AXIMEM_128B_AXI>;
 913                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 914                                       "rst_apb", "rst_sram";
 915                         starfive,vdec_noc_ctrl;
 916                         power-domains = <&pwrc JH7110_PD_VDEC>;
 917                         status = "disabled";
 918                 };
 919
 920                 vpu_enc: vpu_enc@130B0000 {
 921                         compatible = "starfive,venc";
 922                         reg = <0x0 0x130B0000 0x0 0x10000>;
 923                         interrupts = <15>;
 924                         clocks = <&clkgen JH7110_WAVE420L_CLK_AXI>,
 925                                  <&clkgen JH7110_WAVE420L_CLK_BPU>,
 926                                  <&clkgen JH7110_WAVE420L_CLK_VCE>,
 927                                  <&clkgen JH7110_WAVE420L_CLK_APB>,
 928                                  <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>;
 929                         clock-names = "axi_clk", "bpu_clk", "vce_clk",
 930                                       "apb_clk", "noc_bus";
 931                         resets = <&rstgen RSTN_U0_WAVE420L_AXI>,
 932                                  <&rstgen RSTN_U0_WAVE420L_BPU>,
 933                                  <&rstgen RSTN_U0_WAVE420L_VCE>,
 934                                  <&rstgen RSTN_U0_WAVE420L_APB>,
 935                                  <&rstgen RSTN_U1_AXIMEM_128B_AXI>;
 936                         reset-names = "rst_axi", "rst_bpu", "rst_vce",
 937                                       "rst_apb", "rst_sram";
 938                         starfive,venc_noc_ctrl;
 939                         power-domains = <&pwrc JH7110_PD_VENC>;
 940                         status = "disabled";
 941                 };
 942
 943                 rstgen: reset-controller {
 944                         compatible = "starfive,jh7110-reset";
 945                         reg = <0x0 0x13020000 0x0 0x10000>,
 946                                 <0x0 0x10230000 0x0 0x10000>,
 947                                 <0x0 0x17000000 0x0 0x10000>,
 948                                 <0x0 0x19810000 0x0 0x10000>,
 949                                 <0x0 0x295C0000 0x0 0x10000>;
 950                         reg-names = "syscrg", "stgcrg", "aoncrg", "ispcrg", "voutcrg";
 951                         #reset-cells = <1>;
 952                         status = "okay";
 953                 };
 954
 955                 stmmac_axi_setup: stmmac-axi-config {
 956                         snps,wr_osr_lmt = <0xf>;
 957                         snps,rd_osr_lmt = <0xf>;
 958                         snps,blen = <256 128 64 32 0 0 0>;
 959                 };
 960
 961                 gmac0: ethernet@16030000 {
 962                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
 963                         reg = <0x0 0x16030000 0x0 0x10000>;
 964                         clock-names = "gtx",
 965                                 "tx",
 966                                 "ptp_ref",
 967                                 "stmmaceth",
 968                                 "pclk",
 969                                 "gtxc";
 970                         clocks = <&clkgen JH7110_GMAC0_GTXCLK>,
 971                                  <&clkgen JH7110_U0_GMAC5_CLK_TX>,
 972                                  <&clkgen JH7110_GMAC0_PTP>,
 973                                  <&clkgen JH7110_U0_GMAC5_CLK_AHB>,
 974                                  <&clkgen JH7110_U0_GMAC5_CLK_AXI>,
 975                                  <&clkgen JH7110_GMAC0_GTXC>;
 976                         resets = <&rstgen RSTN_U0_DW_GMAC5_AXI64_AHB>,
 977                                  <&rstgen RSTN_U0_DW_GMAC5_AXI64_AXI>;
 978                         reset-names = "ahb", "stmmaceth";
 979                         interrupts = <7>, <6>, <5> ;
 980                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
 981                         max-frame-size = <9000>;
 982                         phy-mode = "rgmii-id";
 983                         snps,multicast-filter-bins = <64>;
 984                         snps,perfect-filter-entries = <128>;
 985                         rx-fifo-depth = <2048>;
 986                         tx-fifo-depth = <2048>;
 987                         snps,fixed-burst;
 988                         snps,no-pbl-x8;
 989                         snps,force_thresh_dma_mode;
 990                         snps,axi-config = <&stmmac_axi_setup>;
 991                         snps,tso;
 992                         snps,en-tx-lpi-clockgating;
 993                         snps,en-lpi;
 994                         snps,write-requests = <4>;
 995                         snps,read-requests = <4>;
 996                         snps,burst-map = <0x7>;
 997                         snps,txpbl = <16>;
 998                         snps,rxpbl = <16>;
 999                         status = "disabled";
1000                 };
1001
1002                 gmac1: ethernet@16040000 {
1003                         compatible = "starfive,dwmac","snps,dwmac-5.10a";
1004                         reg = <0x0 0x16040000 0x0 0x10000>;
1005                         clock-names = "gtx",
1006                                 "tx",
1007                                 "ptp_ref",
1008                                 "stmmaceth",
1009                                 "pclk",
1010                                 "gtxc";
1011                         clocks = <&clkgen JH7110_GMAC1_GTXCLK>,
1012                                  <&clkgen JH7110_GMAC5_CLK_TX>,
1013                                  <&clkgen JH7110_GMAC5_CLK_PTP>,
1014                                  <&clkgen JH7110_GMAC5_CLK_AHB>,
1015                                  <&clkgen JH7110_GMAC5_CLK_AXI>,
1016                                  <&clkgen JH7110_GMAC1_GTXC>;
1017                         resets = <&rstgen RSTN_U1_DW_GMAC5_AXI64_H_N>,
1018                                  <&rstgen RSTN_U1_DW_GMAC5_AXI64_A_I>;
1019                         reset-names = "ahb", "stmmaceth";
1020                         interrupts = <78>, <77>, <76> ;
1021                         interrupt-names = "macirq", "eth_wake_irq", "eth_lpi";
1022                         max-frame-size = <9000>;
1023                         phy-mode = "rgmii-id";
1024                         snps,multicast-filter-bins = <64>;
1025                         snps,perfect-filter-entries = <128>;
1026                         rx-fifo-depth = <2048>;
1027                         tx-fifo-depth = <2048>;
1028                         snps,fixed-burst;
1029                         snps,no-pbl-x8;
1030                         snps,force_thresh_dma_mode;
1031                         snps,axi-config = <&stmmac_axi_setup>;
1032                         snps,tso;
1033                         snps,en-tx-lpi-clockgating;
1034                         snps,en-lpi;
1035                         snps,write-requests = <4>;
1036                         snps,read-requests = <4>;
1037                         snps,burst-map = <0x7>;
1038                         snps,txpbl = <16>;
1039                         snps,rxpbl = <16>;
1040                         status = "disabled";
1041                 };
1042
1043                 gpu: gpu@18000000 {
1044                         compatible = "img-gpu";
1045                         reg = <0x0 0x18000000 0x0 0x100000>,
1046                                 <0x0 0x130C000 0x0 0x10000>;
1047                         clocks = <&clkgen JH7110_GPU_CORE>,
1048                                  <&clkgen JH7110_GPU_CLK_APB>,
1049                                  <&clkgen JH7110_GPU_RTC_TOGGLE>,
1050                                  <&clkgen JH7110_GPU_CORE_CLK>,
1051                                  <&clkgen JH7110_GPU_SYS_CLK>,
1052                                  <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>;
1053                         clock-names = "clk_bv", "clk_apb", "clk_rtc",
1054                                         "clk_core", "clk_sys", "clk_axi";
1055                         resets = <&rstgen RSTN_U0_IMG_GPU_APB>,
1056                                  <&rstgen RSTN_U0_IMG_GPU_DOMA>;
1057                         reset-names = "rst_apb", "rst_doma";
1058                         power-domains = <&pwrc JH7110_PD_GPUA>;
1059                         interrupts = <82>;
1060                         current-clock = <8000000>;
1061                         status = "disabled";
1062                 };
1063
1064                 can0: can@130d0000 {
1065                         compatible = "starfive,jh7110-can", "ipms,can";
1066                         reg = <0x0 0x130d0000 0x0 0x1000>;
1067                         interrupts = <112>;
1068                         clocks = <&clkgen JH7110_CAN0_CTRL_CLK_APB>,
1069                                  <&clkgen JH7110_CAN0_CTRL_CLK_CAN>,
1070                                  <&clkgen JH7110_CAN0_CTRL_CLK_TIMER>;
1071                         clock-names = "apb_clk", "core_clk", "timer_clk";
1072                         resets = <&rstgen RSTN_U0_CAN_CTRL_APB>,
1073                                  <&rstgen RSTN_U0_CAN_CTRL_CORE>,
1074                                  <&rstgen RSTN_U0_CAN_CTRL_TIMER>;
1075                         reset-names = "rst_apb", "rst_core", "rst_timer";
1076                         frequency = <40000000>;
1077                         starfive,sys-syscon = <&sys_syscon 0x10 0x3 0x8>;
1078                         syscon,can_or_canfd = <0>;
1079                         status = "disabled";
1080                 };
1081
1082                 can1: can@130e0000 {
1083                         compatible = "starfive,jh7110-can", "ipms,can";
1084                         reg = <0x0 0x130e0000 0x0 0x1000>;
1085                         interrupts = <113>;
1086                         clocks = <&clkgen JH7110_CAN1_CTRL_CLK_APB>,
1087                                  <&clkgen JH7110_CAN1_CTRL_CLK_CAN>,
1088                                  <&clkgen JH7110_CAN1_CTRL_CLK_TIMER>;
1089                         clock-names = "apb_clk", "core_clk", "timer_clk";
1090                         resets = <&rstgen RSTN_U1_CAN_CTRL_APB>,
1091                                  <&rstgen RSTN_U1_CAN_CTRL_CORE>,
1092                                  <&rstgen RSTN_U1_CAN_CTRL_TIMER>;
1093                         reset-names = "rst_apb", "rst_core", "rst_timer";
1094                         frequency = <40000000>;
1095                         starfive,sys-syscon = <&sys_syscon 0x88 0x12 0x40000>;
1096                         syscon,can_or_canfd = <1>;
1097                         status = "disabled";
1098                 };
1099
1100                 tdm: tdm@10090000 {
1101                         compatible = "starfive,jh7110-tdm";
1102                         reg = <0x0 0x10090000 0x0 0x1000>;
1103                         reg-names = "tdm";
1104                         clocks = <&clkgen JH7110_AHB0>,
1105                                  <&clkgen JH7110_TDM_CLK_AHB>,
1106                                  <&clkgen JH7110_APB0>,
1107                                  <&clkgen JH7110_TDM_CLK_APB>,
1108                                  <&clkgen JH7110_TDM_INTERNAL>,
1109                                  <&tdm_ext>,
1110                                  <&clkgen JH7110_TDM_CLK_TDM>,
1111                                  <&clkgen JH7110_MCLK_INNER>;
1112                         clock-names = "clk_ahb0", "clk_tdm_ahb",
1113                                       "clk_apb0", "clk_tdm_apb",
1114                                       "clk_tdm_internal", "clk_tdm_ext",
1115                                       "clk_tdm", "mclk_inner";
1116                         resets = <&rstgen RSTN_U0_TDM16SLOT_AHB>,
1117                                  <&rstgen RSTN_U0_TDM16SLOT_APB>,
1118                                  <&rstgen RSTN_U0_TDM16SLOT_TDM>;
1119                         reset-names = "tdm_ahb", "tdm_apb", "tdm_rst";
1120                         dmas = <&dma 20 1>, <&dma 21 1>;
1121                         dma-names = "rx","tx";
1122                         #sound-dai-cells = <0>;
1123                         status = "disabled";
1124                 };
1125
1126                 spdif0: spdif0@100a0000 {
1127                         compatible = "starfive,jh7110-spdif";
1128                         reg = <0x0 0x100a0000 0x0 0x1000>;
1129                         clocks = <&clkgen JH7110_SPDIF_CLK_APB>,
1130                                  <&clkgen JH7110_SPDIF_CLK_CORE>,
1131                                  <&clkgen JH7110_AUDIO_ROOT>,
1132                                  <&clkgen JH7110_MCLK_INNER>,
1133                                  <&mclk_ext>, <&clkgen JH7110_MCLK>;
1134                         clock-names = "spdif-apb", "spdif-core",
1135                                       "audroot", "mclk_inner",
1136                                       "mclk_ext", "mclk";
1137                         resets = <&rstgen RSTN_U0_CDNS_SPDIF_APB>;
1138                         reset-names = "rst_apb";
1139                         interrupts = <84>;
1140                         interrupt-names = "tx";
1141                         #sound-dai-cells = <0>;
1142                         status = "disabled";
1143                 };
1144
1145                 pwmdac: pwmdac@100b0000 {
1146                         compatible = "starfive,jh7110-pwmdac";
1147                         reg = <0x0 0x100b0000 0x0 0x1000>;
1148                         clocks = <&clkgen JH7110_APB0>,
1149                                  <&clkgen JH7110_PWMDAC_CLK_APB>,
1150                                  <&clkgen JH7110_PWMDAC_CLK_CORE>;
1151                         clock-names = "apb0", "pwmdac-apb", "pwmdac-core";
1152                         resets = <&rstgen RSTN_U0_PWMDAC_APB>;
1153                         reset-names = "rst-apb";
1154                         dmas = <&dma 22 1>;
1155                         dma-names = "tx";
1156                         #sound-dai-cells = <0>;
1157                         status = "disabled";
1158                 };
1159
1160                 i2stx: i2stx@100c0000 {
1161                         compatible = "snps,designware-i2stx";
1162                         reg = <0x0 0x100c0000 0x0 0x1000>;
1163                         interrupt-names = "tx";
1164                         #sound-dai-cells = <0>;
1165                         dmas = <&dma 28 1>;
1166                         dma-names = "rx";
1167                         status = "disabled";
1168                 };
1169
1170                 pdm: pdm@100d0000 {
1171                         compatible = "starfive,jh7110-pdm";
1172                         reg = <0x0 0x100d0000 0x0 0x1000>;
1173                         reg-names = "pdm";
1174                         clocks = <&clkgen JH7110_PDM_CLK_DMIC>,
1175                                  <&clkgen JH7110_APB0>,
1176                                  <&clkgen JH7110_PDM_CLK_APB>,
1177                                  <&clkgen JH7110_MCLK>,
1178                                  <&mclk_ext>;
1179                         clock-names = "pdm_mclk", "clk_apb0",
1180                                       "pdm_apb", "clk_mclk",
1181                                       "mclk_ext";
1182                         resets = <&rstgen RSTN_U0_PDM_4MIC_DMIC>,
1183                                  <&rstgen RSTN_U0_PDM_4MIC_APB>;
1184                         reset-names = "pdm_dmic", "pdm_apb";
1185                         #sound-dai-cells = <0>;
1186                 };
1187
1188                 i2srx_mst: i2srx_mst@100e0000 {
1189                         compatible = "starfive,jh7110-i2srx-master";
1190                         reg = <0x0 0x100e0000 0x0 0x1000>;
1191                         clocks = <&clkgen JH7110_APB0>,
1192                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1193                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1194                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1195                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1196                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>;
1197                         clock-names = "apb0", "i2srx_apb",
1198                                       "i2srx_bclk_mst", "i2srx_lrck_mst",
1199                                       "i2srx_bclk", "i2srx_lrck";
1200                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1201                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1202                         reset-names = "rst_apb_rx", "rst_bclk_rx";
1203                         dmas = <&dma 24 1>;
1204                         dma-names = "rx";
1205                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1206                         #sound-dai-cells = <0>;
1207                         status = "disabled";
1208                 };
1209
1210                 i2srx_3ch: i2srx_3ch@100e0000 {
1211                         compatible = "starfive,jh7110-i2srx", "snps,designware-i2s";
1212                         reg = <0x0 0x100e0000 0x0 0x1000>;
1213                         clocks = <&clkgen JH7110_APB0>,
1214                                  <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
1215                                  <&clkgen JH7110_AUDIO_ROOT>,
1216                                  <&clkgen JH7110_MCLK_INNER>,
1217                                  <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
1218                                  <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
1219                                  <&clkgen JH7110_I2SRX0_3CH_BCLK>,
1220                                  <&clkgen JH7110_I2SRX0_3CH_LRCK>,
1221                                  <&clkgen JH7110_MCLK>,
1222                                  <&i2srx_bclk_ext>,
1223                                  <&i2srx_lrck_ext>;
1224                         clock-names = "apb0", "3ch-apb",
1225                                       "audioroot", "mclk-inner",
1226                                       "bclk_mst", "3ch-lrck",
1227                                       "rx-bclk", "rx-lrck",
1228                                       "mclk", "bclk-ext",
1229                                       "lrck-ext";
1230                         resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
1231                                  <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
1232                         dmas = <&dma 24 1>;
1233                         dma-names = "rx";
1234                         starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
1235                         #sound-dai-cells = <0>;
1236                         status = "disabled";
1237                 };
1238
1239                 i2stx_4ch0: i2stx_4ch0@120b0000 {
1240                         compatible = "starfive,jh7110-i2stx-4ch0", "snps,designware-i2s";
1241                         reg = <0x0 0x120b0000 0x0 0x1000>;
1242                         clocks = <&clkgen JH7110_MCLK_INNER>,
1243                                  <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
1244                                  <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
1245                                  <&clkgen JH7110_MCLK>,
1246                                  <&clkgen JH7110_I2STX0_4CHBCLK>,
1247                                  <&clkgen JH7110_I2STX0_4CHLRCK>,
1248                                  <&clkgen JH7110_I2STX0_4CHCLK_APB>,
1249                                  <&mclk_ext>;
1250                         clock-names = "inner", "bclk-mst",
1251                                         "lrck-mst", "mclk",
1252                                         "bclk0", "lrck0",
1253                                         "i2s_apb", "mclk_ext";
1254                         resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
1255                                  <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
1256                         reset-names = "rst_apb", "rst_bclk";
1257                         dmas = <&dma 47 1>;
1258                         dma-names = "tx";
1259                         #sound-dai-cells = <0>;
1260                         status = "disabled";
1261                 };
1262
1263                 i2stx_4ch1: i2stx_4ch1@120c0000 {
1264                         compatible = "starfive,jh7110-i2stx-4ch1", "snps,designware-i2s";
1265                         reg = <0x0 0x120c0000 0x0 0x1000>;
1266                         clocks = <&clkgen JH7110_AUDIO_ROOT>,
1267                                  <&clkgen JH7110_MCLK_INNER>,
1268                                  <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
1269                                  <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
1270                                  <&clkgen JH7110_MCLK>,
1271                                  <&clkgen JH7110_I2STX1_4CHBCLK>,
1272                                  <&clkgen JH7110_I2STX1_4CHLRCK>,
1273                                  <&clkgen JH7110_MCLK_OUT>,
1274                                  <&clkgen JH7110_APB0>,
1275                                  <&clkgen JH7110_I2STX1_4CHCLK_APB>,
1276                                  <&mclk_ext>,
1277                                  <&i2stx_bclk_ext>,
1278                                  <&i2stx_lrck_ext>;
1279                         clock-names = "audroot", "mclk_inner", "bclk_mst",
1280                                       "lrck_mst", "mclk", "4chbclk",
1281                                       "4chlrck", "mclk_out",
1282                                       "apb0", "clk_apb",
1283                                       "mclk_ext", "bclk_ext", "lrck_ext";
1284                         resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
1285                                  <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
1286                         dmas = <&dma 48 1>;
1287                         dma-names = "tx";
1288                         #sound-dai-cells = <0>;
1289                         status = "disabled";
1290                 };
1291
1292                 ptc: pwm@120d0000 {
1293                         compatible = "starfive,jh7110-pwm";
1294                         reg = <0x0 0x120d0000 0x0 0x10000>;
1295                         reg-names = "control";
1296                         clocks = <&clkgen JH7110_PWM_CLK_APB>;
1297                         resets = <&rstgen RSTN_U0_PWM_8CH_APB>;
1298                         starfive,approx-freq = <2000000>;
1299                         #pwm-cells=<3>;
1300                         starfive,npwm = <8>;
1301                         status = "disabled";
1302                 };
1303
1304                 spdif_transmitter: spdif_transmitter {
1305                         compatible = "linux,spdif-dit";
1306                         #sound-dai-cells = <0>;
1307                         status = "disabled";
1308                 };
1309
1310                 pwmdac_codec: pwmdac-transmitter {
1311                         compatible = "starfive,jh7110-pwmdac-dit";
1312                         #sound-dai-cells = <0>;
1313                         status = "disabled";
1314                 };
1315
1316                 dmic_codec: dmic_codec {
1317                         compatible = "dmic-codec";
1318                         #sound-dai-cells = <0>;
1319                         status = "disabled";
1320                 };
1321
1322                 spi0: spi@10060000 {
1323                         compatible = "arm,pl022", "arm,primecell";
1324                         reg = <0x0 0x10060000 0x0 0x10000>;
1325                         clocks = <&clkgen JH7110_SPI0_CLK_APB>;
1326                         clock-names = "apb_pclk";
1327                         resets = <&rstgen RSTN_U0_SSP_SPI_APB>;
1328                         reset-names = "rst_apb";
1329                         interrupts = <38>;
1330                         /* shortage of dma channel that not be used */
1331                         /*dmas = <&dma 14 1>, <&dma 15 1>;*/
1332                         /*dma-names = "rx","tx";*/
1333                         arm,primecell-periphid = <0x00041022>;
1334                         num-cs = <1>;
1335                         #address-cells = <1>;
1336                         #size-cells = <0>;
1337                         status = "disabled";
1338                 };
1339
1340                 spi1: spi@10070000 {
1341                         compatible = "arm,pl022", "arm,primecell";
1342                         reg = <0x0 0x10070000 0x0 0x10000>;
1343                         clocks = <&clkgen JH7110_SPI1_CLK_APB>;
1344                         clock-names = "apb_pclk";
1345                         resets = <&rstgen RSTN_U1_SSP_SPI_APB>;
1346                         reset-names = "rst_apb";
1347                         interrupts = <39>;
1348                         /* shortage of dma channel that not be used */
1349                         /*dmas = <&dma 16 1>, <&dma 17 1>;*/
1350                         /*dma-names = "rx","tx";*/
1351                         arm,primecell-periphid = <0x00041022>;
1352                         num-cs = <1>;
1353                         #address-cells = <1>;
1354                         #size-cells = <0>;
1355                         status = "disabled";
1356                 };
1357
1358                 spi2: spi@10080000 {
1359                         compatible = "arm,pl022", "arm,primecell";
1360                         reg = <0x0 0x10080000 0x0 0x10000>;
1361                         clocks = <&clkgen JH7110_SPI2_CLK_APB>;
1362                         clock-names = "apb_pclk";
1363                         resets = <&rstgen RSTN_U2_SSP_SPI_APB>;
1364                         reset-names = "rst_apb";
1365                         interrupts = <40>;
1366                         /* shortage of dma channel that not be used */
1367                         /*dmas = <&dma 18 1>, <&dma 19 1>;*/
1368                         /*dma-names = "rx","tx";*/
1369                         arm,primecell-periphid = <0x00041022>;
1370                         num-cs = <1>;
1371                         #address-cells = <1>;
1372                         #size-cells = <0>;
1373                         status = "disabled";
1374                 };
1375
1376                 spi3: spi@12070000 {
1377                         compatible = "arm,pl022", "arm,primecell";
1378                         reg = <0x0 0x12070000 0x0 0x10000>;
1379                         clocks = <&clkgen JH7110_SPI3_CLK_APB>;
1380                         clock-names = "apb_pclk";
1381                         resets = <&rstgen RSTN_U3_SSP_SPI_APB>;
1382                         reset-names = "rst_apb";
1383                         interrupts = <52>;
1384                         /* shortage of dma channel that not be used */
1385                         /*dmas = <&dma 39 1>, <&dma 40 1>;*/
1386                         /*dma-names = "rx","tx";*/
1387                         arm,primecell-periphid = <0x00041022>;
1388                         num-cs = <1>;
1389                         #address-cells = <1>;
1390                         #size-cells = <0>;
1391                         status = "disabled";
1392                 };
1393
1394                 spi4: spi@12080000 {
1395                         compatible = "arm,pl022", "arm,primecell";
1396                         reg = <0x0 0x12080000 0x0 0x10000>;
1397                         clocks = <&clkgen JH7110_SPI4_CLK_APB>;
1398                         clock-names = "apb_pclk";
1399                         resets = <&rstgen RSTN_U4_SSP_SPI_APB>;
1400                         reset-names = "rst_apb";
1401                         interrupts = <53>;
1402                         /* shortage of dma channel that not be used */
1403                         /*dmas = <&dma 41 1>, <&dma 42 1>;*/
1404                         /*dma-names = "rx","tx";*/
1405                         arm,primecell-periphid = <0x00041022>;
1406                         num-cs = <1>;
1407                         #address-cells = <1>;
1408                         #size-cells = <0>;
1409                         status = "disabled";
1410                 };
1411
1412                 spi5: spi@12090000 {
1413                         compatible = "arm,pl022", "arm,primecell";
1414                         reg = <0x0 0x12090000 0x0 0x10000>;
1415                         clocks = <&clkgen JH7110_SPI5_CLK_APB>;
1416                         clock-names = "apb_pclk";
1417                         resets = <&rstgen RSTN_U5_SSP_SPI_APB>;
1418                         reset-names = "rst_apb";
1419                         interrupts = <54>;
1420                         /* shortage of dma channel that not be used */
1421                         /*dmas = <&dma 43 1>, <&dma 44 1>;*/
1422                         /*dma-names = "rx","tx";*/
1423                         arm,primecell-periphid = <0x00041022>;
1424                         num-cs = <1>;
1425                         #address-cells = <1>;
1426                         #size-cells = <0>;
1427                         status = "disabled";
1428                 };
1429
1430                 spi6: spi@120A0000 {
1431                         compatible = "arm,pl022", "arm,primecell";
1432                         reg = <0x0 0x120A0000 0x0 0x10000>;
1433                         clocks = <&clkgen JH7110_SPI6_CLK_APB>;
1434                         clock-names = "apb_pclk";
1435                         resets = <&rstgen RSTN_U6_SSP_SPI_APB>;
1436                         reset-names = "rst_apb";
1437                         interrupts = <55>;
1438                         /* shortage of dma channel that not be used */
1439                         /*dmas = <&dma 45 1>, <&dma 46 1>;*/
1440                         /*dma-names = "rx","tx";*/
1441                         arm,primecell-periphid = <0x00041022>;
1442                         num-cs = <1>;
1443                         #address-cells = <1>;
1444                         #size-cells = <0>;
1445                         status = "disabled";
1446                 };
1447
1448                 pcie0: pcie@2B000000 {
1449                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1450                         #address-cells = <3>;
1451                         #size-cells = <2>;
1452                         #interrupt-cells = <1>;
1453                         reg = <0x0 0x2B000000 0x0 0x1000000
1454                                0x9 0x40000000 0x0 0x10000000>;
1455                         reg-names = "reg", "config";
1456                         device_type = "pci";
1457                         starfive,stg-syscon = <&stg_syscon 0xc0 0xc4 0x130 0x1b8>;
1458                         bus-range = <0x0 0xff>;
1459                         ranges = <0x82000000  0x0 0x30000000  0x0 0x30000000 0x0 0x08000000>,
1460                                  <0xc3000000  0x9 0x00000000  0x9 0x00000000 0x0 0x40000000>;
1461                         msi-parent = <&plic>;
1462                         interrupts = <56>;
1463                         interrupt-controller;
1464                         interrupt-names = "msi";
1465                         interrupt-parent = <&plic>;
1466                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1467                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1468                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1469                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1470                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1471                         resets = <&rstgen RSTN_U0_PLDA_PCIE_AXI_MST0>,
1472                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV0>,
1473                                  <&rstgen RSTN_U0_PLDA_PCIE_AXI_SLV>,
1474                                  <&rstgen RSTN_U0_PLDA_PCIE_BRG>,
1475                                  <&rstgen RSTN_U0_PLDA_PCIE_CORE>,
1476                                  <&rstgen RSTN_U0_PLDA_PCIE_APB>;
1477                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1478                                       "rst_brg", "rst_core", "rst_apb";
1479                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1480                                  <&clkgen JH7110_PCIE0_CLK_TL>,
1481                                  <&clkgen JH7110_PCIE0_CLK_AXI_MST0>,
1482                                  <&clkgen JH7110_PCIE0_CLK_APB>;
1483                         clock-names = "noc", "tl", "axi_mst0", "apb";
1484                         status = "disabled";
1485                 };
1486
1487                 pcie1: pcie@2C000000 {
1488                         compatible = "starfive,jh7110-pcie","plda,pci-xpressrich3-axi";
1489                         #address-cells = <3>;
1490                         #size-cells = <2>;
1491                         #interrupt-cells = <1>;
1492                         reg = <0x0 0x2C000000 0x0 0x1000000
1493                                0x9 0xc0000000 0x0 0x10000000>;
1494                         reg-names = "reg", "config";
1495                         device_type = "pci";
1496                         starfive,stg-syscon = <&stg_syscon 0x270 0x274 0x2e0 0x368>;
1497                         bus-range = <0x0 0xff>;
1498                         ranges = <0x82000000  0x0 0x38000000  0x0 0x38000000 0x0 0x08000000>,
1499                                  <0xc3000000  0x9 0x80000000  0x9 0x80000000 0x0 0x40000000>;
1500                         msi-parent = <&plic>;
1501                         interrupts = <57>;
1502                         interrupt-controller;
1503                         interrupt-names = "msi";
1504                         interrupt-parent = <&plic>;
1505                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
1506                         interrupt-map = <0x0 0x0 0x0 0x1 &plic 0x1>,
1507                                         <0x0 0x0 0x0 0x2 &plic 0x2>,
1508                                         <0x0 0x0 0x0 0x3 &plic 0x3>,
1509                                         <0x0 0x0 0x0 0x4 &plic 0x4>;
1510                         resets = <&rstgen RSTN_U1_PLDA_PCIE_AXI_MST0>,
1511                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV0>,
1512                                  <&rstgen RSTN_U1_PLDA_PCIE_AXI_SLV>,
1513                                  <&rstgen RSTN_U1_PLDA_PCIE_BRG>,
1514                                  <&rstgen RSTN_U1_PLDA_PCIE_CORE>,
1515                                  <&rstgen RSTN_U1_PLDA_PCIE_APB>;
1516                         reset-names = "rst_mst0", "rst_slv0", "rst_slv",
1517                                       "rst_brg", "rst_core", "rst_apb";
1518                         clocks = <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
1519                                  <&clkgen JH7110_PCIE1_CLK_TL>,
1520                                  <&clkgen JH7110_PCIE1_CLK_AXI_MST0>,
1521                                  <&clkgen JH7110_PCIE1_CLK_APB>;
1522                         clock-names = "noc", "tl", "axi_mst0", "apb";
1523                         status = "disabled";
1524                 };
1525
1526                 mailbox_contrl0: mailbox@0 {
1527                         compatible = "starfive,mail_box";
1528                         reg = <0x0 0x13060000 0x0 0x0001000>;
1529                         clocks = <&clkgen JH7110_MAILBOX_CLK_APB>;
1530                         clock-names = "clk_apb";
1531                         resets = <&rstgen RSTN_U0_MAILBOX_RRESETN>;
1532                         reset-names = "mbx_rre";
1533                         interrupts = <26 27>;
1534                         #mbox-cells = <2>;
1535                         status = "disabled";
1536                 };
1537
1538                 mailbox_client0: mailbox_client@0 {
1539                         compatible = "starfive,mailbox-test";
1540                         mbox-names = "rx", "tx";
1541                         mboxes = <&mailbox_contrl0 0 1>,<&mailbox_contrl0 1 0>;
1542                         status = "disabled";
1543                 };
1544
1545                 display: display-subsystem {
1546                         compatible = "starfive,jh7110-display","verisilicon,display-subsystem";
1547                         ports = <&dc_out_dpi0>;
1548                         status = "disabled";
1549                 };
1550
1551                 dssctrl: dssctrl@295B0000 {
1552                         compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon";
1553                         reg = <0 0x295B0000 0 0x90>;
1554                 };
1555
1556                 tda988x_pin: tda988x_pin {
1557                         compatible = "starfive,tda998x_rgb_pin";
1558                         status = "disabled";
1559                 };
1560
1561                 rgb_output: rgb-output {
1562                         compatible = "starfive,jh7110-rgb_output","verisilicon,rgb-encoder";
1563                         //verisilicon,dss-syscon = <&dssctrl>;
1564                         //verisilicon,mux-mask = <0x70 0x380>;
1565                         //verisilicon,mux-val = <0x40 0x280>;
1566                         status = "disabled";
1567                 };
1568
1569                 dc8200: dc8200@29400000 {
1570                         compatible = "starfive,jh7110-dc8200","verisilicon,dc8200";
1571                         verisilicon,dss-syscon = <&dssctrl>;//20220624 panel syscon
1572                         reg = <0x0 0x29400000 0x0 0x100>,
1573                               <0x0 0x29400800 0x0 0x2000>,
1574                               <0x0 0x17030000 0x0 0x1000>;
1575                         interrupts = <95>;
1576                         status = "disabled";
1577                         clocks = <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
1578                         <&clkgen JH7110_VOUT_SRC>,
1579                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1580                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
1581                         <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
1582                         <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
1583                         <&clkvout JH7110_U0_DC8200_CLK_AXI>,
1584                         <&clkvout JH7110_U0_DC8200_CLK_CORE>,
1585                         <&clkvout JH7110_U0_DC8200_CLK_AHB>,
1586                         <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
1587                         <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
1588                         <&hdmitx0_pixelclk>,
1589                         <&clkvout JH7110_DC8200_PIX0>,
1590                         <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
1591                         <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
1592                         clock-names = "noc_disp","vout_src",
1593                            "top_vout_axi","top_vout_ahb",
1594                            "pix_clk","vout_pix1",
1595                            "axi_clk","core_clk","vout_ahb",
1596                            "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
1597                            "dc8200_pix0_out","dc8200_pix1_out";
1598                         resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
1599                                  <&rstgen RSTN_U0_DC8200_AXI>,
1600                                  <&rstgen RSTN_U0_DC8200_AHB>,
1601                                  <&rstgen RSTN_U0_DC8200_CORE>,
1602                                  <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>;
1603                         reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
1604                                         "rst_noc_disp";
1605                 };
1606
1607                 dsi_output: dsi-output {
1608                         compatible = "starfive,jh7110-display-encoder","verisilicon,dsi-encoder";
1609                         status = "disabled";
1610                 };
1611
1612                 mipi_dphy: mipi-dphy@295e0000{
1613                         compatible = "starfive,jh7110-mipi-dphy-tx","m31,mipi-dphy-tx";
1614                         reg = <0x0 0x295e0000 0x0 0x10000>;
1615                         clocks = <&clkvout JH7110_U0_MIPITX_DPHY_CLK_TXESC>;
1616                         clock-names = "dphy_txesc";
1617                         resets = <&rstgen RSTN_U0_MIPITX_DPHY_SYS>,
1618                                  <&rstgen RSTN_U0_MIPITX_DPHY_TXBYTEHS>;
1619                         reset-names = "dphy_sys", "dphy_txbytehs";
1620                         #phy-cells = <0>;
1621                         status = "disabled";
1622                 };
1623
1624                  mipi_dsi: mipi@295d0000 {
1625                         compatible = "starfive,jh7110-mipi_dsi","cdns,dsi";
1626                         reg = <0x0 0x295d0000 0x0 0x10000>;
1627                         interrupts = <98>;
1628                         reg-names = "dsi";
1629                         clocks = <&clkvout JH7110_U0_CDNS_DSITX_CLK_SYS>,
1630                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_APB>,
1631                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_TXESC>,
1632                                  <&clkvout JH7110_U0_CDNS_DSITX_CLK_DPI>;
1633                         clock-names = "sys", "apb", "txesc", "dpi";
1634                         resets = <&rstgen RSTN_U0_CDNS_DSITX_DPI>,
1635                                  <&rstgen RSTN_U0_CDNS_DSITX_APB>,
1636                                  <&rstgen RSTN_U0_CDNS_DSITX_RXESC>,
1637                                  <&rstgen RSTN_U0_CDNS_DSITX_SYS>,
1638                                  <&rstgen RSTN_U0_CDNS_DSITX_TXBYTEHS>,
1639                                  <&rstgen RSTN_U0_CDNS_DSITX_TXESC>;
1640                         reset-names = "dsi_dpi", "dsi_apb", "dsi_rxesc",
1641                                         "dsi_sys", "dsi_txbytehs", "dsi_txesc";
1642                         phys = <&mipi_dphy>;
1643                         phy-names = "dphy";
1644                         status = "disabled";
1645
1646                         port {
1647                                 dsi_out_port: endpoint@0 {
1648                                         remote-endpoint = <&panel_dsi_port>;
1649                                 };
1650                                 dsi_in_port: endpoint@1 {
1651                                         remote-endpoint = <&mipi_out>;
1652                                 };
1653                         };
1654
1655                         mipi_panel: panel@0 {
1656                                 /*compatible = "";*/
1657                                 status = "okay";
1658                         };
1659                 };
1660
1661                 hdmi: hdmi@29590000 {
1662                         compatible = "starfive,jh7110-hdmi","inno,hdmi";
1663                         reg = <0x0 0x29590000 0x0 0x4000>;
1664                         interrupts = <99>;
1665                         /*interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;*/
1666                         /*clocks = <&cru  PCLK_HDMI>;*/
1667                         /*clock-names = "pclk";*/
1668                         /*pinctrl-names = "default";*/
1669                         /*pinctrl-0 = <&hdmi_ctl>;*/
1670                         status = "disabled";
1671                         clocks = <&clkvout JH7110_U0_HDMI_TX_CLK_SYS>,
1672                                  <&clkvout JH7110_U0_HDMI_TX_CLK_MCLK>,
1673                                  <&clkvout JH7110_U0_HDMI_TX_CLK_BCLK>,
1674                                  <&hdmitx0_pixelclk>;
1675                         clock-names = "sysclk", "mclk","bclk","pclk";
1676                         resets = <&rstgen RSTN_U0_HDMI_TX_HDMI>;
1677                         reset-names = "hdmi_tx";
1678                         #sound-dai-cells = <0>;
1679                 };
1680
1681                 sound: snd-card {
1682                         compatible = "simple-audio-card";
1683                         simple-audio-card,name = "Starfive-Multi-Sound-Card";
1684                         #address-cells = <1>;
1685                         #size-cells = <0>;
1686                 };
1687
1688                 co_process: e24@0 {
1689                         compatible = "starfive,e24";
1690                         reg = <0x0 0xc0110000 0x0 0x00001000>,
1691                                 <0x0 0xc0111000 0x0 0x0001f000>;
1692                         reg-names = "ecmd", "espace";
1693                         clocks = <&clkgen JH7110_E2_RTC_CLK>,
1694                                  <&clkgen JH7110_E2_CLK_CORE>,
1695                                  <&clkgen JH7110_E2_CLK_DBG>;
1696                         clock-names = "clk_rtc", "clk_core", "clk_dbg";
1697                         resets = <&rstgen RSTN_U0_E24_CORE>;
1698                         reset-names = "e24_core";
1699                         starfive,stg-syscon = <&stg_syscon>;
1700                         interrupt-parent = <&plic>;
1701                         firmware-name = "e24_elf";
1702                         irq-mode = <1>;
1703                         mbox-names = "tx", "rx";
1704                         mboxes = <&mailbox_contrl0 0 2>,<&mailbox_contrl0 2 0>;
1705                         #address-cells = <1>;
1706                         #size-cells = <1>;
1707                         ranges = <0xc0000000 0x0 0xc0000000 0x200000>;
1708                         status = "disabled";
1709                         dsp@0 {};
1710                 };
1711
1712                 xrp: xrp@0 {
1713                         compatible = "cdns,xrp";
1714                         reg = <0x0  0x10230000 0x0 0x00010000
1715                                 0x0  0x10240000 0x0 0x00010000>;
1716                         memory-region = <&xrp_reserved>;
1717                         clocks = <&clkgen JH7110_HIFI4_CLK_CORE>;
1718                         clock-names = "core_clk";
1719                         resets = <&rstgen RSTN_U0_HIFI4_CORE>,
1720                                  <&rstgen RSTN_U0_HIFI4_AXI>;
1721                         reset-names = "rst_core","rst_axi";
1722                         starfive,stg-syscon = <&stg_syscon>;
1723                         firmware-name = "hifi4_elf";
1724                         #address-cells = <1>;
1725                         #size-cells = <1>;
1726                         ranges = <0x40000000 0x0 0x20000000 0x040000
1727                                 0xf0000000 0x0 0xf0000000 0x03000000>;
1728                         status = "disabled";
1729                         dsp@0 {
1730                         };
1731                 };
1732
1733                 starfive_cpufreq: starfive,jh7110-cpufreq {
1734                         compatible = "starfive,jh7110-cpufreq";
1735                         clocks = <&clkgen JH7110_CPU_CORE>;
1736                         clock-names = "cpu_clk";
1737                 };
1738         };
1739 };