arch/riscv/boot/dts/starfive/jh7100.dtsi

   1 // SPDX-License-Identifier: GPL-2.0 OR MIT
   2 /*
   3  * Copyright (C) 2021 StarFive Technology Co., Ltd.
   4  * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
   5  */
   6
   7 /dts-v1/;
   8 #include <dt-bindings/clock/starfive-jh7100.h>
   9 #include <dt-bindings/reset/starfive-jh7100.h>
  10
  11 / {
  12         compatible = "starfive,jh7100";
  13         #address-cells = <2>;
  14         #size-cells = <2>;
  15
  16         cpus {
  17                 #address-cells = <1>;
  18                 #size-cells = <0>;
  19
  20                 U74_0: cpu@0 {
  21                         compatible = "sifive,u74-mc", "riscv";
  22                         reg = <0>;
  23                         d-cache-block-size = <64>;
  24                         d-cache-sets = <64>;
  25                         d-cache-size = <32768>;
  26                         d-tlb-sets = <1>;
  27                         d-tlb-size = <32>;
  28                         device_type = "cpu";
  29                         i-cache-block-size = <64>;
  30                         i-cache-sets = <64>;
  31                         i-cache-size = <32768>;
  32                         i-tlb-sets = <1>;
  33                         i-tlb-size = <32>;
  34                         mmu-type = "riscv,sv39";
  35                         riscv,isa = "rv64imafdc";
  36                         tlb-split;
  37
  38                         cpu0_intc: interrupt-controller {
  39                                 compatible = "riscv,cpu-intc";
  40                                 interrupt-controller;
  41                                 #interrupt-cells = <1>;
  42                         };
  43                 };
  44
  45                 U74_1: cpu@1 {
  46                         compatible = "sifive,u74-mc", "riscv";
  47                         reg = <1>;
  48                         d-cache-block-size = <64>;
  49                         d-cache-sets = <64>;
  50                         d-cache-size = <32768>;
  51                         d-tlb-sets = <1>;
  52                         d-tlb-size = <32>;
  53                         device_type = "cpu";
  54                         i-cache-block-size = <64>;
  55                         i-cache-sets = <64>;
  56                         i-cache-size = <32768>;
  57                         i-tlb-sets = <1>;
  58                         i-tlb-size = <32>;
  59                         mmu-type = "riscv,sv39";
  60                         riscv,isa = "rv64imafdc";
  61                         tlb-split;
  62
  63                         cpu1_intc: interrupt-controller {
  64                                 compatible = "riscv,cpu-intc";
  65                                 interrupt-controller;
  66                                 #interrupt-cells = <1>;
  67                         };
  68                 };
  69
  70                 cpu-map {
  71                         cluster0 {
  72                                 core0 {
  73                                         cpu = <&U74_0>;
  74                                 };
  75
  76                                 core1 {
  77                                         cpu = <&U74_1>;
  78                                 };
  79                         };
  80                 };
  81         };
  82
  83         osc_sys: osc_sys {
  84                 compatible = "fixed-clock";
  85                 #clock-cells = <0>;
  86                 /* This value must be overridden by the board */
  87                 clock-frequency = <0>;
  88         };
  89
  90         osc_aud: osc_aud {
  91                 compatible = "fixed-clock";
  92                 #clock-cells = <0>;
  93                 /* This value must be overridden by the board */
  94                 clock-frequency = <0>;
  95         };
  96
  97         gmac_rmii_ref: gmac_rmii_ref {
  98                 compatible = "fixed-clock";
  99                 #clock-cells = <0>;
 100                 /* Should be overridden by the board when needed */
 101                 clock-frequency = <0>;
 102         };
 103
 104         gmac_gr_mii_rxclk: gmac_gr_mii_rxclk {
 105                 compatible = "fixed-clock";
 106                 #clock-cells = <0>;
 107                 /* Should be overridden by the board when needed */
 108                 clock-frequency = <0>;
 109         };
 110
 111         soc {
 112                 compatible = "simple-bus";
 113                 interrupt-parent = <&plic>;
 114                 #address-cells = <2>;
 115                 #size-cells = <2>;
 116                 ranges;
 117
 118                 clint: clint@2000000 {
 119                         compatible = "starfive,jh7100-clint", "sifive,clint0";
 120                         reg = <0x0 0x2000000 0x0 0x10000>;
 121                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 122                                               <&cpu1_intc 3>, <&cpu1_intc 7>;
 123                 };
 124
 125                 plic: interrupt-controller@c000000 {
 126                         compatible = "starfive,jh7100-plic", "sifive,plic-1.0.0";
 127                         reg = <0x0 0xc000000 0x0 0x4000000>;
 128                         interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>,
 129                                               <&cpu1_intc 11>, <&cpu1_intc 9>;
 130                         interrupt-controller;
 131                         #address-cells = <0>;
 132                         #interrupt-cells = <1>;
 133                         riscv,ndev = <133>;
 134                 };
 135
 136                 audclk: clock-controller@10480000 {
 137                         compatible = "starfive,jh7100-audclk";
 138                         reg = <0x0 0x10480000 0x0 0x10000>;
 139                         clocks = <&clkgen JH7100_CLK_AUDIO_SRC>,
 140                                  <&clkgen JH7100_CLK_AUDIO_12288>,
 141                                  <&clkgen JH7100_CLK_DOM7AHB_BUS>;
 142                         clock-names = "audio_src", "audio_12288", "dom7ahb_bus";
 143                         #clock-cells = <1>;
 144                 };
 145
 146                 clkgen: clock-controller@11800000 {
 147                         compatible = "starfive,jh7100-clkgen";
 148                         reg = <0x0 0x11800000 0x0 0x10000>;
 149                         clocks = <&osc_sys>, <&osc_aud>, <&gmac_rmii_ref>, <&gmac_gr_mii_rxclk>;
 150                         clock-names = "osc_sys", "osc_aud", "gmac_rmii_ref", "gmac_gr_mii_rxclk";
 151                         #clock-cells = <1>;
 152                 };
 153
 154                 rstgen: reset-controller@11840000 {
 155                         compatible = "starfive,jh7100-reset";
 156                         reg = <0x0 0x11840000 0x0 0x10000>;
 157                         #reset-cells = <1>;
 158                 };
 159
 160                 i2c0: i2c@118b0000 {
 161                         compatible = "snps,designware-i2c";
 162                         reg = <0x0 0x118b0000 0x0 0x10000>;
 163                         clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
 164                                  <&clkgen JH7100_CLK_I2C0_APB>;
 165                         clock-names = "ref", "pclk";
 166                         resets = <&rstgen JH7100_RSTN_I2C0_APB>;
 167                         interrupts = <96>;
 168                         #address-cells = <1>;
 169                         #size-cells = <0>;
 170                         status = "disabled";
 171                 };
 172
 173                 i2c1: i2c@118c0000 {
 174                         compatible = "snps,designware-i2c";
 175                         reg = <0x0 0x118c0000 0x0 0x10000>;
 176                         clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
 177                                  <&clkgen JH7100_CLK_I2C1_APB>;
 178                         clock-names = "ref", "pclk";
 179                         resets = <&rstgen JH7100_RSTN_I2C1_APB>;
 180                         interrupts = <97>;
 181                         #address-cells = <1>;
 182                         #size-cells = <0>;
 183                         status = "disabled";
 184                 };
 185
 186                 gpio: pinctrl@11910000 {
 187                         compatible = "starfive,jh7100-pinctrl";
 188                         reg = <0x0 0x11910000 0x0 0x10000>,
 189                               <0x0 0x11858000 0x0 0x1000>;
 190                         reg-names = "gpio", "padctl";
 191                         clocks = <&clkgen JH7100_CLK_GPIO_APB>;
 192                         resets = <&rstgen JH7100_RSTN_GPIO_APB>;
 193                         interrupts = <32>;
 194                         gpio-controller;
 195                         #gpio-cells = <2>;
 196                         interrupt-controller;
 197                         #interrupt-cells = <2>;
 198                 };
 199
 200                 uart2: serial@12430000 {
 201                         compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
 202                         reg = <0x0 0x12430000 0x0 0x10000>;
 203                         clocks = <&clkgen JH7100_CLK_UART2_CORE>,
 204                                  <&clkgen JH7100_CLK_UART2_APB>;
 205                         clock-names = "baudclk", "apb_pclk";
 206                         resets = <&rstgen JH7100_RSTN_UART2_APB>;
 207                         interrupts = <72>;
 208                         reg-io-width = <4>;
 209                         reg-shift = <2>;
 210                         status = "disabled";
 211                 };
 212
 213                 uart3: serial@12440000 {
 214                         compatible = "starfive,jh7100-uart", "snps,dw-apb-uart";
 215                         reg = <0x0 0x12440000 0x0 0x10000>;
 216                         clocks = <&clkgen JH7100_CLK_UART3_CORE>,
 217                                  <&clkgen JH7100_CLK_UART3_APB>;
 218                         clock-names = "baudclk", "apb_pclk";
 219                         resets = <&rstgen JH7100_RSTN_UART3_APB>;
 220                         interrupts = <73>;
 221                         reg-io-width = <4>;
 222                         reg-shift = <2>;
 223                         status = "disabled";
 224                 };
 225
 226                 i2c2: i2c@12450000 {
 227                         compatible = "snps,designware-i2c";
 228                         reg = <0x0 0x12450000 0x0 0x10000>;
 229                         clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
 230                                  <&clkgen JH7100_CLK_I2C2_APB>;
 231                         clock-names = "ref", "pclk";
 232                         resets = <&rstgen JH7100_RSTN_I2C2_APB>;
 233                         interrupts = <74>;
 234                         #address-cells = <1>;
 235                         #size-cells = <0>;
 236                         status = "disabled";
 237                 };
 238
 239                 i2c3: i2c@12460000 {
 240                         compatible = "snps,designware-i2c";
 241                         reg = <0x0 0x12460000 0x0 0x10000>;
 242                         clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
 243                                  <&clkgen JH7100_CLK_I2C3_APB>;
 244                         clock-names = "ref", "pclk";
 245                         resets = <&rstgen JH7100_RSTN_I2C3_APB>;
 246                         interrupts = <75>;
 247                         #address-cells = <1>;
 248                         #size-cells = <0>;
 249                         status = "disabled";
 250                 };
 251         };
 252 };