1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020 SiFive, Inc */
6 #include <dt-bindings/clock/sifive-fu740-prci.h>
11 compatible = "sifive,fu740-c000", "sifive,fu740";
26 compatible = "sifive,bullet0", "riscv";
28 i-cache-block-size = <64>;
30 i-cache-size = <16384>;
31 next-level-cache = <&ccache>;
33 riscv,isa = "rv64imac";
35 cpu0_intc: interrupt-controller {
36 #interrupt-cells = <1>;
37 compatible = "riscv,cpu-intc";
42 compatible = "sifive,bullet0", "riscv";
43 d-cache-block-size = <64>;
45 d-cache-size = <32768>;
49 i-cache-block-size = <64>;
51 i-cache-size = <32768>;
54 mmu-type = "riscv,sv39";
55 next-level-cache = <&ccache>;
57 riscv,isa = "rv64imafdc";
59 cpu1_intc: interrupt-controller {
60 #interrupt-cells = <1>;
61 compatible = "riscv,cpu-intc";
66 compatible = "sifive,bullet0", "riscv";
67 d-cache-block-size = <64>;
69 d-cache-size = <32768>;
73 i-cache-block-size = <64>;
75 i-cache-size = <32768>;
78 mmu-type = "riscv,sv39";
79 next-level-cache = <&ccache>;
81 riscv,isa = "rv64imafdc";
83 cpu2_intc: interrupt-controller {
84 #interrupt-cells = <1>;
85 compatible = "riscv,cpu-intc";
90 compatible = "sifive,bullet0", "riscv";
91 d-cache-block-size = <64>;
93 d-cache-size = <32768>;
97 i-cache-block-size = <64>;
99 i-cache-size = <32768>;
102 mmu-type = "riscv,sv39";
103 next-level-cache = <&ccache>;
105 riscv,isa = "rv64imafdc";
107 cpu3_intc: interrupt-controller {
108 #interrupt-cells = <1>;
109 compatible = "riscv,cpu-intc";
110 interrupt-controller;
114 compatible = "sifive,bullet0", "riscv";
115 d-cache-block-size = <64>;
117 d-cache-size = <32768>;
121 i-cache-block-size = <64>;
122 i-cache-sets = <128>;
123 i-cache-size = <32768>;
126 mmu-type = "riscv,sv39";
127 next-level-cache = <&ccache>;
129 riscv,isa = "rv64imafdc";
131 cpu4_intc: interrupt-controller {
132 #interrupt-cells = <1>;
133 compatible = "riscv,cpu-intc";
134 interrupt-controller;
163 #address-cells = <2>;
165 compatible = "simple-bus";
167 plic0: interrupt-controller@c000000 {
168 #interrupt-cells = <1>;
169 #address-cells = <0>;
170 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171 reg = <0x0 0xc000000 0x0 0x4000000>;
173 interrupt-controller;
174 interrupts-extended = <
175 &cpu0_intc 0xffffffff
176 &cpu1_intc 0xffffffff &cpu1_intc 9
177 &cpu2_intc 0xffffffff &cpu2_intc 9
178 &cpu3_intc 0xffffffff &cpu3_intc 9
179 &cpu4_intc 0xffffffff &cpu4_intc 9>;
181 prci: clock-controller@10000000 {
182 compatible = "sifive,fu740-c000-prci";
183 reg = <0x0 0x10000000 0x0 0x1000>;
184 clocks = <&hfclk>, <&rtcclk>;
188 uart0: serial@10010000 {
189 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
190 reg = <0x0 0x10010000 0x0 0x1000>;
191 interrupt-parent = <&plic0>;
193 clocks = <&prci PRCI_CLK_PCLK>;
196 uart1: serial@10011000 {
197 compatible = "sifive,fu740-c000-uart", "sifive,uart0";
198 reg = <0x0 0x10011000 0x0 0x1000>;
199 interrupt-parent = <&plic0>;
201 clocks = <&prci PRCI_CLK_PCLK>;
205 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
206 reg = <0x0 0x10030000 0x0 0x1000>;
207 interrupt-parent = <&plic0>;
209 clocks = <&prci PRCI_CLK_PCLK>;
212 #address-cells = <1>;
217 compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
218 reg = <0x0 0x10031000 0x0 0x1000>;
219 interrupt-parent = <&plic0>;
221 clocks = <&prci PRCI_CLK_PCLK>;
224 #address-cells = <1>;
228 qspi0: spi@10040000 {
229 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
230 reg = <0x0 0x10040000 0x0 0x1000>,
231 <0x0 0x20000000 0x0 0x10000000>;
232 interrupt-parent = <&plic0>;
234 clocks = <&prci PRCI_CLK_PCLK>;
235 #address-cells = <1>;
239 qspi1: spi@10041000 {
240 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
241 reg = <0x0 0x10041000 0x0 0x1000>,
242 <0x0 0x30000000 0x0 0x10000000>;
243 interrupt-parent = <&plic0>;
245 clocks = <&prci PRCI_CLK_PCLK>;
246 #address-cells = <1>;
251 compatible = "sifive,fu740-c000-spi", "sifive,spi0";
252 reg = <0x0 0x10050000 0x0 0x1000>;
253 interrupt-parent = <&plic0>;
255 clocks = <&prci PRCI_CLK_PCLK>;
256 #address-cells = <1>;
260 eth0: ethernet@10090000 {
261 compatible = "sifive,fu540-c000-gem";
262 interrupt-parent = <&plic0>;
264 reg = <0x0 0x10090000 0x0 0x2000>,
265 <0x0 0x100a0000 0x0 0x1000>;
266 local-mac-address = [00 00 00 00 00 00];
267 clock-names = "pclk", "hclk";
268 clocks = <&prci PRCI_CLK_GEMGXLPLL>,
269 <&prci PRCI_CLK_GEMGXLPLL>;
270 #address-cells = <1>;
275 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
276 reg = <0x0 0x10020000 0x0 0x1000>;
277 interrupt-parent = <&plic0>;
278 interrupts = <44>, <45>, <46>, <47>;
279 clocks = <&prci PRCI_CLK_PCLK>;
284 compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
285 reg = <0x0 0x10021000 0x0 0x1000>;
286 interrupt-parent = <&plic0>;
287 interrupts = <48>, <49>, <50>, <51>;
288 clocks = <&prci PRCI_CLK_PCLK>;
292 ccache: cache-controller@2010000 {
293 compatible = "sifive,fu740-c000-ccache", "cache";
294 cache-block-size = <64>;
297 cache-size = <2097152>;
299 interrupt-parent = <&plic0>;
300 interrupts = <19 21 22 20>;
301 reg = <0x0 0x2010000 0x0 0x1000>;
303 gpio: gpio@10060000 {
304 compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
305 interrupt-parent = <&plic0>;
306 interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
307 <30>, <31>, <32>, <33>, <34>, <35>, <36>,
309 reg = <0x0 0x10060000 0x0 0x1000>;
312 interrupt-controller;
313 #interrupt-cells = <2>;
314 clocks = <&prci PRCI_CLK_PCLK>;
318 compatible = "sifive,fu740-pcie";
319 #address-cells = <3>;
321 #interrupt-cells = <1>;
322 reg = <0xe 0x00000000 0x0 0x80000000>,
323 <0xd 0xf0000000 0x0 0x10000000>,
324 <0x0 0x100d0000 0x0 0x1000>;
325 reg-names = "dbi", "config", "mgmt";
328 bus-range = <0x0 0xff>;
329 ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */
330 <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */
331 <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x10000000>, /* mem */
332 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */
334 interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
335 interrupt-names = "msi", "inta", "intb", "intc", "intd";
336 interrupt-parent = <&plic0>;
337 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
338 interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
339 <0x0 0x0 0x0 0x2 &plic0 58>,
340 <0x0 0x0 0x0 0x3 &plic0 59>,
341 <0x0 0x0 0x0 0x4 &plic0 60>;
342 clock-names = "pcie_aux";
343 clocks = <&prci PRCI_CLK_PCIE_AUX>;
344 pwren-gpios = <&gpio 5 0>;
345 reset-gpios = <&gpio 8 0>;