arch/riscv/boot/dts/sifive/fu540-c000.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2018-2019 SiFive, Inc */
   3
   4 /dts-v1/;
   5
   6 #include <dt-bindings/clock/sifive-fu540-prci.h>
   7
   8 / {
   9         #address-cells = <2>;
  10         #size-cells = <2>;
  11         compatible = "sifive,fu540-c000", "sifive,fu540";
  12
  13         aliases {
  14                 serial0 = &uart0;
  15                 serial1 = &uart1;
  16                 ethernet0 = &eth0;
  17         };
  18
  19         chosen {
  20         };
  21
  22         cpus {
  23                 #address-cells = <1>;
  24                 #size-cells = <0>;
  25                 cpu0: cpu@0 {
  26                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
  27                         device_type = "cpu";
  28                         i-cache-block-size = <64>;
  29                         i-cache-sets = <128>;
  30                         i-cache-size = <16384>;
  31                         reg = <0>;
  32                         riscv,isa = "rv64imac";
  33                         status = "disabled";
  34                         cpu0_intc: interrupt-controller {
  35                                 #interrupt-cells = <1>;
  36                                 compatible = "riscv,cpu-intc";
  37                                 interrupt-controller;
  38                         };
  39                 };
  40                 cpu1: cpu@1 {
  41                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  42                         d-cache-block-size = <64>;
  43                         d-cache-sets = <64>;
  44                         d-cache-size = <32768>;
  45                         d-tlb-sets = <1>;
  46                         d-tlb-size = <32>;
  47                         device_type = "cpu";
  48                         i-cache-block-size = <64>;
  49                         i-cache-sets = <64>;
  50                         i-cache-size = <32768>;
  51                         i-tlb-sets = <1>;
  52                         i-tlb-size = <32>;
  53                         mmu-type = "riscv,sv39";
  54                         reg = <1>;
  55                         riscv,isa = "rv64imafdc";
  56                         tlb-split;
  57                         next-level-cache = <&l2cache>;
  58                         cpu1_intc: interrupt-controller {
  59                                 #interrupt-cells = <1>;
  60                                 compatible = "riscv,cpu-intc";
  61                                 interrupt-controller;
  62                         };
  63                 };
  64                 cpu2: cpu@2 {
  65                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  66                         d-cache-block-size = <64>;
  67                         d-cache-sets = <64>;
  68                         d-cache-size = <32768>;
  69                         d-tlb-sets = <1>;
  70                         d-tlb-size = <32>;
  71                         device_type = "cpu";
  72                         i-cache-block-size = <64>;
  73                         i-cache-sets = <64>;
  74                         i-cache-size = <32768>;
  75                         i-tlb-sets = <1>;
  76                         i-tlb-size = <32>;
  77                         mmu-type = "riscv,sv39";
  78                         reg = <2>;
  79                         riscv,isa = "rv64imafdc";
  80                         tlb-split;
  81                         next-level-cache = <&l2cache>;
  82                         cpu2_intc: interrupt-controller {
  83                                 #interrupt-cells = <1>;
  84                                 compatible = "riscv,cpu-intc";
  85                                 interrupt-controller;
  86                         };
  87                 };
  88                 cpu3: cpu@3 {
  89                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  90                         d-cache-block-size = <64>;
  91                         d-cache-sets = <64>;
  92                         d-cache-size = <32768>;
  93                         d-tlb-sets = <1>;
  94                         d-tlb-size = <32>;
  95                         device_type = "cpu";
  96                         i-cache-block-size = <64>;
  97                         i-cache-sets = <64>;
  98                         i-cache-size = <32768>;
  99                         i-tlb-sets = <1>;
 100                         i-tlb-size = <32>;
 101                         mmu-type = "riscv,sv39";
 102                         reg = <3>;
 103                         riscv,isa = "rv64imafdc";
 104                         tlb-split;
 105                         next-level-cache = <&l2cache>;
 106                         cpu3_intc: interrupt-controller {
 107                                 #interrupt-cells = <1>;
 108                                 compatible = "riscv,cpu-intc";
 109                                 interrupt-controller;
 110                         };
 111                 };
 112                 cpu4: cpu@4 {
 113                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 114                         d-cache-block-size = <64>;
 115                         d-cache-sets = <64>;
 116                         d-cache-size = <32768>;
 117                         d-tlb-sets = <1>;
 118                         d-tlb-size = <32>;
 119                         device_type = "cpu";
 120                         i-cache-block-size = <64>;
 121                         i-cache-sets = <64>;
 122                         i-cache-size = <32768>;
 123                         i-tlb-sets = <1>;
 124                         i-tlb-size = <32>;
 125                         mmu-type = "riscv,sv39";
 126                         reg = <4>;
 127                         riscv,isa = "rv64imafdc";
 128                         tlb-split;
 129                         next-level-cache = <&l2cache>;
 130                         cpu4_intc: interrupt-controller {
 131                                 #interrupt-cells = <1>;
 132                                 compatible = "riscv,cpu-intc";
 133                                 interrupt-controller;
 134                         };
 135                 };
 136         };
 137         soc {
 138                 #address-cells = <2>;
 139                 #size-cells = <2>;
 140                 compatible = "simple-bus";
 141                 ranges;
 142                 plic0: interrupt-controller@c000000 {
 143                         compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 144                         reg = <0x0 0xc000000 0x0 0x4000000>;
 145                         #address-cells = <0>;
 146                         #interrupt-cells = <1>;
 147                         interrupt-controller;
 148                         interrupts-extended =
 149                                 <&cpu0_intc 0xffffffff>,
 150                                 <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
 151                                 <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
 152                                 <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
 153                                 <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
 154                         riscv,ndev = <53>;
 155                 };
 156                 prci: clock-controller@10000000 {
 157                         compatible = "sifive,fu540-c000-prci";
 158                         reg = <0x0 0x10000000 0x0 0x1000>;
 159                         clocks = <&hfclk>, <&rtcclk>;
 160                         #clock-cells = <1>;
 161                 };
 162                 uart0: serial@10010000 {
 163                         compatible = "sifive,fu540-c000-uart", "sifive,uart0";
 164                         reg = <0x0 0x10010000 0x0 0x1000>;
 165                         interrupt-parent = <&plic0>;
 166                         interrupts = <4>;
 167                         clocks = <&prci PRCI_CLK_TLCLK>;
 168                         status = "disabled";
 169                 };
 170                 dma: dma@3000000 {
 171                         compatible = "sifive,fu540-c000-pdma";
 172                         reg = <0x0 0x3000000 0x0 0x8000>;
 173                         interrupt-parent = <&plic0>;
 174                         interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
 175                                      <30>;
 176                         #dma-cells = <1>;
 177                 };
 178                 uart1: serial@10011000 {
 179                         compatible = "sifive,fu540-c000-uart", "sifive,uart0";
 180                         reg = <0x0 0x10011000 0x0 0x1000>;
 181                         interrupt-parent = <&plic0>;
 182                         interrupts = <5>;
 183                         clocks = <&prci PRCI_CLK_TLCLK>;
 184                         status = "disabled";
 185                 };
 186                 i2c0: i2c@10030000 {
 187                         compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
 188                         reg = <0x0 0x10030000 0x0 0x1000>;
 189                         interrupt-parent = <&plic0>;
 190                         interrupts = <50>;
 191                         clocks = <&prci PRCI_CLK_TLCLK>;
 192                         reg-shift = <2>;
 193                         reg-io-width = <1>;
 194                         #address-cells = <1>;
 195                         #size-cells = <0>;
 196                         status = "disabled";
 197                 };
 198                 qspi0: spi@10040000 {
 199                         compatible = "sifive,fu540-c000-spi", "sifive,spi0";
 200                         reg = <0x0 0x10040000 0x0 0x1000>,
 201                               <0x0 0x20000000 0x0 0x10000000>;
 202                         interrupt-parent = <&plic0>;
 203                         interrupts = <51>;
 204                         clocks = <&prci PRCI_CLK_TLCLK>;
 205                         #address-cells = <1>;
 206                         #size-cells = <0>;
 207                         status = "disabled";
 208                 };
 209                 qspi1: spi@10041000 {
 210                         compatible = "sifive,fu540-c000-spi", "sifive,spi0";
 211                         reg = <0x0 0x10041000 0x0 0x1000>,
 212                               <0x0 0x30000000 0x0 0x10000000>;
 213                         interrupt-parent = <&plic0>;
 214                         interrupts = <52>;
 215                         clocks = <&prci PRCI_CLK_TLCLK>;
 216                         #address-cells = <1>;
 217                         #size-cells = <0>;
 218                         status = "disabled";
 219                 };
 220                 qspi2: spi@10050000 {
 221                         compatible = "sifive,fu540-c000-spi", "sifive,spi0";
 222                         reg = <0x0 0x10050000 0x0 0x1000>;
 223                         interrupt-parent = <&plic0>;
 224                         interrupts = <6>;
 225                         clocks = <&prci PRCI_CLK_TLCLK>;
 226                         #address-cells = <1>;
 227                         #size-cells = <0>;
 228                         status = "disabled";
 229                 };
 230                 eth0: ethernet@10090000 {
 231                         compatible = "sifive,fu540-c000-gem";
 232                         interrupt-parent = <&plic0>;
 233                         interrupts = <53>;
 234                         reg = <0x0 0x10090000 0x0 0x2000>,
 235                               <0x0 0x100a0000 0x0 0x1000>;
 236                         local-mac-address = [00 00 00 00 00 00];
 237                         clock-names = "pclk", "hclk";
 238                         clocks = <&prci PRCI_CLK_GEMGXLPLL>,
 239                                  <&prci PRCI_CLK_GEMGXLPLL>;
 240                         #address-cells = <1>;
 241                         #size-cells = <0>;
 242                         status = "disabled";
 243                 };
 244                 pwm0: pwm@10020000 {
 245                         compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
 246                         reg = <0x0 0x10020000 0x0 0x1000>;
 247                         interrupt-parent = <&plic0>;
 248                         interrupts = <42>, <43>, <44>, <45>;
 249                         clocks = <&prci PRCI_CLK_TLCLK>;
 250                         #pwm-cells = <3>;
 251                         status = "disabled";
 252                 };
 253                 pwm1: pwm@10021000 {
 254                         compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
 255                         reg = <0x0 0x10021000 0x0 0x1000>;
 256                         interrupt-parent = <&plic0>;
 257                         interrupts = <46>, <47>, <48>, <49>;
 258                         clocks = <&prci PRCI_CLK_TLCLK>;
 259                         #pwm-cells = <3>;
 260                         status = "disabled";
 261                 };
 262                 l2cache: cache-controller@2010000 {
 263                         compatible = "sifive,fu540-c000-ccache", "cache";
 264                         cache-block-size = <64>;
 265                         cache-level = <2>;
 266                         cache-sets = <1024>;
 267                         cache-size = <2097152>;
 268                         cache-unified;
 269                         interrupt-parent = <&plic0>;
 270                         interrupts = <1>, <2>, <3>;
 271                         reg = <0x0 0x2010000 0x0 0x1000>;
 272                 };
 273                 gpio: gpio@10060000 {
 274                         compatible = "sifive,fu540-c000-gpio", "sifive,gpio0";
 275                         interrupt-parent = <&plic0>;
 276                         interrupts = <7>, <8>, <9>, <10>, <11>, <12>, <13>,
 277                                      <14>, <15>, <16>, <17>, <18>, <19>, <20>,
 278                                      <21>, <22>;
 279                         reg = <0x0 0x10060000 0x0 0x1000>;
 280                         gpio-controller;
 281                         #gpio-cells = <2>;
 282                         interrupt-controller;
 283                         #interrupt-cells = <2>;
 284                         clocks = <&prci PRCI_CLK_TLCLK>;
 285                         status = "disabled";
 286                 };
 287         };
 288 };