1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
10 model = "Microchip PolarFire SoC";
11 compatible = "microchip,mpfs";
18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
20 i-cache-block-size = <64>;
22 i-cache-size = <16384>;
24 riscv,isa = "rv64imac";
25 clocks = <&clkcfg CLK_CPU>;
28 cpu0_intc: interrupt-controller {
29 #interrupt-cells = <1>;
30 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
37 d-cache-block-size = <64>;
39 d-cache-size = <32768>;
43 i-cache-block-size = <64>;
45 i-cache-size = <32768>;
48 mmu-type = "riscv,sv39";
50 riscv,isa = "rv64imafdc";
51 clocks = <&clkcfg CLK_CPU>;
55 cpu1_intc: interrupt-controller {
56 #interrupt-cells = <1>;
57 compatible = "riscv,cpu-intc";
63 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
64 d-cache-block-size = <64>;
66 d-cache-size = <32768>;
70 i-cache-block-size = <64>;
72 i-cache-size = <32768>;
75 mmu-type = "riscv,sv39";
77 riscv,isa = "rv64imafdc";
78 clocks = <&clkcfg CLK_CPU>;
82 cpu2_intc: interrupt-controller {
83 #interrupt-cells = <1>;
84 compatible = "riscv,cpu-intc";
90 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
91 d-cache-block-size = <64>;
93 d-cache-size = <32768>;
97 i-cache-block-size = <64>;
99 i-cache-size = <32768>;
102 mmu-type = "riscv,sv39";
104 riscv,isa = "rv64imafdc";
105 clocks = <&clkcfg CLK_CPU>;
109 cpu3_intc: interrupt-controller {
110 #interrupt-cells = <1>;
111 compatible = "riscv,cpu-intc";
112 interrupt-controller;
117 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
118 d-cache-block-size = <64>;
120 d-cache-size = <32768>;
124 i-cache-block-size = <64>;
126 i-cache-size = <32768>;
129 mmu-type = "riscv,sv39";
131 riscv,isa = "rv64imafdc";
132 clocks = <&clkcfg CLK_CPU>;
135 cpu4_intc: interrupt-controller {
136 #interrupt-cells = <1>;
137 compatible = "riscv,cpu-intc";
138 interrupt-controller;
144 compatible = "fixed-clock";
148 syscontroller: syscontroller {
149 compatible = "microchip,mpfs-sys-controller";
154 #address-cells = <2>;
156 compatible = "simple-bus";
159 cctrllr: cache-controller@2010000 {
160 compatible = "sifive,fu540-c000-ccache", "cache";
161 reg = <0x0 0x2010000 0x0 0x1000>;
162 cache-block-size = <64>;
165 cache-size = <2097152>;
167 interrupt-parent = <&plic>;
168 interrupts = <1>, <2>, <3>;
171 clint: clint@2000000 {
172 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
173 reg = <0x0 0x2000000 0x0 0xC000>;
174 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
175 <&cpu1_intc 3>, <&cpu1_intc 7>,
176 <&cpu2_intc 3>, <&cpu2_intc 7>,
177 <&cpu3_intc 3>, <&cpu3_intc 7>,
178 <&cpu4_intc 3>, <&cpu4_intc 7>;
181 plic: interrupt-controller@c000000 {
182 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
183 reg = <0x0 0xc000000 0x0 0x4000000>;
184 #address-cells = <0>;
185 #interrupt-cells = <1>;
186 interrupt-controller;
187 interrupts-extended = <&cpu0_intc 11>,
188 <&cpu1_intc 11>, <&cpu1_intc 9>,
189 <&cpu2_intc 11>, <&cpu2_intc 9>,
190 <&cpu3_intc 11>, <&cpu3_intc 9>,
191 <&cpu4_intc 11>, <&cpu4_intc 9>;
195 clkcfg: clkcfg@20002000 {
196 compatible = "microchip,mpfs-clkcfg";
197 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
202 mmuart0: serial@20000000 {
203 compatible = "ns16550a";
204 reg = <0x0 0x20000000 0x0 0x400>;
207 interrupt-parent = <&plic>;
209 current-speed = <115200>;
210 clocks = <&clkcfg CLK_MMUART0>;
211 status = "disabled"; /* Reserved for the HSS */
214 mmuart1: serial@20100000 {
215 compatible = "ns16550a";
216 reg = <0x0 0x20100000 0x0 0x400>;
219 interrupt-parent = <&plic>;
221 current-speed = <115200>;
222 clocks = <&clkcfg CLK_MMUART1>;
226 mmuart2: serial@20102000 {
227 compatible = "ns16550a";
228 reg = <0x0 0x20102000 0x0 0x400>;
231 interrupt-parent = <&plic>;
233 current-speed = <115200>;
234 clocks = <&clkcfg CLK_MMUART2>;
238 mmuart3: serial@20104000 {
239 compatible = "ns16550a";
240 reg = <0x0 0x20104000 0x0 0x400>;
243 interrupt-parent = <&plic>;
245 current-speed = <115200>;
246 clocks = <&clkcfg CLK_MMUART3>;
250 mmuart4: serial@20106000 {
251 compatible = "ns16550a";
252 reg = <0x0 0x20106000 0x0 0x400>;
255 interrupt-parent = <&plic>;
257 clocks = <&clkcfg CLK_MMUART4>;
258 current-speed = <115200>;
262 /* Common node entry for emmc/sd */
264 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
265 reg = <0x0 0x20008000 0x0 0x1000>;
266 interrupt-parent = <&plic>;
268 clocks = <&clkcfg CLK_MMC>;
269 max-frequency = <200000000>;
274 compatible = "microchip,mpfs-spi";
275 #address-cells = <1>;
277 reg = <0x0 0x20108000 0x0 0x1000>;
278 interrupt-parent = <&plic>;
280 clocks = <&clkcfg CLK_SPI0>;
281 spi-max-frequency = <25000000>;
286 compatible = "microchip,mpfs-spi";
287 #address-cells = <1>;
289 reg = <0x0 0x20109000 0x0 0x1000>;
290 interrupt-parent = <&plic>;
292 clocks = <&clkcfg CLK_SPI1>;
293 spi-max-frequency = <25000000>;
298 compatible = "microchip,mpfs-qspi";
299 #address-cells = <1>;
301 reg = <0x0 0x21000000 0x0 0x1000>;
302 interrupt-parent = <&plic>;
304 clocks = <&clkcfg CLK_QSPI>;
305 spi-max-frequency = <25000000>;
310 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
311 reg = <0x0 0x2010a000 0x0 0x1000>;
312 #address-cells = <1>;
314 interrupt-parent = <&plic>;
316 clocks = <&clkcfg CLK_I2C0>;
317 clock-frequency = <100000>;
322 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
323 reg = <0x0 0x2010b000 0x0 0x1000>;
324 #address-cells = <1>;
326 interrupt-parent = <&plic>;
328 clocks = <&clkcfg CLK_I2C1>;
329 clock-frequency = <100000>;
333 mac0: ethernet@20110000 {
334 compatible = "cdns,macb";
335 reg = <0x0 0x20110000 0x0 0x2000>;
336 #address-cells = <1>;
338 interrupt-parent = <&plic>;
339 interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
340 local-mac-address = [00 00 00 00 00 00];
341 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
342 clock-names = "pclk", "hclk";
346 mac1: ethernet@20112000 {
347 compatible = "cdns,macb";
348 reg = <0x0 0x20112000 0x0 0x2000>;
349 #address-cells = <1>;
351 interrupt-parent = <&plic>;
352 interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
353 local-mac-address = [00 00 00 00 00 00];
354 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
355 clock-names = "pclk", "hclk";
359 gpio0: gpio@20120000 {
360 compatible = "microchip,mpfs-gpio";
361 reg = <0x0 0x20120000 0x0 0x1000>;
362 interrupt-parent = <&plic>;
363 interrupt-controller;
364 #interrupt-cells = <1>;
365 clocks = <&clkcfg CLK_GPIO0>;
371 gpio1: gpio@20121000 {
372 compatible = "microchip,mpfs-gpio";
373 reg = <0x0 0x20121000 0x0 0x1000>;
374 interrupt-parent = <&plic>;
375 interrupt-controller;
376 #interrupt-cells = <1>;
377 clocks = <&clkcfg CLK_GPIO1>;
383 gpio2: gpio@20122000 {
384 compatible = "microchip,mpfs-gpio";
385 reg = <0x0 0x20122000 0x0 0x1000>;
386 interrupt-parent = <&plic>;
387 interrupt-controller;
388 #interrupt-cells = <1>;
389 clocks = <&clkcfg CLK_GPIO2>;
396 compatible = "microchip,mpfs-rtc";
397 reg = <0x0 0x20124000 0x0 0x1000>;
398 interrupt-parent = <&plic>;
399 interrupts = <80>, <81>;
400 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
401 clock-names = "rtc", "rtcref";
406 compatible = "microchip,mpfs-musb";
407 reg = <0x0 0x20201000 0x0 0x1000>;
408 interrupt-parent = <&plic>;
409 interrupts = <86>, <87>;
410 clocks = <&clkcfg CLK_USB>;
411 interrupt-names = "dma","mc";
415 pcie: pcie@2000000000 {
416 compatible = "microchip,pcie-host-1.0";
417 #address-cells = <0x3>;
418 #interrupt-cells = <0x1>;
421 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
422 reg-names = "cfg", "apb";
423 bus-range = <0x0 0x7f>;
424 interrupt-parent = <&plic>;
426 interrupt-map = <0 0 0 1 &pcie_intc 0>,
427 <0 0 0 2 &pcie_intc 1>,
428 <0 0 0 3 &pcie_intc 2>,
429 <0 0 0 4 &pcie_intc 3>;
430 interrupt-map-mask = <0 0 0 7>;
431 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
432 clock-names = "fic0", "fic1", "fic3";
433 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
434 msi-parent = <&pcie>;
436 microchip,axi-m-atr0 = <0x10 0x0>;
438 pcie_intc: legacy-interrupt-controller {
439 #address-cells = <0>;
440 #interrupt-cells = <1>;
441 interrupt-controller;
445 mbox: mailbox@37020000 {
446 compatible = "microchip,mpfs-mailbox";
447 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
448 interrupt-parent = <&plic>;