arch/riscv/boot/dts/microchip/mpfs.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
   3
   4 /dts-v1/;
   5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
   6
   7 / {
   8         #address-cells = <2>;
   9         #size-cells = <2>;
  10         model = "Microchip PolarFire SoC";
  11         compatible = "microchip,mpfs";
  12
  13         cpus {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 cpu0: cpu@0 {
  18                         compatible = "sifive,e51", "sifive,rocket0", "riscv";
  19                         device_type = "cpu";
  20                         i-cache-block-size = <64>;
  21                         i-cache-sets = <128>;
  22                         i-cache-size = <16384>;
  23                         reg = <0>;
  24                         riscv,isa = "rv64imac";
  25                         clocks = <&clkcfg CLK_CPU>;
  26                         status = "disabled";
  27
  28                         cpu0_intc: interrupt-controller {
  29                                 #interrupt-cells = <1>;
  30                                 compatible = "riscv,cpu-intc";
  31                                 interrupt-controller;
  32                         };
  33                 };
  34
  35                 cpu1: cpu@1 {
  36                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  37                         d-cache-block-size = <64>;
  38                         d-cache-sets = <64>;
  39                         d-cache-size = <32768>;
  40                         d-tlb-sets = <1>;
  41                         d-tlb-size = <32>;
  42                         device_type = "cpu";
  43                         i-cache-block-size = <64>;
  44                         i-cache-sets = <64>;
  45                         i-cache-size = <32768>;
  46                         i-tlb-sets = <1>;
  47                         i-tlb-size = <32>;
  48                         mmu-type = "riscv,sv39";
  49                         reg = <1>;
  50                         riscv,isa = "rv64imafdc";
  51                         clocks = <&clkcfg CLK_CPU>;
  52                         tlb-split;
  53                         status = "okay";
  54
  55                         cpu1_intc: interrupt-controller {
  56                                 #interrupt-cells = <1>;
  57                                 compatible = "riscv,cpu-intc";
  58                                 interrupt-controller;
  59                         };
  60                 };
  61
  62                 cpu2: cpu@2 {
  63                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  64                         d-cache-block-size = <64>;
  65                         d-cache-sets = <64>;
  66                         d-cache-size = <32768>;
  67                         d-tlb-sets = <1>;
  68                         d-tlb-size = <32>;
  69                         device_type = "cpu";
  70                         i-cache-block-size = <64>;
  71                         i-cache-sets = <64>;
  72                         i-cache-size = <32768>;
  73                         i-tlb-sets = <1>;
  74                         i-tlb-size = <32>;
  75                         mmu-type = "riscv,sv39";
  76                         reg = <2>;
  77                         riscv,isa = "rv64imafdc";
  78                         clocks = <&clkcfg CLK_CPU>;
  79                         tlb-split;
  80                         status = "okay";
  81
  82                         cpu2_intc: interrupt-controller {
  83                                 #interrupt-cells = <1>;
  84                                 compatible = "riscv,cpu-intc";
  85                                 interrupt-controller;
  86                         };
  87                 };
  88
  89                 cpu3: cpu@3 {
  90                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
  91                         d-cache-block-size = <64>;
  92                         d-cache-sets = <64>;
  93                         d-cache-size = <32768>;
  94                         d-tlb-sets = <1>;
  95                         d-tlb-size = <32>;
  96                         device_type = "cpu";
  97                         i-cache-block-size = <64>;
  98                         i-cache-sets = <64>;
  99                         i-cache-size = <32768>;
 100                         i-tlb-sets = <1>;
 101                         i-tlb-size = <32>;
 102                         mmu-type = "riscv,sv39";
 103                         reg = <3>;
 104                         riscv,isa = "rv64imafdc";
 105                         clocks = <&clkcfg CLK_CPU>;
 106                         tlb-split;
 107                         status = "okay";
 108
 109                         cpu3_intc: interrupt-controller {
 110                                 #interrupt-cells = <1>;
 111                                 compatible = "riscv,cpu-intc";
 112                                 interrupt-controller;
 113                         };
 114                 };
 115
 116                 cpu4: cpu@4 {
 117                         compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
 118                         d-cache-block-size = <64>;
 119                         d-cache-sets = <64>;
 120                         d-cache-size = <32768>;
 121                         d-tlb-sets = <1>;
 122                         d-tlb-size = <32>;
 123                         device_type = "cpu";
 124                         i-cache-block-size = <64>;
 125                         i-cache-sets = <64>;
 126                         i-cache-size = <32768>;
 127                         i-tlb-sets = <1>;
 128                         i-tlb-size = <32>;
 129                         mmu-type = "riscv,sv39";
 130                         reg = <4>;
 131                         riscv,isa = "rv64imafdc";
 132                         clocks = <&clkcfg CLK_CPU>;
 133                         tlb-split;
 134                         status = "okay";
 135                         cpu4_intc: interrupt-controller {
 136                                 #interrupt-cells = <1>;
 137                                 compatible = "riscv,cpu-intc";
 138                                 interrupt-controller;
 139                         };
 140                 };
 141
 142                 cpu-map {
 143                         cluster0 {
 144                                 core0 {
 145                                         cpu = <&cpu0>;
 146                                 };
 147
 148                                 core1 {
 149                                         cpu = <&cpu1>;
 150                                 };
 151
 152                                 core2 {
 153                                         cpu = <&cpu2>;
 154                                 };
 155
 156                                 core3 {
 157                                         cpu = <&cpu3>;
 158                                 };
 159
 160                                 core4 {
 161                                         cpu = <&cpu4>;
 162                                 };
 163                         };
 164                 };
 165         };
 166
 167         refclk: mssrefclk {
 168                 compatible = "fixed-clock";
 169                 #clock-cells = <0>;
 170         };
 171
 172         syscontroller: syscontroller {
 173                 compatible = "microchip,mpfs-sys-controller";
 174                 mboxes = <&mbox 0>;
 175         };
 176
 177         soc {
 178                 #address-cells = <2>;
 179                 #size-cells = <2>;
 180                 compatible = "simple-bus";
 181                 ranges;
 182
 183                 cctrllr: cache-controller@2010000 {
 184                         compatible = "sifive,fu540-c000-ccache", "cache";
 185                         reg = <0x0 0x2010000 0x0 0x1000>;
 186                         cache-block-size = <64>;
 187                         cache-level = <2>;
 188                         cache-sets = <1024>;
 189                         cache-size = <2097152>;
 190                         cache-unified;
 191                         interrupt-parent = <&plic>;
 192                         interrupts = <1>, <2>, <3>;
 193                 };
 194
 195                 clint: clint@2000000 {
 196                         compatible = "sifive,fu540-c000-clint", "sifive,clint0";
 197                         reg = <0x0 0x2000000 0x0 0xC000>;
 198                         interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
 199                                               <&cpu1_intc 3>, <&cpu1_intc 7>,
 200                                               <&cpu2_intc 3>, <&cpu2_intc 7>,
 201                                               <&cpu3_intc 3>, <&cpu3_intc 7>,
 202                                               <&cpu4_intc 3>, <&cpu4_intc 7>;
 203                 };
 204
 205                 plic: interrupt-controller@c000000 {
 206                         compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
 207                         reg = <0x0 0xc000000 0x0 0x4000000>;
 208                         #address-cells = <0>;
 209                         #interrupt-cells = <1>;
 210                         interrupt-controller;
 211                         interrupts-extended = <&cpu0_intc 11>,
 212                                               <&cpu1_intc 11>, <&cpu1_intc 9>,
 213                                               <&cpu2_intc 11>, <&cpu2_intc 9>,
 214                                               <&cpu3_intc 11>, <&cpu3_intc 9>,
 215                                               <&cpu4_intc 11>, <&cpu4_intc 9>;
 216                         riscv,ndev = <186>;
 217                 };
 218
 219                 clkcfg: clkcfg@20002000 {
 220                         compatible = "microchip,mpfs-clkcfg";
 221                         reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
 222                         clocks = <&refclk>;
 223                         #clock-cells = <1>;
 224                 };
 225
 226                 mmuart0: serial@20000000 {
 227                         compatible = "ns16550a";
 228                         reg = <0x0 0x20000000 0x0 0x400>;
 229                         reg-io-width = <4>;
 230                         reg-shift = <2>;
 231                         interrupt-parent = <&plic>;
 232                         interrupts = <90>;
 233                         current-speed = <115200>;
 234                         clocks = <&clkcfg CLK_MMUART0>;
 235                         status = "disabled"; /* Reserved for the HSS */
 236                 };
 237
 238                 mmuart1: serial@20100000 {
 239                         compatible = "ns16550a";
 240                         reg = <0x0 0x20100000 0x0 0x400>;
 241                         reg-io-width = <4>;
 242                         reg-shift = <2>;
 243                         interrupt-parent = <&plic>;
 244                         interrupts = <91>;
 245                         current-speed = <115200>;
 246                         clocks = <&clkcfg CLK_MMUART1>;
 247                         status = "disabled";
 248                 };
 249
 250                 mmuart2: serial@20102000 {
 251                         compatible = "ns16550a";
 252                         reg = <0x0 0x20102000 0x0 0x400>;
 253                         reg-io-width = <4>;
 254                         reg-shift = <2>;
 255                         interrupt-parent = <&plic>;
 256                         interrupts = <92>;
 257                         current-speed = <115200>;
 258                         clocks = <&clkcfg CLK_MMUART2>;
 259                         status = "disabled";
 260                 };
 261
 262                 mmuart3: serial@20104000 {
 263                         compatible = "ns16550a";
 264                         reg = <0x0 0x20104000 0x0 0x400>;
 265                         reg-io-width = <4>;
 266                         reg-shift = <2>;
 267                         interrupt-parent = <&plic>;
 268                         interrupts = <93>;
 269                         current-speed = <115200>;
 270                         clocks = <&clkcfg CLK_MMUART3>;
 271                         status = "disabled";
 272                 };
 273
 274                 mmuart4: serial@20106000 {
 275                         compatible = "ns16550a";
 276                         reg = <0x0 0x20106000 0x0 0x400>;
 277                         reg-io-width = <4>;
 278                         reg-shift = <2>;
 279                         interrupt-parent = <&plic>;
 280                         interrupts = <94>;
 281                         clocks = <&clkcfg CLK_MMUART4>;
 282                         current-speed = <115200>;
 283                         status = "disabled";
 284                 };
 285
 286                 /* Common node entry for emmc/sd */
 287                 mmc: mmc@20008000 {
 288                         compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
 289                         reg = <0x0 0x20008000 0x0 0x1000>;
 290                         interrupt-parent = <&plic>;
 291                         interrupts = <88>;
 292                         clocks = <&clkcfg CLK_MMC>;
 293                         max-frequency = <200000000>;
 294                         status = "disabled";
 295                 };
 296
 297                 spi0: spi@20108000 {
 298                         compatible = "microchip,mpfs-spi";
 299                         #address-cells = <1>;
 300                         #size-cells = <0>;
 301                         reg = <0x0 0x20108000 0x0 0x1000>;
 302                         interrupt-parent = <&plic>;
 303                         interrupts = <54>;
 304                         clocks = <&clkcfg CLK_SPI0>;
 305                         status = "disabled";
 306                 };
 307
 308                 spi1: spi@20109000 {
 309                         compatible = "microchip,mpfs-spi";
 310                         #address-cells = <1>;
 311                         #size-cells = <0>;
 312                         reg = <0x0 0x20109000 0x0 0x1000>;
 313                         interrupt-parent = <&plic>;
 314                         interrupts = <55>;
 315                         clocks = <&clkcfg CLK_SPI1>;
 316                         status = "disabled";
 317                 };
 318
 319                 qspi: spi@21000000 {
 320                         compatible = "microchip,mpfs-qspi";
 321                         #address-cells = <1>;
 322                         #size-cells = <0>;
 323                         reg = <0x0 0x21000000 0x0 0x1000>;
 324                         interrupt-parent = <&plic>;
 325                         interrupts = <85>;
 326                         clocks = <&clkcfg CLK_QSPI>;
 327                         status = "disabled";
 328                 };
 329
 330                 i2c0: i2c@2010a000 {
 331                         compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 332                         reg = <0x0 0x2010a000 0x0 0x1000>;
 333                         #address-cells = <1>;
 334                         #size-cells = <0>;
 335                         interrupt-parent = <&plic>;
 336                         interrupts = <58>;
 337                         clocks = <&clkcfg CLK_I2C0>;
 338                         clock-frequency = <100000>;
 339                         status = "disabled";
 340                 };
 341
 342                 i2c1: i2c@2010b000 {
 343                         compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
 344                         reg = <0x0 0x2010b000 0x0 0x1000>;
 345                         #address-cells = <1>;
 346                         #size-cells = <0>;
 347                         interrupt-parent = <&plic>;
 348                         interrupts = <61>;
 349                         clocks = <&clkcfg CLK_I2C1>;
 350                         clock-frequency = <100000>;
 351                         status = "disabled";
 352                 };
 353
 354                 mac0: ethernet@20110000 {
 355                         compatible = "cdns,macb";
 356                         reg = <0x0 0x20110000 0x0 0x2000>;
 357                         #address-cells = <1>;
 358                         #size-cells = <0>;
 359                         interrupt-parent = <&plic>;
 360                         interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
 361                         local-mac-address = [00 00 00 00 00 00];
 362                         clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
 363                         clock-names = "pclk", "hclk";
 364                         status = "disabled";
 365                 };
 366
 367                 mac1: ethernet@20112000 {
 368                         compatible = "cdns,macb";
 369                         reg = <0x0 0x20112000 0x0 0x2000>;
 370                         #address-cells = <1>;
 371                         #size-cells = <0>;
 372                         interrupt-parent = <&plic>;
 373                         interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
 374                         local-mac-address = [00 00 00 00 00 00];
 375                         clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
 376                         clock-names = "pclk", "hclk";
 377                         status = "disabled";
 378                 };
 379
 380                 gpio0: gpio@20120000 {
 381                         compatible = "microchip,mpfs-gpio";
 382                         reg = <0x0 0x20120000 0x0 0x1000>;
 383                         interrupt-parent = <&plic>;
 384                         interrupt-controller;
 385                         #interrupt-cells = <1>;
 386                         clocks = <&clkcfg CLK_GPIO0>;
 387                         gpio-controller;
 388                         #gpio-cells = <2>;
 389                         status = "disabled";
 390                 };
 391
 392                 gpio1: gpio@20121000 {
 393                         compatible = "microchip,mpfs-gpio";
 394                         reg = <0x0 0x20121000 0x0 0x1000>;
 395                         interrupt-parent = <&plic>;
 396                         interrupt-controller;
 397                         #interrupt-cells = <1>;
 398                         clocks = <&clkcfg CLK_GPIO1>;
 399                         gpio-controller;
 400                         #gpio-cells = <2>;
 401                         status = "disabled";
 402                 };
 403
 404                 gpio2: gpio@20122000 {
 405                         compatible = "microchip,mpfs-gpio";
 406                         reg = <0x0 0x20122000 0x0 0x1000>;
 407                         interrupt-parent = <&plic>;
 408                         interrupt-controller;
 409                         #interrupt-cells = <1>;
 410                         clocks = <&clkcfg CLK_GPIO2>;
 411                         gpio-controller;
 412                         #gpio-cells = <2>;
 413                         status = "disabled";
 414                 };
 415
 416                 rtc: rtc@20124000 {
 417                         compatible = "microchip,mpfs-rtc";
 418                         reg = <0x0 0x20124000 0x0 0x1000>;
 419                         interrupt-parent = <&plic>;
 420                         interrupts = <80>, <81>;
 421                         clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
 422                         clock-names = "rtc", "rtcref";
 423                         status = "disabled";
 424                 };
 425
 426                 usb: usb@20201000 {
 427                         compatible = "microchip,mpfs-musb";
 428                         reg = <0x0 0x20201000 0x0 0x1000>;
 429                         interrupt-parent = <&plic>;
 430                         interrupts = <86>, <87>;
 431                         clocks = <&clkcfg CLK_USB>;
 432                         interrupt-names = "dma","mc";
 433                         status = "disabled";
 434                 };
 435
 436                 pcie: pcie@2000000000 {
 437                         compatible = "microchip,pcie-host-1.0";
 438                         #address-cells = <0x3>;
 439                         #interrupt-cells = <0x1>;
 440                         #size-cells = <0x2>;
 441                         device_type = "pci";
 442                         reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
 443                         reg-names = "cfg", "apb";
 444                         bus-range = <0x0 0x7f>;
 445                         interrupt-parent = <&plic>;
 446                         interrupts = <119>;
 447                         interrupt-map = <0 0 0 1 &pcie_intc 0>,
 448                                         <0 0 0 2 &pcie_intc 1>,
 449                                         <0 0 0 3 &pcie_intc 2>,
 450                                         <0 0 0 4 &pcie_intc 3>;
 451                         interrupt-map-mask = <0 0 0 7>;
 452                         clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
 453                         clock-names = "fic0", "fic1", "fic3";
 454                         ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
 455                         msi-parent = <&pcie>;
 456                         msi-controller;
 457                         microchip,axi-m-atr0 = <0x10 0x0>;
 458                         status = "disabled";
 459                         pcie_intc: legacy-interrupt-controller {
 460                                 #address-cells = <0>;
 461                                 #interrupt-cells = <1>;
 462                                 interrupt-controller;
 463                         };
 464                 };
 465
 466                 mbox: mailbox@37020000 {
 467                         compatible = "microchip,mpfs-mailbox";
 468                         reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
 469                         interrupt-parent = <&plic>;
 470                         interrupts = <96>;
 471                         #mbox-cells = <1>;
 472                         status = "disabled";
 473                 };
 474         };
 475 };