1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
2 /* Copyright (c) 2020-2021 Microchip Technology Inc */
5 #include "dt-bindings/clock/microchip,mpfs-clock.h"
10 model = "Microchip PolarFire SoC";
11 compatible = "microchip,mpfs";
18 compatible = "sifive,e51", "sifive,rocket0", "riscv";
20 i-cache-block-size = <64>;
22 i-cache-size = <16384>;
24 riscv,isa = "rv64imac";
25 clocks = <&clkcfg CLK_CPU>;
28 cpu0_intc: interrupt-controller {
29 #interrupt-cells = <1>;
30 compatible = "riscv,cpu-intc";
36 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
37 d-cache-block-size = <64>;
39 d-cache-size = <32768>;
43 i-cache-block-size = <64>;
45 i-cache-size = <32768>;
48 mmu-type = "riscv,sv39";
50 riscv,isa = "rv64imafdc";
51 clocks = <&clkcfg CLK_CPU>;
55 cpu1_intc: interrupt-controller {
56 #interrupt-cells = <1>;
57 compatible = "riscv,cpu-intc";
63 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
64 d-cache-block-size = <64>;
66 d-cache-size = <32768>;
70 i-cache-block-size = <64>;
72 i-cache-size = <32768>;
75 mmu-type = "riscv,sv39";
77 riscv,isa = "rv64imafdc";
78 clocks = <&clkcfg CLK_CPU>;
82 cpu2_intc: interrupt-controller {
83 #interrupt-cells = <1>;
84 compatible = "riscv,cpu-intc";
90 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
91 d-cache-block-size = <64>;
93 d-cache-size = <32768>;
97 i-cache-block-size = <64>;
99 i-cache-size = <32768>;
102 mmu-type = "riscv,sv39";
104 riscv,isa = "rv64imafdc";
105 clocks = <&clkcfg CLK_CPU>;
109 cpu3_intc: interrupt-controller {
110 #interrupt-cells = <1>;
111 compatible = "riscv,cpu-intc";
112 interrupt-controller;
117 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
118 d-cache-block-size = <64>;
120 d-cache-size = <32768>;
124 i-cache-block-size = <64>;
126 i-cache-size = <32768>;
129 mmu-type = "riscv,sv39";
131 riscv,isa = "rv64imafdc";
132 clocks = <&clkcfg CLK_CPU>;
135 cpu4_intc: interrupt-controller {
136 #interrupt-cells = <1>;
137 compatible = "riscv,cpu-intc";
138 interrupt-controller;
168 compatible = "fixed-clock";
172 syscontroller: syscontroller {
173 compatible = "microchip,mpfs-sys-controller";
178 #address-cells = <2>;
180 compatible = "simple-bus";
183 cctrllr: cache-controller@2010000 {
184 compatible = "sifive,fu540-c000-ccache", "cache";
185 reg = <0x0 0x2010000 0x0 0x1000>;
186 cache-block-size = <64>;
189 cache-size = <2097152>;
191 interrupt-parent = <&plic>;
192 interrupts = <1>, <2>, <3>;
195 clint: clint@2000000 {
196 compatible = "sifive,fu540-c000-clint", "sifive,clint0";
197 reg = <0x0 0x2000000 0x0 0xC000>;
198 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
199 <&cpu1_intc 3>, <&cpu1_intc 7>,
200 <&cpu2_intc 3>, <&cpu2_intc 7>,
201 <&cpu3_intc 3>, <&cpu3_intc 7>,
202 <&cpu4_intc 3>, <&cpu4_intc 7>;
205 plic: interrupt-controller@c000000 {
206 compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
207 reg = <0x0 0xc000000 0x0 0x4000000>;
208 #address-cells = <0>;
209 #interrupt-cells = <1>;
210 interrupt-controller;
211 interrupts-extended = <&cpu0_intc 11>,
212 <&cpu1_intc 11>, <&cpu1_intc 9>,
213 <&cpu2_intc 11>, <&cpu2_intc 9>,
214 <&cpu3_intc 11>, <&cpu3_intc 9>,
215 <&cpu4_intc 11>, <&cpu4_intc 9>;
219 clkcfg: clkcfg@20002000 {
220 compatible = "microchip,mpfs-clkcfg";
221 reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
226 mmuart0: serial@20000000 {
227 compatible = "ns16550a";
228 reg = <0x0 0x20000000 0x0 0x400>;
231 interrupt-parent = <&plic>;
233 current-speed = <115200>;
234 clocks = <&clkcfg CLK_MMUART0>;
235 status = "disabled"; /* Reserved for the HSS */
238 mmuart1: serial@20100000 {
239 compatible = "ns16550a";
240 reg = <0x0 0x20100000 0x0 0x400>;
243 interrupt-parent = <&plic>;
245 current-speed = <115200>;
246 clocks = <&clkcfg CLK_MMUART1>;
250 mmuart2: serial@20102000 {
251 compatible = "ns16550a";
252 reg = <0x0 0x20102000 0x0 0x400>;
255 interrupt-parent = <&plic>;
257 current-speed = <115200>;
258 clocks = <&clkcfg CLK_MMUART2>;
262 mmuart3: serial@20104000 {
263 compatible = "ns16550a";
264 reg = <0x0 0x20104000 0x0 0x400>;
267 interrupt-parent = <&plic>;
269 current-speed = <115200>;
270 clocks = <&clkcfg CLK_MMUART3>;
274 mmuart4: serial@20106000 {
275 compatible = "ns16550a";
276 reg = <0x0 0x20106000 0x0 0x400>;
279 interrupt-parent = <&plic>;
281 clocks = <&clkcfg CLK_MMUART4>;
282 current-speed = <115200>;
286 /* Common node entry for emmc/sd */
288 compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
289 reg = <0x0 0x20008000 0x0 0x1000>;
290 interrupt-parent = <&plic>;
292 clocks = <&clkcfg CLK_MMC>;
293 max-frequency = <200000000>;
298 compatible = "microchip,mpfs-spi";
299 #address-cells = <1>;
301 reg = <0x0 0x20108000 0x0 0x1000>;
302 interrupt-parent = <&plic>;
304 clocks = <&clkcfg CLK_SPI0>;
309 compatible = "microchip,mpfs-spi";
310 #address-cells = <1>;
312 reg = <0x0 0x20109000 0x0 0x1000>;
313 interrupt-parent = <&plic>;
315 clocks = <&clkcfg CLK_SPI1>;
320 compatible = "microchip,mpfs-qspi";
321 #address-cells = <1>;
323 reg = <0x0 0x21000000 0x0 0x1000>;
324 interrupt-parent = <&plic>;
326 clocks = <&clkcfg CLK_QSPI>;
331 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
332 reg = <0x0 0x2010a000 0x0 0x1000>;
333 #address-cells = <1>;
335 interrupt-parent = <&plic>;
337 clocks = <&clkcfg CLK_I2C0>;
338 clock-frequency = <100000>;
343 compatible = "microchip,mpfs-i2c", "microchip,corei2c-rtl-v7";
344 reg = <0x0 0x2010b000 0x0 0x1000>;
345 #address-cells = <1>;
347 interrupt-parent = <&plic>;
349 clocks = <&clkcfg CLK_I2C1>;
350 clock-frequency = <100000>;
354 mac0: ethernet@20110000 {
355 compatible = "cdns,macb";
356 reg = <0x0 0x20110000 0x0 0x2000>;
357 #address-cells = <1>;
359 interrupt-parent = <&plic>;
360 interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
361 local-mac-address = [00 00 00 00 00 00];
362 clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
363 clock-names = "pclk", "hclk";
367 mac1: ethernet@20112000 {
368 compatible = "cdns,macb";
369 reg = <0x0 0x20112000 0x0 0x2000>;
370 #address-cells = <1>;
372 interrupt-parent = <&plic>;
373 interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
374 local-mac-address = [00 00 00 00 00 00];
375 clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
376 clock-names = "pclk", "hclk";
380 gpio0: gpio@20120000 {
381 compatible = "microchip,mpfs-gpio";
382 reg = <0x0 0x20120000 0x0 0x1000>;
383 interrupt-parent = <&plic>;
384 interrupt-controller;
385 #interrupt-cells = <1>;
386 clocks = <&clkcfg CLK_GPIO0>;
392 gpio1: gpio@20121000 {
393 compatible = "microchip,mpfs-gpio";
394 reg = <0x0 0x20121000 0x0 0x1000>;
395 interrupt-parent = <&plic>;
396 interrupt-controller;
397 #interrupt-cells = <1>;
398 clocks = <&clkcfg CLK_GPIO1>;
404 gpio2: gpio@20122000 {
405 compatible = "microchip,mpfs-gpio";
406 reg = <0x0 0x20122000 0x0 0x1000>;
407 interrupt-parent = <&plic>;
408 interrupt-controller;
409 #interrupt-cells = <1>;
410 clocks = <&clkcfg CLK_GPIO2>;
417 compatible = "microchip,mpfs-rtc";
418 reg = <0x0 0x20124000 0x0 0x1000>;
419 interrupt-parent = <&plic>;
420 interrupts = <80>, <81>;
421 clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>;
422 clock-names = "rtc", "rtcref";
427 compatible = "microchip,mpfs-musb";
428 reg = <0x0 0x20201000 0x0 0x1000>;
429 interrupt-parent = <&plic>;
430 interrupts = <86>, <87>;
431 clocks = <&clkcfg CLK_USB>;
432 interrupt-names = "dma","mc";
436 pcie: pcie@2000000000 {
437 compatible = "microchip,pcie-host-1.0";
438 #address-cells = <0x3>;
439 #interrupt-cells = <0x1>;
442 reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
443 reg-names = "cfg", "apb";
444 bus-range = <0x0 0x7f>;
445 interrupt-parent = <&plic>;
447 interrupt-map = <0 0 0 1 &pcie_intc 0>,
448 <0 0 0 2 &pcie_intc 1>,
449 <0 0 0 3 &pcie_intc 2>,
450 <0 0 0 4 &pcie_intc 3>;
451 interrupt-map-mask = <0 0 0 7>;
452 clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>;
453 clock-names = "fic0", "fic1", "fic3";
454 ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
455 msi-parent = <&pcie>;
457 microchip,axi-m-atr0 = <0x10 0x0>;
459 pcie_intc: legacy-interrupt-controller {
460 #address-cells = <0>;
461 #interrupt-cells = <1>;
462 interrupt-controller;
466 mbox: mailbox@37020000 {
467 compatible = "microchip,mpfs-mailbox";
468 reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
469 interrupt-parent = <&plic>;